JPH01145693A - Data driver for matrix type display - Google Patents

Abstract

PURPOSE: To enable driving while lowering the transfer frequency of (n) pieces of shift registers by parallelly providing the respective shift registers and transferring data parallelly for (n) bits per horizontal scanning term H. CONSTITUTION: Shift registers 11 -14 provided corresponding to parallel transfer data I-IV of four bits per H shift the transfer data. Then, the outputs of the shift registers 11 -14 are successively switched and selected by a switching and selecting means 7 and during 1H term, the data of four bits are successively supplied to the data side electrode of a display 3. Since the transfer data are transferred parallelly for 4 bits per H in this case, the number of transfer frequencies of the respective shift registers is reduced into 1/4 in comparison with the conventional case. Thus, the display having comparatively a lot of picture elements can be driven while lowering the frequency of data transfer to a data driver.

Description

[Detailed Description of the Invention] [Summary] A matrix type display that supplies data necessary for displaying halftones (gradations) on a matrix type display such as an AC type PDP (plasma display panel). Regarding the data driver, the purpose is to drive a display with a relatively large number of pixels by lowering the data transfer frequency to the data driver, and the transfer data is parallel transfer data of multiple bits per horizontal scanning period, and the parallel transfer data is A plurality of shift registers are provided in parallel corresponding to the parallel transfer data, and each parallel output of each shift register is sequentially switched and selected to sequentially transfer the plurality of bits of data per horizontal scanning period to the matrix display. The configuration includes a switching selection means for supplying data to the data side type 1 group.

[Industrial application field]

The present invention relates to a data driver for a matrix type display, such as an AC type PDP, which supplies data necessary for displaying halftones to the display.

As mentioned above, especially when making an interlocutory hearing, the general
Unlike value display, it is necessary to use n-bit data. In this case, the current limit for the data transfer frequency to the data driver is about 16M1-1z to 20MHz, and from this current situation, it is desirable that the data transfer frequency be lower.

[Conventional technology]

An intra-field time division method is known as a method for displaying halftones on AC type PDPs and the like. If the number of pixels on the display is, for example, 640 (horizontal = data side) x 400 (vertical = scanning side), for general binary display, 640 (pixels) of data can be transferred per horizontal scanning period (1H). However, in the case of halftone display using the intra-field time division method (for example, 4 bits for 16 halftones), data of 4 (pips 1~) x 640 (pixels) per 1H is displayed as shown in Figure 7. Must be transferred serially. In Figure 7, H8
YNC is a horizontal synchronizing signal, and ① to IV are 4-bit serial transfer data, indicating the weight of the intermediate tone. - On the other hand, a schematic representation of the weight of halftones in terms of time length and the vertical scanning line (electrode) N of the display.

Figure 8 shows the relationship between In FIG. 8, the vertical axis is the scanning tl
ANa, the horizontal axis indicates the scanning time for one field (one screen).

Here, to explain the data format with reference to FIGS. 7 and 8, during the first 1H period, the first bit
The data for the line is 640 pixels, and the second bit ■ is the first
The 97th line data contains 640 pixels, the 3rd bit (■) contains 640 pixels of 189th line data, and the 4th bit I (1) contains 640 pixels of 173rd line data. The 1H period is also structured in accordance with this.

In other words, in the first 1H period, the 1st, 197th, and 189th
, the pixel data of each 173rd line is sent, and the next 1H
The second, 198th, . . . pixel data are sent during the period.

FIG. 9 shows a block diagram of a conventional data driver. Serial transfer data of 4 bits per 1H as explained in Fig. 7 is transferred to shift register 1 by the shift clock.
The data taken in and output from the shift register 1 is latched by the latch 2 and then supplied to the display 3, where halftone display is performed based on the transferred data.

In this case, since the intra-field time division method is used, 2
In the case of 1 halftone (n bits), it is necessary to serially transfer data 0 times in 1H.

[Problem that the invention seeks to solve]

For example, set the number of pixels of the display to 640 (horizontal) x 400 (
In the case of vertical), the data transfer rate is about 16 MHz for binary display with n=1, and in a normal display in which the data electrode is divided into two and taken out at the top and bottom, it is 8 MHz each.

However, the above-mentioned halftone display requires multiple bits, and for example, when n-4 (16 halftones) is displayed, the data transfer rate is approximately 32Mf-Iz, and as the number of halftones and pixels increases, the data transfer rate decreases. It gets even faster.

However, with current technology, the data transfer speed to the data driver is limited to about 16MHz to 20Ml-1z, and even if higher speeds are developed in the future, increased power consumption will be a problem, so the above-mentioned 640 (horizontal)
There was a problem that it could not be applied to a display with a relatively large number of pixels such as 400 (vertical).

SUMMARY OF THE INVENTION An object of the present invention is to provide a data driver for a matrix type display that can drive a display with a relatively large number of pixels by lowering the data transfer frequency to the data driver.

[Means for solving problems]

FIG. 1 shows a diagram of the principle of the present invention. In the figure, ■ to ■ are parallel transfer data of a plurality of bits per day. 11-1
Numeral 4 is a shift register for shifting the parallel transfer data, and a plurality of shift registers are provided in parallel corresponding to the parallel transfer data. Reference numeral 7 denotes a switching selection means which sequentially switches and selects each parallel output of each shift register to sequentially supply the plurality of bits of data per 1H to the data-side electrode group of the matrix display 3.

[Operation] Transfer data is shifted in shift registers 11-14 provided corresponding to 4-bit parallel transfer data E-IV per day. The outputs of the shift registers 11 to 14 are sequentially switched and selected by the switching and selecting means 7 to sequentially supply 4-bit data to the data side electrode of the display 3 during one day. In this case, since the transfer data is transferred in parallel at 4 bits per 1H, the transfer frequency of each shift register can be reduced to 1/4 of that of the conventional one.

〔Example〕

FIG. 2 shows a block diagram of a first embodiment of a data driver according to the present invention. In the figure, shift registers 11 to 14 are provided in parallel corresponding to transfer data 1 to 2, which will be described later, respectively, and shift the transfer data E to 2, respectively. 21
-24 are latches, which are provided corresponding to the shift registers 11-14, respectively, and latch the respective outputs of the shift registers 11-14. Reference numerals 4a, 4b, . . . are changeover switches which time-divisionally switch and take out the respective outputs of the latches 21 to 24 per 1H.

Here, the transferred data is H3 shown in FIG. 3(A).
The transfer data of bits 1 to bit IV (Fig. 3 (B)) consisting of 640 pixel data per 1H of YNC is input in parallel (in other words, n-bit parallel data is input per 11-1). ing. Therefore, the transfer data frequency is 1/n of the conventional transfer frequency explained in FIG.

In FIG. 2, data E to ■ are respectively shift register 1.
1 to 14 and are shifted, and latched by latches 21 to 24 at the timing of the latch signal shown in FIG. 3(C). The data output from latches 21 to 24 is
Switches 4a, 4b, . Supplied.

In this way, a plurality (n) of shift registers 11 to 14 are provided in parallel in the data driver to transfer data n per 1H.
Since the bits are transferred in parallel, the transfer frequency of each shift register 11 to 14 is only 1/n of the conventional one, and therefore it can be used even on a relatively large display with 640 (horizontal) x 400 (vertical) pixels. Fully applicable.

FIG. 4 shows a block diagram of a second embodiment of the present invention, in which the same parts as those in FIG. 2 are given the same numbers and their explanations will be omitted. In the figure, 5 is a latch, and switches 4a and 4b
, . . . The latching is performed at the same timing as the switching timing.

The transferred data in this case is 1 as shown in FIG. 5(B).
Parallel data 1 to ■ of 4 bits per day is 1H n(
=4) It is configured such that inputs are made at sequentially shifted timings during equally divided periods. This one only requires one latch.

In FIG. 4, data E to ■ are respectively shift register 1.
1 to 14 and are shifted and output by switches 4a, 4b, . . . which are switched at the same timing as the latch signal shown in FIG. 5(D). The outputs of the switches 4a, 4b, ... are outputted by the latch 5 as shown in Fig. 5(D).
It is latched at the timing of the latch signal shown in Figure 5 (
The data is converted to 4 bits per day as shown in C) and is supplied to the data side electrode of the display 3.

In this embodiment, as in the previous embodiment, the data is n per 1H.
Since the bits are transferred in parallel, the transfer frequency can be reduced to 1/n of that of the conventional method.

In each of the embodiments described above, n shift registers are provided for n bits, but if the transfer frequency permits, the number of shift registers may be (n/2). This transfers data in both serial and parallel formats, as shown in FIG. The data of I[ is supplied to the shift register 61, and the data of bits ■ and ■ are supplied to the shift register 62, respectively.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of (n) shift registers are provided in parallel and data is transferred in parallel at n bits per 1H, so the transfer frequency of each shift register is 1/2 compared to the conventional one. /n, so for example 640 (horizontal) x 4o.

A relatively large display having a number of pixels such as (vertical) can also be sufficiently applied.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention, FIGS. 2 and 3 are block diagrams and operation timing charts of the first embodiment of the present invention, and FIGS. 4 and 5 are diagrams of the second embodiment of the present invention, respectively. Example block diagram and its operation timing chart, FIG. 6 is a diagram explaining another embodiment of the present invention, FIG. 7 is a diagram showing the transfer data by the intra-field time division method, FIG. 8 is the transfer data 9 is a conventional block diagram. In the figure, 11 to 1a, 6+, and 62 are shift registers, and 21 to 1a are shift registers.
24 and 5 are latches, 3 is a display, 4a, 4b, . . . are switches, and 7 is a switching selection means. Block diagram of the first embodiment of the present invention FIG. 2 Operation timing chart of the block diagram shown in FIG. 2 Third
Figure 5: Block diagram of the second embodiment of the present invention; Operation timing chart of the block diagram shown in Figure 4;
FIG. 6 is a diagram illustrating another embodiment of the present invention! H-th 28th-th Figure 17 shows the transfer data using the intra-field time division method.

Claims (1)

[Claims] Transfer data is parallel transfer data (I, II, III, IV) of multiple bits per horizontal scanning period, and shift registers (1_1 to 1_4) for shifting the parallel transfer data (I, II, III, IV) are assigned. A plurality of shift registers (1_1 to 1_1 to
1_4) is provided with switching selection means (7) which sequentially switches and selects each of the parallel outputs to sequentially supply the plurality of bits of data to the data-side electrode group of the matrix display (3) per horizontal scanning period. Data driver for matrix type display.