JPH01120343U - - Google Patents

Info

Publication number
JPH01120343U
JPH01120343U JP1988016778U JP1677888U JPH01120343U JP H01120343 U JPH01120343 U JP H01120343U JP 1988016778 U JP1988016778 U JP 1988016778U JP 1677888 U JP1677888 U JP 1677888U JP H01120343 U JPH01120343 U JP H01120343U
Authority
JP
Japan
Prior art keywords
resin
sealed
semiconductor pellet
semiconductor device
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988016778U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988016778U priority Critical patent/JPH01120343U/ja
Publication of JPH01120343U publication Critical patent/JPH01120343U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図はこの考案の第1の実施例を示す要部拡
大縦断面図である。第2図はこの考案の第2の実
施例を示す要部拡大縦断面図である。第3図及び
第4図はこの考案の第3の実施例を示し、第3図
は平面図、第4図は要部拡大縦断面図である。第
5図及び第6図はこの考案の第4の実施例を示し
、第5図は平面図、第6図は要部拡大縦断面図で
ある。第7図は樹脂封止型半導体装置の従来例を
示す要部拡大縦断面図である。第8図は、第7図
の樹脂封止型半導体装置の製造に使用するリード
フレームの平面図である。 11…基板、12…リード、13…半導体ペレ
ツト、14…金属細線、15…緩衝層、16…樹
脂パツケージ。

Claims (1)

  1. 【実用新案登録請求の範囲】 放熱板上にマウントした半導体ペレツトと、一
    端を半導体ペレツト近傍に配置したリードとを金
    属細線で電気的に接続し、基板の全面を樹脂にて
    封止した半導体装置に於いて、 上記放熱板の半導体ペレツト非マウント面可撓
    性を有する緩衝層を設けたことを特徴とする樹脂
    封止型半導体装置。
JP1988016778U 1988-02-09 1988-02-09 Pending JPH01120343U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988016778U JPH01120343U (ja) 1988-02-09 1988-02-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988016778U JPH01120343U (ja) 1988-02-09 1988-02-09

Publications (1)

Publication Number Publication Date
JPH01120343U true JPH01120343U (ja) 1989-08-15

Family

ID=31229998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988016778U Pending JPH01120343U (ja) 1988-02-09 1988-02-09

Country Status (1)

Country Link
JP (1) JPH01120343U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009295712A (ja) * 2008-06-04 2009-12-17 Denso Corp 基板および電子装置の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58440B2 (ja) * 1971-11-20 1983-01-06 フエルナオ・アウグスト・デ・アラウ−ホ・ヴイセンテ 17,21−ジヒドロキシ−20−ケトプレグナン類の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58440B2 (ja) * 1971-11-20 1983-01-06 フエルナオ・アウグスト・デ・アラウ−ホ・ヴイセンテ 17,21−ジヒドロキシ−20−ケトプレグナン類の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009295712A (ja) * 2008-06-04 2009-12-17 Denso Corp 基板および電子装置の製造方法

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