JP7845375B2 - メモリ回路 - Google Patents

メモリ回路

Info

Publication number
JP7845375B2
JP7845375B2 JP2023562054A JP2023562054A JP7845375B2 JP 7845375 B2 JP7845375 B2 JP 7845375B2 JP 2023562054 A JP2023562054 A JP 2023562054A JP 2023562054 A JP2023562054 A JP 2023562054A JP 7845375 B2 JP7845375 B2 JP 7845375B2
Authority
JP
Japan
Prior art keywords
memory
control unit
signal
memory group
mcnt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2023562054A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2023089778A1 (https=
Inventor
竜志 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Socionext Inc filed Critical Socionext Inc
Publication of JPWO2023089778A1 publication Critical patent/JPWO2023089778A1/ja
Application granted granted Critical
Publication of JP7845375B2 publication Critical patent/JP7845375B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP2023562054A 2021-11-19 2021-11-19 メモリ回路 Active JP7845375B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/042634 WO2023089778A1 (ja) 2021-11-19 2021-11-19 メモリ回路

Publications (2)

Publication Number Publication Date
JPWO2023089778A1 JPWO2023089778A1 (https=) 2023-05-25
JP7845375B2 true JP7845375B2 (ja) 2026-04-14

Family

ID=86396469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023562054A Active JP7845375B2 (ja) 2021-11-19 2021-11-19 メモリ回路

Country Status (4)

Country Link
US (1) US20240295973A1 (https=)
JP (1) JP7845375B2 (https=)
CN (1) CN118251724A (https=)
WO (1) WO2023089778A1 (https=)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006065697A (ja) 2004-08-27 2006-03-09 Hitachi Ltd 記憶デバイス制御装置
JP2010501916A (ja) 2006-08-22 2010-01-21 モサイド・テクノロジーズ・インコーポレーテッド スケーラブルメモリシステム
JP2010514017A (ja) 2006-12-20 2010-04-30 モサイド・テクノロジーズ・インコーポレーテッド 揮発性メモリおよび不揮発性メモリを有するハイブリッド固体メモリシステム
JP2012504263A (ja) 2008-09-30 2012-02-16 モサイド・テクノロジーズ・インコーポレーテッド 出力遅延調整によるシリアル接続のメモリシステム

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8407395B2 (en) * 2006-08-22 2013-03-26 Mosaid Technologies Incorporated Scalable memory system
US10764455B2 (en) * 2018-12-31 2020-09-01 Kyocera Document Solutions Inc. Memory control method, memory control apparatus, and image forming method that uses memory control method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006065697A (ja) 2004-08-27 2006-03-09 Hitachi Ltd 記憶デバイス制御装置
JP2010501916A (ja) 2006-08-22 2010-01-21 モサイド・テクノロジーズ・インコーポレーテッド スケーラブルメモリシステム
JP2010514017A (ja) 2006-12-20 2010-04-30 モサイド・テクノロジーズ・インコーポレーテッド 揮発性メモリおよび不揮発性メモリを有するハイブリッド固体メモリシステム
JP2012504263A (ja) 2008-09-30 2012-02-16 モサイド・テクノロジーズ・インコーポレーテッド 出力遅延調整によるシリアル接続のメモリシステム

Also Published As

Publication number Publication date
US20240295973A1 (en) 2024-09-05
CN118251724A (zh) 2024-06-25
JPWO2023089778A1 (https=) 2023-05-25
WO2023089778A1 (ja) 2023-05-25

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