JP7827393B2 - ３次元チップレット形成のための局所的応力領域 - Google Patents

３次元チップレット形成のための局所的応力領域

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Publication number
JP7827393B2
JP7827393B2 JP2023544627A JP2023544627A JP7827393B2 JP 7827393 B2 JP7827393 B2 JP 7827393B2 JP 2023544627 A JP2023544627 A JP 2023544627A JP 2023544627 A JP2023544627 A JP 2023544627A JP 7827393 B2 JP7827393 B2 JP 7827393B2
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JP
Japan
Prior art keywords
stress film
semiconductor structure
chiplet
patterned
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2023544627A
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English (en)
Japanese (ja)
Other versions
JP2024504999A (ja
JP2024504999A5 (https=
Inventor
デヴィリアーズ，アントン
フルフォード，ダニエル
シェピス，アンソニー
ガードナー，マーク
フルフォード，エイチ．ジム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
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Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of JP2024504999A publication Critical patent/JP2024504999A/ja
Publication of JP2024504999A5 publication Critical patent/JP2024504999A5/ja
Application granted granted Critical
Publication of JP7827393B2 publication Critical patent/JP7827393B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/211—Direct bonding of chips, wafers or substrates using auxiliary members, e.g. aids for protecting the bonding area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Formation Of Insulating Films (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
JP2023544627A 2021-01-26 2022-01-19 ３次元チップレット形成のための局所的応力領域 Active JP7827393B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202163141553P 2021-01-26 2021-01-26
US202163141552P 2021-01-26 2021-01-26
US63/141,552 2021-01-26
US63/141,553 2021-01-26
PCT/US2022/012923 WO2022164693A1 (en) 2021-01-26 2022-01-19 Localized stress regions for three-dimension chiplet formation

Publications (3)

Publication Number Publication Date
JP2024504999A JP2024504999A (ja) 2024-02-02
JP2024504999A5 JP2024504999A5 (https=) 2024-10-31
JP7827393B2 true JP7827393B2 (ja) 2026-03-10

Family

ID=82654872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023544627A Active JP7827393B2 (ja) 2021-01-26 2022-01-19 ３次元チップレット形成のための局所的応力領域

Country Status (4)

Country Link
JP (1) JP7827393B2 (https=)
KR (1) KR102937484B1 (https=)
TW (1) TWI905370B (https=)
WO (1) WO2022164693A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250087600A1 (en) * 2023-09-12 2025-03-13 Macronix International Co., Ltd. Semiconductor bonded structure and fabricating method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090085228A1 (en) 2007-09-27 2009-04-02 Haixiao Sun Die warpage control
US20100102435A1 (en) 2008-10-28 2010-04-29 Advanced Micro Devices, Inc. Method and apparatus for reducing semiconductor package tensile stress
US20140357051A1 (en) 2013-05-28 2014-12-04 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Method for forming radio frequency device
US20160379935A1 (en) 2015-06-24 2016-12-29 Inotera Memories, Inc. Wafer level package and fabrication method thereof
JP2017503341A (ja) 2013-12-03 2017-01-26 インヴェンサス・コーポレイション 電気回路機構を有する構造体内の反りの低減
US20190252328A1 (en) 2006-05-16 2019-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of Manufacturing an Integrated Circuit Having Stress Tuning Layer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201701429A (zh) * 2015-06-24 2017-01-01 華亞科技股份有限公司 晶圓級封裝及其製作方法
TWI652774B (zh) * 2017-03-03 2019-03-01 Siliconware Precision Industries Co., Ltd. 電子封裝件之製法
US10840227B2 (en) * 2017-11-02 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190252328A1 (en) 2006-05-16 2019-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of Manufacturing an Integrated Circuit Having Stress Tuning Layer
US20090085228A1 (en) 2007-09-27 2009-04-02 Haixiao Sun Die warpage control
US20100102435A1 (en) 2008-10-28 2010-04-29 Advanced Micro Devices, Inc. Method and apparatus for reducing semiconductor package tensile stress
US20140357051A1 (en) 2013-05-28 2014-12-04 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Method for forming radio frequency device
JP2017503341A (ja) 2013-12-03 2017-01-26 インヴェンサス・コーポレイション 電気回路機構を有する構造体内の反りの低減
US20160379935A1 (en) 2015-06-24 2016-12-29 Inotera Memories, Inc. Wafer level package and fabrication method thereof

Also Published As

Publication number Publication date
JP2024504999A (ja) 2024-02-02
TWI905370B (zh) 2025-11-21
KR102937484B1 (ko) 2026-03-11
TW202247259A (zh) 2022-12-01
WO2022164693A1 (en) 2022-08-04
KR20230137370A (ko) 2023-10-04

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