KR102937484B1 - 3차원 칩렛 형성을 위한 국부화된 응력 영역 - Google Patents

3차원 칩렛 형성을 위한 국부화된 응력 영역

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Publication number
KR102937484B1
KR102937484B1 KR1020237028211A KR20237028211A KR102937484B1 KR 102937484 B1 KR102937484 B1 KR 102937484B1 KR 1020237028211 A KR1020237028211 A KR 1020237028211A KR 20237028211 A KR20237028211 A KR 20237028211A KR 102937484 B1 KR102937484 B1 KR 102937484B1
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KR
South Korea
Prior art keywords
stress film
semiconductor structure
chiplet
patterned
delete delete
Prior art date
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Application number
KR1020237028211A
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English (en)
Korean (ko)
Other versions
KR20230137370A (ko
Inventor
안톤 데빌리어스
다니엘 풀포드
앤서니 셰피스
마크 가드너
에이치 짐 풀포드
Original Assignee
도쿄엘렉트론가부시키가이샤
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Publication of KR20230137370A publication Critical patent/KR20230137370A/ko
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Publication of KR102937484B1 publication Critical patent/KR102937484B1/ko
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/211—Direct bonding of chips, wafers or substrates using auxiliary members, e.g. aids for protecting the bonding area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H01L2924/10158—
    • H01L2924/3511—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Formation Of Insulating Films (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
KR1020237028211A 2021-01-26 2022-01-19 3차원 칩렛 형성을 위한 국부화된 응력 영역 Active KR102937484B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202163141553P 2021-01-26 2021-01-26
US202163141552P 2021-01-26 2021-01-26
US63/141,552 2021-01-26
US63/141,553 2021-01-26
PCT/US2022/012923 WO2022164693A1 (en) 2021-01-26 2022-01-19 Localized stress regions for three-dimension chiplet formation

Publications (2)

Publication Number Publication Date
KR20230137370A KR20230137370A (ko) 2023-10-04
KR102937484B1 true KR102937484B1 (ko) 2026-03-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020237028211A Active KR102937484B1 (ko) 2021-01-26 2022-01-19 3차원 칩렛 형성을 위한 국부화된 응력 영역

Country Status (4)

Country Link
JP (1) JP7827393B2 (https=)
KR (1) KR102937484B1 (https=)
TW (1) TWI905370B (https=)
WO (1) WO2022164693A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250087600A1 (en) * 2023-09-12 2025-03-13 Macronix International Co., Ltd. Semiconductor bonded structure and fabricating method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090085228A1 (en) * 2007-09-27 2009-04-02 Haixiao Sun Die warpage control
US20180254232A1 (en) * 2017-03-03 2018-09-06 Siliconware Precision Industries Co., Ltd. Electronic package and method for manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US8212346B2 (en) * 2008-10-28 2012-07-03 Global Foundries, Inc. Method and apparatus for reducing semiconductor package tensile stress
CN103296013B (zh) * 2013-05-28 2017-08-08 上海华虹宏力半导体制造有限公司 射频器件的形成方法
US9397051B2 (en) * 2013-12-03 2016-07-19 Invensas Corporation Warpage reduction in structures with electrical circuitry
US9761540B2 (en) * 2015-06-24 2017-09-12 Micron Technology, Inc. Wafer level package and fabrication method thereof
TW201701429A (zh) * 2015-06-24 2017-01-01 華亞科技股份有限公司 晶圓級封裝及其製作方法
US10840227B2 (en) * 2017-11-02 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090085228A1 (en) * 2007-09-27 2009-04-02 Haixiao Sun Die warpage control
US20180254232A1 (en) * 2017-03-03 2018-09-06 Siliconware Precision Industries Co., Ltd. Electronic package and method for manufacturing the same

Also Published As

Publication number Publication date
JP2024504999A (ja) 2024-02-02
JP7827393B2 (ja) 2026-03-10
TWI905370B (zh) 2025-11-21
TW202247259A (zh) 2022-12-01
WO2022164693A1 (en) 2022-08-04
KR20230137370A (ko) 2023-10-04

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