TWI905370B - 用於三維小晶片形成的局部應力區域 - Google Patents

用於三維小晶片形成的局部應力區域

Info

Publication number
TWI905370B
TWI905370B TW111102830A TW111102830A TWI905370B TW I905370 B TWI905370 B TW I905370B TW 111102830 A TW111102830 A TW 111102830A TW 111102830 A TW111102830 A TW 111102830A TW I905370 B TWI905370 B TW I905370B
Authority
TW
Taiwan
Prior art keywords
stress film
semiconductor structure
stress
patterned
wafer
Prior art date
Application number
TW111102830A
Other languages
English (en)
Chinese (zh)
Other versions
TW202247259A (zh
Inventor
安東 Ｊ 德維利耶
丹尼爾 富爾福德
安東尼 Ｒ 舍皮斯
馬克 Ｉ 加德納
Ｈ 吉姆 富爾福德
Original Assignee
日商東京威力科創股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東京威力科創股份有限公司 filed Critical 日商東京威力科創股份有限公司
Publication of TW202247259A publication Critical patent/TW202247259A/zh
Application granted granted Critical
Publication of TWI905370B publication Critical patent/TWI905370B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/211—Direct bonding of chips, wafers or substrates using auxiliary members, e.g. aids for protecting the bonding area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Formation Of Insulating Films (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
TW111102830A 2021-01-26 2022-01-24 用於三維小晶片形成的局部應力區域 TWI905370B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202163141553P 2021-01-26 2021-01-26
US202163141552P 2021-01-26 2021-01-26
US63/141,552 2021-01-26
US63/141,553 2021-01-26

Publications (2)

Publication Number Publication Date
TW202247259A TW202247259A (zh) 2022-12-01
TWI905370B true TWI905370B (zh) 2025-11-21

Family

ID=82654872

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111102830A TWI905370B (zh) 2021-01-26 2022-01-24 用於三維小晶片形成的局部應力區域

Country Status (4)

Country Link
JP (1) JP7827393B2 (https=)
KR (1) KR102937484B1 (https=)
TW (1) TWI905370B (https=)
WO (1) WO2022164693A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250087600A1 (en) * 2023-09-12 2025-03-13 Macronix International Co., Ltd. Semiconductor bonded structure and fabricating method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7675182B2 (en) * 2007-09-27 2010-03-09 Intel Corporation Die warpage control
TW201701429A (zh) * 2015-06-24 2017-01-01 華亞科技股份有限公司 晶圓級封裝及其製作方法
TWI683398B (zh) * 2017-11-02 2020-01-21 台灣積體電路製造股份有限公司 半導體封裝體及其形成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US8212346B2 (en) * 2008-10-28 2012-07-03 Global Foundries, Inc. Method and apparatus for reducing semiconductor package tensile stress
CN103296013B (zh) * 2013-05-28 2017-08-08 上海华虹宏力半导体制造有限公司 射频器件的形成方法
US9397051B2 (en) * 2013-12-03 2016-07-19 Invensas Corporation Warpage reduction in structures with electrical circuitry
US9761540B2 (en) * 2015-06-24 2017-09-12 Micron Technology, Inc. Wafer level package and fabrication method thereof
TWI652774B (zh) * 2017-03-03 2019-03-01 Siliconware Precision Industries Co., Ltd. 電子封裝件之製法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7675182B2 (en) * 2007-09-27 2010-03-09 Intel Corporation Die warpage control
TW201701429A (zh) * 2015-06-24 2017-01-01 華亞科技股份有限公司 晶圓級封裝及其製作方法
TWI683398B (zh) * 2017-11-02 2020-01-21 台灣積體電路製造股份有限公司 半導體封裝體及其形成方法

Also Published As

Publication number Publication date
JP2024504999A (ja) 2024-02-02
JP7827393B2 (ja) 2026-03-10
KR102937484B1 (ko) 2026-03-11
TW202247259A (zh) 2022-12-01
WO2022164693A1 (en) 2022-08-04
KR20230137370A (ko) 2023-10-04

Similar Documents

Publication Publication Date Title
TWI628715B (zh) 特徵尺寸縮減技術（二）
TWI614805B (zh) 結合不同圖案材料的光微影技術
US6946384B2 (en) Stacked device underfill and a method of fabrication
TWI469229B (zh) 製造積體電路系統的方法
US6180512B1 (en) Single-mask dual damascene processes by using phase-shifting mask
US8933540B2 (en) Thermal via for 3D integrated circuits structures
CN108780777A (zh) 利用选择性沉积对金属和通孔进行自对准
CN100590789C (zh) 制造微电子元件的方法
CN109755107B (zh) 自对准双重图案方法
TWI579971B (zh) 半導體裝置之製造方法
US10475649B2 (en) Patterning method
CN110021518A (zh) 自对准双重图案方法
TW202220032A (zh) 製造半導體裝置的方法
US7060625B2 (en) Imprint stamp
TWI905370B (zh) 用於三維小晶片形成的局部應力區域
US11150388B2 (en) Optical diffuser and its method of manufacture
US11721551B2 (en) Localized stress regions for three-dimension chiplet formation
CN109166820B (zh) 半导体器件制作方法以及半导体器件
CN119069409B (zh) 先进封装tsv标识对准封装方法、封装结构及封装对准系统
US11688642B2 (en) Localized stress regions for three-dimension chiplet formation
TWI910438B (zh) 半導體結構與其形成方法
CN108054137B (zh) 金属互连结构及其制作方法
KR20020002785A (ko) 반도체소자의 평탄화 방법
CN111799154A (zh) 背照式图像传感器的制造方法
CN111403262A (zh) 一种集成电路晶圆薄化制程支撑结构及其加工方法