JP2024504999A5 - - Google Patents

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Publication number
JP2024504999A5
JP2024504999A5 JP2023544627A JP2023544627A JP2024504999A5 JP 2024504999 A5 JP2024504999 A5 JP 2024504999A5 JP 2023544627 A JP2023544627 A JP 2023544627A JP 2023544627 A JP2023544627 A JP 2023544627A JP 2024504999 A5 JP2024504999 A5 JP 2024504999A5
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JP
Japan
Prior art keywords
semiconductor structure
stress film
steps include
patterned
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2023544627A
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English (en)
Japanese (ja)
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JP2024504999A (ja
JP7827393B2 (ja
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Priority claimed from PCT/US2022/012923 external-priority patent/WO2022164693A1/en
Publication of JP2024504999A publication Critical patent/JP2024504999A/ja
Publication of JP2024504999A5 publication Critical patent/JP2024504999A5/ja
Application granted granted Critical
Publication of JP7827393B2 publication Critical patent/JP7827393B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2023544627A 2021-01-26 2022-01-19 ３次元チップレット形成のための局所的応力領域 Active JP7827393B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202163141553P 2021-01-26 2021-01-26
US202163141552P 2021-01-26 2021-01-26
US63/141,552 2021-01-26
US63/141,553 2021-01-26
PCT/US2022/012923 WO2022164693A1 (en) 2021-01-26 2022-01-19 Localized stress regions for three-dimension chiplet formation

Publications (3)

Publication Number Publication Date
JP2024504999A JP2024504999A (ja) 2024-02-02
JP2024504999A5 true JP2024504999A5 (https=) 2024-10-31
JP7827393B2 JP7827393B2 (ja) 2026-03-10

Family

ID=82654872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023544627A Active JP7827393B2 (ja) 2021-01-26 2022-01-19 ３次元チップレット形成のための局所的応力領域

Country Status (4)

Country Link
JP (1) JP7827393B2 (https=)
KR (1) KR102937484B1 (https=)
TW (1) TWI905370B (https=)
WO (1) WO2022164693A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250087600A1 (en) * 2023-09-12 2025-03-13 Macronix International Co., Ltd. Semiconductor bonded structure and fabricating method thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US7675182B2 (en) * 2007-09-27 2010-03-09 Intel Corporation Die warpage control
US8212346B2 (en) * 2008-10-28 2012-07-03 Global Foundries, Inc. Method and apparatus for reducing semiconductor package tensile stress
CN103296013B (zh) * 2013-05-28 2017-08-08 上海华虹宏力半导体制造有限公司 射频器件的形成方法
US9397051B2 (en) * 2013-12-03 2016-07-19 Invensas Corporation Warpage reduction in structures with electrical circuitry
US9761540B2 (en) * 2015-06-24 2017-09-12 Micron Technology, Inc. Wafer level package and fabrication method thereof
TW201701429A (zh) * 2015-06-24 2017-01-01 華亞科技股份有限公司 晶圓級封裝及其製作方法
TWI652774B (zh) * 2017-03-03 2019-03-01 Siliconware Precision Industries Co., Ltd. 電子封裝件之製法
US10840227B2 (en) * 2017-11-02 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device

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