WO2020103226A1 - 半导体器件及其制作方法、对位标记的制作方法 - Google Patents

半导体器件及其制作方法、对位标记的制作方法

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Publication number
WO2020103226A1
WO2020103226A1 PCT/CN2018/120714 CN2018120714W WO2020103226A1 WO 2020103226 A1 WO2020103226 A1 WO 2020103226A1 CN 2018120714 W CN2018120714 W CN 2018120714W WO 2020103226 A1 WO2020103226 A1 WO 2020103226A1
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WIPO (PCT)
Prior art keywords
substrate
alignment
manufacturing
semiconductor device
photoresist layer
Prior art date
Application number
PCT/CN2018/120714
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English (en)
French (fr)
Inventor
刘孟彬
Original Assignee
中芯集成电路（宁波）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中芯集成电路（宁波）有限公司 filed Critical 中芯集成电路（宁波）有限公司
Priority to US16/236,568 priority Critical patent/US11049816B2/en
Publication of WO2020103226A1 publication Critical patent/WO2020103226A1/zh
Priority to US17/330,767 priority patent/US20210280527A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]

Definitions

  • the invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor device, a manufacturing method thereof, and a manufacturing method of an alignment mark.
  • the alignment and bonding of two wafers are often performed. Before the wafer alignment and bonding, at least two alignment marks need to be made on the carrier wafer (Carrier Wafer) (Mark), used to align the wafer with another wafer, and then form a bonding film (Lamination) on the carrier wafer for bonding the wafer to another wafer, the bonding film The alignment mark is covered, and finally the wafer is aligned according to the alignment mark, and bonding is performed through a bonding film.
  • Carrier Wafer Carrier Wafer
  • the light transmittance of the bonding film is low, and the bonding film covers the alignment mark, which will affect the subsequent equipment to grab the alignment mark. Therefore, before the alignment, the bonding film covering the alignment mark needs to be removed, because For the reason of the ability of the laminating machine, it is necessary to cut off the bonding film in a certain area centered on the alignment mark. As a result, a single piece of bonded film will be wasted by about 6%, and the usable area of the single wafer will also drop by about 6%, and each model needs to manufacture a mask to be used for loading
  • the alignment mark is formed on the wafer, thereby increasing the production cost, and the formation of the alignment mark also occupies production resources.
  • the production cycle of the alignment mark on each carrier wafer is 48 hours.
  • An object of the present invention is to provide a semiconductor device, a manufacturing method thereof, and a manufacturing method of an alignment mark, so as to increase the usable area of a substrate and reduce production costs.
  • the present invention provides a method for manufacturing a semiconductor device, including the following steps:
  • a die attach process is used to attach the alignment die to the bonding film of the alignment region of the second substrate.
  • the method further includes: aligning and bonding a side of the second substrate on which the alignment die is attached to a third substrate.
  • the bonding is a temporary bonding, and after the second substrate is separated from the third substrate, a bonding film can be formed on the second substrate again and an alignment die can be attached for alignment Position and bonding.
  • the method further includes: pasting a chip on the side of the second substrate to which the alignment die is attached.
  • the die attaching process includes: placing the alignment die on the bonding film of the alignment area of the second substrate and applying pressure to complete the attachment.
  • the applied pressure is 0.1N to 5N
  • the temperature when the pressure is applied is 23 ° C to 80 ° C
  • the time for applying the pressure is 0.1s to 5s.
  • the first substrate is a semiconductor material substrate;
  • the material of the bonding film is: a thermoplastic or thermosetting organic material, an inorganic material containing copper, nickel, chromium, or cobalt, an adhesive film, or a dry film membrane.
  • a method for forming a plurality of alignment marks on the first substrate includes:
  • the patterned first photoresist layer is removed.
  • the scribe line and the alignment mark are formed in the same process; during the process of etching the shading layer to form a plurality of alignment marks, the shading layer in the area of the scribe line is simultaneously etched to form The groove forms a cutting channel.
  • the method before or after forming the alignment mark, the method further includes:
  • the patterned second photoresist layer is removed.
  • At least two alignment regions are provided on the second substrate, and the two alignment regions are located on opposite sides of the second substrate.
  • the attachment accuracy of the alignment die is less than or equal to 3 ⁇ m.
  • the shape of the alignment mark includes one or more of a cross shape, a miter shape, a circle, an ellipse, a rectangle, and a square.
  • the maximum size of the alignment mark is between 0.5mm * 0.5mm-10mm * 10mm.
  • the present invention also provides a semiconductor device formed by the method described above, including:
  • the alignment die used for the alignment of the second substrate is located on the bonding film of the alignment region of the second substrate, and the alignment die includes the first substrate after cutting and formed on At least one alignment mark on the cut first substrate, the cut first substrate is attached to the bonding film.
  • the first substrate is a semiconductor material substrate; at least two alignment regions are provided on the second substrate, and the two alignment regions are located on opposite sides of the second substrate.
  • the shape of the alignment mark includes one or more of a cross shape, a miter shape, a circle, an ellipse, a rectangle, and a square.
  • the maximum size of the alignment mark is between 0.5mm * 0.5mm-10mm * 10mm.
  • the invention also provides a method for manufacturing the alignment mark, including:
  • a plurality of alignment marks are formed on the semiconductor material substrate, and the plurality of alignment marks are spread over the semiconductor material substrate.
  • the method further includes: after forming a plurality of alignment marks, cutting the semiconductor material substrate to form a plurality of alignment grains for alignment.
  • the method for forming multiple alignment marks includes:
  • the patterned photoresist layer is removed.
  • a plurality of alignment grains including the alignment mark are first manufactured, and when the second substrate needs to be aligned, only the alignment grain needs to be pasted It only needs to be attached to the second substrate, and there is no need to use a mask plate to make alignment marks on the second substrate each time, which saves the process steps, reduces the production cost, and improves the production efficiency.
  • a bonding film is formed on the second substrate, and the alignment die is formed on the bonding film, thereby avoiding the bond
  • the cutting of the bonding film saves the process steps and the bonding film, and at the same time increases the available area of the second substrate.
  • FIG. 1 is a schematic diagram of a semiconductor device.
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the invention.
  • 3 to 5 are schematic structural diagrams of various steps of a method for manufacturing a semiconductor device according to an embodiment of the invention.
  • 6a to 6d are schematic diagrams of alignment marks provided by an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a semiconductor device. Please refer to FIG. 1.
  • the semiconductor device includes a carrier wafer 10 on which two alignment marks 20 are formed.
  • the two alignment marks 20 It is formed on two opposite sides of the carrier wafer 10 to achieve the alignment of the carrier wafer 10 and another wafer.
  • the carrier wafer 10 and the alignment mark 20 are further covered with a bonding film 30, so as to realize the bonding of the carrier wafer 10 and another wafer in the wafer bonding process.
  • the alignment mark needs to be made on the carrier wafer through a mask plate, and the production cycle of the alignment mark on each carrier wafer is 48 hours, that is The formation of alignment marks also consumes production resources.
  • the present invention provides a method of manufacturing a semiconductor device, including: providing a first substrate, and forming a plurality of alignment marks on the first substrate; cutting the first substrate to form a plurality of Aligned alignment die, each of the alignment die includes a cut first substrate and at least one alignment mark formed on the cut first substrate; providing a second that requires alignment A substrate, and forming a bonding film on the second substrate; a die attach process is used to attach the alignment die to the bonding film in the alignment area of the second substrate.
  • the present invention also provides a semiconductor device, comprising: a second substrate, a bonding film is formed on the second substrate; and an alignment die for the alignment of the second substrate is located in the second On the bonding film of the alignment area of the substrate, the alignment die includes a first substrate after cutting and at least one alignment mark formed on the first substrate after cutting, after the cutting The first substrate is attached to the bonding film.
  • the invention also provides a method for manufacturing an alignment mark, which comprises: providing a semiconductor material substrate, forming a plurality of alignment marks on the semiconductor material substrate, the plurality of alignment marks spread over the semiconductor material substrate.
  • a plurality of alignment grains including the alignment mark are first manufactured, and when the second substrate needs to be aligned, only the alignment grain needs to be pasted It only needs to be attached to the second substrate, and there is no need to use a mask plate to make alignment marks on the substrate every time, saving process steps, reducing production costs, and improving production efficiency.
  • a bonding film is formed on the second substrate, and the alignment die is formed on the bonding film, thereby avoiding the bond
  • the cutting of the bonding film saves the process steps and the bonding film, and at the same time increases the available area of the second substrate.
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • the present invention provides a method for manufacturing a semiconductor device, including the following steps:
  • Step S100 providing a first substrate, and forming a plurality of alignment marks on the first substrate;
  • Step S200 cutting the first substrate to form a plurality of alignment dies for alignment, each alignment die including a first substrate after cutting and a first substrate formed on the cutting At least one alignment mark on
  • Step S300 providing a second substrate that needs to be aligned, and forming a bonding film on the second substrate;
  • Step S400 Adhere the alignment die to the bonding film of the alignment area of the second substrate using a die attach process.
  • FIGS. 3 to 5 are schematic structural diagrams of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to FIGS. 3 to 5.
  • the first substrate 100 is a semiconductor material substrate.
  • the first substrate 100 may be a silicon substrate, or a germanium, silicon germanium, gallium arsenide or silicon-on-insulator substrate. Those skilled in the art may select the first substrate 100 as needed.
  • the material of the substrate 100, so the type of the first substrate 100 should not limit the protection scope of the present invention.
  • the first substrate 100 is, for example, a flat-plate structure.
  • the top shape of the first substrate 100 may be a circle, a rectangle, or other shapes, and the shape of the first substrate 100 is not particularly limited in the present invention.
  • the first substrate 100 is a silicon substrate, and the shape of the first substrate 100 is circular.
  • the first substrate 100 is mainly used to carry alignment marks, which are subsequently cut to form alignment grains containing alignment marks for alignment, and no semiconductor device structure needs to be formed thereon.
  • a plurality of alignment marks 200 are formed on the first substrate 100 to form the structure shown in FIG. 3.
  • a light-shielding layer formed of an opaque material may be formed on the first substrate 100 first, for example, PVD (Physical Vapor Deposition, physical vapor deposition) or other methods may be used to form the light-shielding layer on the first substrate 100
  • a light shielding layer formed of the opaque material may generally be a metal material, such as an aluminum layer, a tungsten layer, or a chromium layer, and the opaque material (that is, the light-shielding layer) may also be a metal Compound conductive layer.
  • a first photoresist layer is formed on the light-shielding layer, and the first photoresist layer is exposed and developed using a mask plate to form a patterned first photoresist layer, and then patterned
  • the first photoresist layer is used as a mask to etch the light-shielding layer to form a plurality of alignment marks 200 on the first substrate 100.
  • the patterned first photoresist layer can be removed through an ashing process.
  • a scribe line may be formed on the first substrate 100 to facilitate subsequent cutting of the first substrate 100.
  • a second photoresist layer is formed on the first substrate 100, and the second photoresist layer is exposed and developed using a mask to form a patterned second photoresist layer, which is exposed The first substrate 100 in the area of the cutting lane.
  • the first substrate 100 is etched using the patterned second photoresist layer as a mask to form a groove, and the groove is a scribe line.
  • the patterned second photoresist layer can be removed through an ashing process.
  • the cutting lane may also be formed during the formation of the alignment mark 200, that is, the cutting lane and the alignment mark 200 are formed in the same process.
  • a mask plate is used to expose and develop the first photoresist layer to form a patterned first photoresist layer.
  • the patterned first photoresist layer not only exposes the predetermined
  • the area of the alignment mark also exposes the scribe line area.
  • the light-shielding layer is etched using the patterned first photoresist layer as a mask, and the light-shielding layer in the area where the alignment mark is to be formed is etched to form the first substrate 100 A plurality of alignment marks 200 are formed thereon, and the light-shielding layer in the area of the scribe line is etched at the same time to form a groove to constitute the scribe line. Finally, the patterned first photoresist layer is removed through an ashing process.
  • alignment marks 200 may be the same or different.
  • a single mask can be used to form a plurality of alignment marks 200 with different shapes, thereby reducing the cost of manufacturing the mask and also simplifying the process.
  • the shape of the alignment mark may be any combination of one or more of a cross shape, a square shape, a circle, an ellipse, a rectangle, and a square.
  • the shape of the alignment mark 200 may be a cross shape, and the size of the horizontal and vertical bars of the cross shape is preferably the same.
  • the shape of the alignment mark 200 may also be a miter shape, that is, a combination of a cross shape and an oval shape, wherein the size of the cross shape and the vertical shape of the cross shape are preferably the same, And, the sizes of the four ellipses in the chevron are also preferably the same.
  • the shape of the alignment mark 200 is a circle.
  • the shape of the alignment mark 200 is a combination of a square and a circle, for example, a square is evenly distributed with four circles of the same size.
  • the marks of several shapes are introduced above with reference to FIGS. 6a-6d. In a specific embodiment, the marks are not limited to the above examples.
  • the alignment mark 200 may be a combination of multiple shapes of the same shape, or a combination of different shapes.
  • the maximum size of the alignment mark 200 is between 0.5 mm * 0.5 mm and 10 mm * 10 mm.
  • the horizontal bar and the vertical bar of the cross shape The dimensions are between 0.5mm * 0.5mm ⁇ 10mm * 10mm.
  • the size of the square is between 0.5mm * 0.5mm ⁇ 10mm * 10mm.
  • the contrast marks 200 are evenly distributed on the first substrate 100 to facilitate subsequent cutting of the first substrate 100.
  • the alignment marks 200 of different shapes can also be typeset on the first substrate 100 to make the most use of the first substrate 100.
  • the first substrate 100 can be cut later A substrate 100 is premised on separating adjacent alignment marks 200.
  • each of the alignment dies 300 includes The cut first substrate 100 and at least one alignment mark 200 formed on the cut first substrate 100.
  • Each alignment die 300 includes at least one alignment mark 200.
  • each alignment die 300 includes an alignment mark 200, as shown in FIG. 4.
  • the shape of the first substrate 100 after cutting is, for example, a square shape, and the shape of the alignment mark 200 is, for example, a cross shape.
  • the second substrate 400 may be a silicon substrate, or a germanium, silicon germanium, gallium arsenide, or silicon-on-insulator substrate.
  • a person skilled in the art can select the second substrate as needed, so the type of the second substrate should not limit the protection scope of the present invention.
  • the second substrate 400 is a silicon substrate.
  • the second substrate 400 may be any substrate that needs to be aligned, and any semiconductor device may be formed on the second substrate 400, for example, may include a memory, a logic circuit, a power device, a bipolar device, and a separate MOS Active devices such as transistors, micro-electromechanical systems (MEMS), and even photoelectric devices such as light-emitting diodes can also include passive devices, such as resistors and capacitors, which are not limited in the present invention.
  • the second substrate 400 may also be a bare substrate. After the alignment and bonding are subsequently completed, it can be peeled off and reused.
  • a bonding film 500 is formed on the second substrate 400.
  • the bonding film 500 may be formed on the second substrate 400 by rolling, spin coating, spray coating, printing, non-spin coating, hot pressing, vacuum pressing, soaking, pressure bonding, and the like.
  • the bonding film 500 may be a temporary bonding film, for example, it may be a thermoplastic or thermosetting organic material, or it may contain components such as Cu (copper), Ni (nickel), Cr (chromium), Co (cobalt), etc.
  • the inorganic materials can be removed by heating, mechanical, chemical, laser, freezing, etc.
  • the bonding film 500 may also be a permanent bonding film, such as an adhesive film (Die Attach Film (DAF) or a dry film).
  • DAF Die Attach Film
  • the adhesive sheet film may be, for example, a resin glue, especially a highly thermally conductive resin glue, so as to play an adhesive role.
  • the dry film is a polymer compound, which can produce a polymerization reaction after being irradiated with ultraviolet rays to form a stable substance attached to the surface of the second substrate 400 to be bonded, so as to play an adhesive role .
  • a die attach process is used to attach the alignment die 300 to the bonding film 500 in the alignment area of the second substrate 400.
  • the die attaching process includes: placing the alignment die 300 on the bonding film 500 in the alignment area of the second substrate 400 and applying pressure to complete the attachment.
  • the applied pressure is 0.1 N to 5 N
  • the temperature when the pressure is applied is 23 ° C. to 80 ° C.
  • the time for applying the pressure is 0.1 s to 5 s, so that the alignment die 300 is completely attached to the On the bonding film 500 of the second substrate 400, the success rate of attachment is improved.
  • At least two alignment regions are provided on the second substrate 400, preferably two alignment regions, and the two alignment regions are located on opposite sides of the second substrate 400.
  • Each of the alignment dies 300 is attached to an alignment region.
  • the attachment accuracy of the alignment dies 300 is less than or equal to 3 ⁇ m.
  • the attaching accuracy refers to the offset of the actual attaching position relative to the ideal attaching position, so that the alignment die 300 can be accurately attached to the alignment area to complete the first
  • the alignment of the two substrates 400 and subsequent substrates improves the alignment accuracy to improve the performance of the semiconductor device.
  • the method further includes: aligning and bonding a side of the second substrate 400 on which the alignment die 300 is attached to a third substrate.
  • the alignment of the second substrate 400 and the third substrate is performed by the alignment die 300, and the bonding of the second substrate 400 and the third substrate is accomplished by the bonding film 500.
  • the bonding may be temporary bonding and permanent bonding. If the bonding is temporary, the second substrate 400 can be reused. That is, after the alignment and temporary bonding are completed, and the subsequent process is completed, the second substrate 400 is separated from the third substrate, and the remaining bonding film 500 and the alignment crystal on the second substrate 400 are peeled off The particles 300 can then form a bonding film on the second substrate again and attach alignment crystal grains to perform alignment and bonding again.
  • the third substrate may be at least one of the semiconductor materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including these semiconductor components Multi-layer structure, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI) Wait.
  • the third substrate is a substrate that needs to be aligned and bonded. Any semiconductor device may be formed on the third substrate.
  • the third substrate may also be a bare substrate, which is not limited in the present invention.
  • the method further includes: pasting a chip on the side of the second substrate 400 to which the alignment die 300 is attached.
  • the alignment of the second substrate 400 and the bottom of the chip is completed by the alignment die 300, and the bonding of the second substrate 400 and the chip is completed by the bonding film 500.
  • the bonding film 30 is formed on the alignment mark 20, and the bonding film 30 needs to be cut, thereby forming a blank area 30 ′, and
  • the alignment die 300 is formed on the bonding film 500, and there is no need to cut the bonding film 500, which saves the process steps and process time, and saves the bonding film 500, while improving The available area of the second substrate 400.
  • the bonding is temporary bonding, for the structure shown in FIG. 1, after the carrier wafer 10 is peeled off, if the alignment mark 20 thereon remains on the carrier wafer 10, the carrier wafer The circle 10 can only be used for the same type of alignment and bonding.
  • the alignment mark 20 thereon is peeled off from the carrier wafer 10, the alignment mark needs to be re-made on the carrier wafer 10, namely Either it is limited by the type of alignment and bonding, or the alignment mark is remade.
  • the manufacturing method of the semiconductor device provided in this embodiment improves the utilization rate of the second substrate, further saves the process steps, reduces the production cost, and improves the production efficiency.
  • the alignment die including the cut first substrate and the alignment marks formed on the cut first substrate to the second substrate
  • the alignment mark is directly formed on the alignment substrate.
  • the thickness of the alignment die in the embodiment of the present application is greater than the thickness of the alignment mark in the prior art. Therefore, the thickness of the carrier substrate It should not be too thick, otherwise the thickness of the alignment die will be too thick and it will affect the subsequent alignment. On the other hand, the thickness of the carrier substrate should not be too thin, otherwise it will affect the formation of alignment on it Marked steps. Therefore, the thickness of the carrier substrate needs to be determined according to actual conditions.
  • each of the alignment dies 300 includes a first substrate 100 after cutting and at least one pair formed on the first substrate 100 after cutting Bit mark 200, and then provide a second substrate 400 that needs to be aligned, and form a bonding film 500 on the second substrate 400; use a die attach process to attach the aligned die 300 to the The bonding film 500 in the alignment region of the second substrate 400.
  • a plurality of alignment dies 300 including alignment marks 200 are manufactured.
  • the alignment die 300 When the second substrate 400 needs to be aligned, only the alignment die 300 needs to be attached to the second substrate 400, and does not need to be Each time, a mask plate is used to make alignment marks on the second substrate 400, saving process steps, reducing production costs, and improving production efficiency. Furthermore, before attaching the alignment die 300 to the second substrate 400, a bonding film 500 is formed on the second substrate 400, and the alignment die 300 is formed on the bonding film 500, Thereby, the cutting of the bonding film 500 is avoided, the process steps are saved, the bonding film 500 is saved, and the available area of the second substrate 400 is increased at the same time.
  • the present invention also provides a semiconductor device manufactured by the method described above, please refer to FIGS. 4 and 5, the semiconductor device includes:
  • the alignment die 300 used for alignment of the second substrate 400 is located above the bonding film 500 of the alignment region of the second substrate 400, and the alignment die 300 includes the first A substrate 100 and at least one alignment mark 200 formed on the cut first substrate 100, the cut first substrate 100 is attached to the bonding film 500.
  • the shape of the alignment mark 200 is a cross shape, and the shape of the alignment mark 200 may also be one of a cross shape, a circle, an ellipse, a rectangle, and a square, or Any combination of multiple.
  • the shape of the alignment mark 200 may be a cross shape, and the size of the horizontal and vertical bars of the cross shape is preferably the same.
  • the shape of the alignment mark 200 may also be a miter shape, that is, a combination of a cross shape and an oval shape, wherein the size of the cross and vertical bars of the cross shape is preferably the same, And, the sizes of the four ellipses in the chevron are also preferably the same.
  • the shape of the alignment mark 200 is a circle.
  • the shape of the alignment mark 200 is a combination of a square and a circle, for example, a square is evenly distributed with four circles of the same size.
  • the marks of several shapes are introduced above with reference to FIGS. 6a-6d. In a specific embodiment, the marks are not limited to the above examples.
  • the alignment mark 200 may be a combination of multiple numbers of the same shape or a combination of multiple shapes.
  • the maximum size of the alignment mark 200 is between 0.5mm * 0.5mm ⁇ 10mm * 10mm.
  • the size of the horizontal bar and the vertical bar in the cross shape are between 0.5 mm * 0.5 mm-10 mm * 10 mm.
  • the size of the square is between 0.5mm * 0.5mm ⁇ 10mm * 10mm.
  • the first substrate 100 is a semiconductor material substrate, and the first substrate 100 may be a silicon substrate, or a germanium, silicon germanium, gallium arsenide or silicon-on-insulator substrate. Those skilled in the art may The material of the first substrate 100 is selected, so the type of the first substrate 100 should not limit the protection scope of the present invention. In this embodiment, the first substrate 100 is a silicon substrate.
  • At least two alignment regions are provided on the second substrate 400, and the two alignment regions are located on opposite sides of the second substrate 400.
  • the second substrate 400 has a circular shape, two alignment regions are located at any two points on the diameter of the alignment substrate 400, and two alignment die 30 are located at two Within the alignment area.
  • the semiconductor device further includes a third substrate, and the third substrate and the second substrate 400 are bonded with one-to-one alignment of the alignment die 300.
  • the semiconductor device further includes a chip attached to the side of the second substrate 400 to which the alignment die 300 is attached.
  • the invention also provides a method for manufacturing an alignment mark, including: providing a semiconductor material substrate, forming a plurality of alignment marks on the semiconductor material substrate, the plurality of alignment marks spread over the semiconductor material substrate .
  • a light-shielding layer formed of an opaque material is formed on the semiconductor material substrate.
  • a method such as PVD (Physical Vapor Deposition) can be used to form the light-shielding layer on the semiconductor material substrate.
  • the opaque material that is, the light-shielding layer
  • the opaque material may generally be a metal material, such as an aluminum layer, a tungsten layer, or a chromium layer
  • the opaque material that is, the light-shielding layer
  • the opaque material may also be a metal Compound conductive layer.
  • a first photoresist layer is formed on the light-shielding layer, and the first photoresist layer is exposed and developed using a mask plate to form a patterned first photoresist layer, and then patterned
  • the first photoresist layer is used as a mask to etch the light-shielding layer to form a plurality of alignment marks on the semiconductor material substrate, and the plurality of alignment marks are spread over the semiconductor material substrate.
  • the patterned first photoresist layer can be removed through an ashing process.
  • a scribe line may also be formed on the semiconductor material substrate to facilitate subsequent cutting of the semiconductor material substrate.
  • a second photoresist layer is formed on the semiconductor material substrate, and the second photoresist layer is exposed and developed using a mask to form a patterned second photoresist layer, and the cutting is exposed The semiconductor material substrate in the track area.
  • the semiconductor material substrate is etched using the patterned second photoresist layer as a mask to form a groove, and the groove is a scribe line.
  • the patterned second photoresist layer can be removed through an ashing process.
  • the cutting lane may also be formed during the formation of the alignment mark, that is, the cutting lane and the alignment mark are formed in the same process.
  • a mask plate is used to expose and develop the first photoresist layer to form a patterned first photoresist layer.
  • the patterned first photoresist layer not only exposes the predetermined
  • the area of the alignment mark also exposes the scribe line area.
  • the patterned first photoresist layer is used as a mask to etch the light-shielding layer, and the light-shielding layer in the area where the alignment mark is to be formed is etched to be on the semiconductor material substrate A plurality of alignment marks are formed, and the light-shielding layer in the area of the scribe line is etched at the same time to form a groove to constitute the scribe line. Finally, the patterned first photoresist layer is removed through an ashing process.
  • the manufacturing method of the alignment mark further includes: after forming a plurality of alignment marks, cutting the semiconductor material substrate to form a plurality of alignment grains for alignment.
  • the alignment die can be directly attached to the alignment area of the substrate, and alignment is used. The die can complete the alignment of the substrate, and there is no need to use a mask to make the alignment mark on the substrate every time, which saves the process steps, reduces the production cost, improves the production efficiency, and because the alignment die is located in the On the bonding film, the cutting of the bonding film can be avoided, the process steps are saved, the bonding film is saved, and the available area of the substrate is increased.
  • the manufacturing method thereof, and the manufacturing method of the alignment mark provided by the present invention first, a plurality of alignment grains including the alignment mark are manufactured.
  • the second substrate needs to be aligned, only the The alignment die can be attached to the second substrate, and there is no need to use a mask to make alignment marks on the second substrate each time, which saves the process steps, reduces the production cost, and improves the production efficiency.
  • a bonding film is formed on the second substrate, and the alignment die is formed on the bonding film, thereby avoiding the bond
  • the cutting of the bonding film saves the process steps and the bonding film, and at the same time increases the available area of the second substrate.

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Abstract

一种半导体器件及其制作方法、对位标记的制作方法，包括：提供第一基底(100)，在第一基底(100)上形成多个对位标记(200)，切割第一基底(100)，形成多个用于对位的对位晶粒(300)，每个对位晶粒(300)包括切割后的第一基底(100)以及形成于切割后的第一基底(100)上的至少一个对位标记(200)，提供一需要对位的第二基底(400)，并在第二基底(400)上形成键合薄膜(500)，采用晶粒贴附工艺将对位晶粒(300)贴附于第二基底(400)的对位区域的键合薄膜(500)上。在将对位晶粒(300)贴附于第二基底(400)之前，在第二基底(400)上形成键合薄膜(500)，对位晶粒(300)形成于键合薄膜(500)之上，从而避免对所述键合薄膜(500)的切割，节省了工艺步骤，并节省了键合薄膜(500)，同时提高了第二基底(400)的可用面积。

Description

半导体器件及其制作方法、对位标记的制作方法 技术领域
本发明涉及集成电路制造技术领域，具体涉及一种半导体器件及其制作方法、对位标记的制作方法。
背景技术
在半导体的制作过程中，经常会进行两个晶圆的对位与键合，在晶圆对位与键合之前，首先需要在承载晶圆(Carrier Wafer)上制作至少两颗对位标记(Mark)，用于承载晶圆与另一晶圆的对位，然后在承载晶圆上形成键合薄膜(Lamination)，用于承载晶圆与另一晶圆的键合，所述键合薄膜覆盖所述对位标记，最后才根据对位标记进行晶圆的对位，并通过键合薄膜进行键合。
然而键合薄膜的透光率低，键合薄膜覆盖对位标记，会影响后续设备对对位标记的抓取，所以进行对位之前，需要将盖住对位标记的键合薄膜去除，由于贴膜机能力原因，必须要割除以对位标记为中心的一定区域内的键合薄膜。由此，会造成键合薄膜单片浪费大约6％，同时单片承载晶圆的可用面积也会随之下降大约6％，并且每一个机种均需制造一张掩模板，用于在承载晶圆上形成对位标记，由此提高了生产成本，并且对位标记的形成也会占用生产资源，每片承载晶圆上对位标记的生产周期是48小时。
发明内容
本发明的目的在于提供一种半导体器件及其制作方法、对位标记的制作方法，提高基底的可用面积，降低生产成本。
为实现上述目的，本发明提供一种半导体器件的制作方法，包括以下步骤：
提供第一基底，并在所述第一基底上形成多个对位标记；
切割所述第一基底，以形成多个用于对位的对位晶粒，每个所述对位晶粒包括切割后的第一基底以及形成于所述切割后的第一基底上的至少一个对位标记；
提供一需要对位的第二基底，并在所述第二基底上形成键合薄膜；
采用晶粒贴附工艺将所述对位晶粒贴附于所述第二基底的对位区域的所述键合薄膜上。
可选的，还包括：将所述第二基底贴附有所述对位晶粒的一面与一第三基底进行对位与键合。
可选的，所述键合为临时键合，所述第二基底与所述第三基底分离之后，能够再次在所述第二基底上形成键合薄膜并贴附对位晶粒以进行对位与键合。
可选的，还包括：在所述第二基底贴附有所述对位晶粒的一面上粘贴芯片。
可选的，所述晶粒贴附工艺包括：将所述对位晶粒放置于所述第二基底的对位区域的所述键合薄膜上并施加压力完成贴附。
可选的，施加的压力为0.1N～5N，施加压力时的温度为23℃～80℃，施加压力的时间为0.1s～5s。
可选的，所述第一基底为半导体材料基底；所述键合薄膜的材料为：热塑或热固型有机材料、含有铜、镍、铬或钴成分的无机材料、粘片膜或干膜。
可选的，在所述第一基底上形成多个对位标记的方法包括：
依次形成遮光层与第一光刻胶层在所述第一基底上；
图形化所述第一光刻胶层；
以图形化的所述第一光刻胶层为掩膜，刻蚀所述遮光层，以形成多个对位标记；
去除图形化的所述第一光刻胶层。
可选的，切割道与所述对位标记在同一工艺过程中形成；刻蚀所述遮光层以形成多个对位标记的过程中，同时刻蚀切割道区域内的所述遮光层，形成凹槽以构成切割道。
可选的，在形成所述对位标记之前或之后，还包括：
形成第二光刻胶层在所述第一基底上；
图形化所述第二光刻胶层，暴露出切割道区域内的所述第一基底；
以图形化的所述第二光刻胶层为掩膜，刻蚀所述第一基底，形成凹槽以构成切割道；
去除图形化的所述第二光刻胶层。
可选的，所述第二基底上设置有至少两个对位区域，两个所述对位区域位于所述第二基底的相对两侧。
可选的，所述对位晶粒的贴附精度小于等于3μm。
可选的，所述对位标记的形状包含：十字型、米字型、圆形、椭圆形、长方形、正方形中的一种或多种。
可选的，所述对位标记的最大尺寸介于0.5mm*0.5mm～10mm*10mm之间。
相应的，本发明还提供一种半导体器件，采用如上所述的方法形成，包括：
第二基底，所述第二基底上形成有键合薄膜；
用于所述第二基底对位的对位晶粒，位于所述第二基底的对位区域的所述键合薄膜之上，所述对位晶粒包含切割后的第一基底以及形成于所述切割后的第一基底上的至少一个对位标记，所述切割后的第一基底贴附于所述键合薄膜上。
可选的，所述第一基底为半导体材料基底；所述第二基底上设置有至少两个对位区域，两个所述对位区域位于所述第二基底的相对两侧。
可选的，所述对位标记的形状包含：十字型、米字型、圆形、椭圆形、长方形、正方形中的一种或多种。
可选的，所述对位标记的最大尺寸介于0.5mm*0.5mm～10mm*10mm之间。
相应的，本发明还提供一种对位标记的制作方法，包括：
提供半导体材料基底；
在所述半导体材料基底上形成多个对位标记，所述多个对位标记遍布所述半导体材料基底。
可选的，还包括：形成多个对位标记后，切割所述半导体材料基底，以 形成多个用于对位的对位晶粒。
可选的，形成多个对位标记的方法包括：
依次形成遮光层与光刻胶层在所述半导体材料基底上；
图形化所述光刻胶层；
以图形化的所述光刻胶层为掩膜，刻蚀所述遮光层，以形成多个对位标记；
去除图形化的所述光刻胶层。
本发明提供的半导体器件及其制作方法、对位标记的制作方法中，先制作多个包含对位标记的对位晶粒，在第二基底需要对位时，只需将对位晶粒贴附于第二基底上即可，并不需要每次都在第二基底上采用掩模板制作对位标记，节省了工艺步骤，降低了生产成本，提高了生产效率。并且，在将对位晶粒贴附于所述第二基底之前，在所述第二基底上形成键合薄膜，对位晶粒形成于所述键合薄膜之上，从而避免对所述键合薄膜的切割，节省了工艺步骤，并节省了键合薄膜，同时提高了第二基底的可用面积。
附图说明
图1为一半导体器件的结构示意图。
图2为本发明一实施例所提供的半导体器件的制作方法的流程图。
图3～5为本发明一实施例所提供的半导体器件的制作方法的各步骤结构示意图。
图6a～6d为本发明一实施例所提供的对位标记的示意图。
具体实施方式
图1为一半导体器件的结构示意图，请参考图1所示，所述半导体器件包含承载晶圆10，所述承载晶圆10上形成有两个对位标记20，这两个对位标记20形成于所述承载晶圆10一相对的两侧，以实现承载晶圆10与另一晶圆的对位。在所述承载晶圆10以及所述对位标记20上还覆盖有键合薄膜30，以在晶圆键合工艺中，实现承载晶圆10与另一晶圆的键合。
然而，发明人发现，键合薄膜30的透光率通常都比较低，为了保证后续对位时设备能够抓取到对位标记，必须将覆盖住所述对位标记20的这部分键合薄膜去除，但由于贴膜机能力原因(贴膜机切割的精度不高)，在切割所述键合薄膜30时难以保证恰好切掉对位标记20上方的键合薄膜，实践发现，切割时往往会切掉对位标记20周边的部分键合薄膜，从而形成一个包围所述对位标记20的空白区域30’，这样会导致这些区域的键合薄膜被浪费，并且承载晶圆10的可用面积也会随之降低。
另外，每片所述承载晶圆在对位之前，均需要通过掩模板在所述承载晶圆上制作所述对位标记，每片承载晶圆上对位标记的生产周期是48小时，即对位标记的形成也会占用生产资源。
基于上述发现，本发明提供一种半导体器件的制作方法，包括：提供第一基底，并在所述第一基底上形成多个对位标记；切割所述第一基底，以形成多个用于对位的对位晶粒，每个所述对位晶粒包括切割后的第一基底以及形成于所述切割后的第一基底上的至少一个对位标记；提供一需要对位的第二基底，并在所述第二基底上形成键合薄膜；采用晶粒贴附工艺将所述对位晶粒贴附于所述第二基底的对位区域的所述键合薄膜上。
相应的，本发明还提供一种半导体器件，包括：第二基底，所述第二基底上形成有键合薄膜；用于所述第二基底对位的对位晶粒，位于所述第二基底的对位区域的所述键合薄膜之上，所述对位晶粒包含切割后的第一基底以及形成于所述切割后的第一基底上的至少一个对位标记，所述切割后的第一基底贴附于所述键合薄膜上。
本发明还提供一种对位标记的制作方法，包括：提供半导体材料基底，在所述半导体材料基底上形成多个对位标记，所述多个对位标记遍布所述半导体材料基底。
本发明提供的半导体器件及其制作方法、对位标记的制作方法中，先制作多个包含对位标记的对位晶粒，在第二基底需要对位时，只需将对位晶粒贴附于第二基底上即可，并不需要每次都在基底上采用掩模板制作对位标记，节省了工艺步骤，降低了生产成本，提高了生产效率。并且，在将对位晶粒 贴附于所述第二基底之前，在所述第二基底上形成键合薄膜，对位晶粒形成于所述键合薄膜之上，从而避免对所述键合薄膜的切割，节省了工艺步骤，并节省了键合薄膜，同时提高了第二基底的可用面积。
为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容做进一步说明。当然本发明并不局限于该具体实施例，本领域的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。其次，本发明利用示意图进行了详细的表述，在详述本发明实例时，为了便于说明，示意图不依照一般比例局部放大，不应对此作为本发明的限定。
请参考图2，其为本发明一实施例所提供的半导体器件的制作方法的流程图。如图2所示，本发明提供一种半导体器件的制作方法，包括以下步骤：
步骤S100：提供第一基底，并在所述第一基底上形成多个对位标记；
步骤S200：切割所述第一基底，以形成多个用于对位的对位晶粒，每个所述对位晶粒包括切割后的第一基底以及形成于所述切割后的第一基底上的至少一个对位标记；
步骤S300：提供一需要对位的第二基底，并在所述第二基底上形成键合薄膜；
步骤S400：采用晶粒贴附工艺将所述对位晶粒贴附于所述第二基底的对位区域的所述键合薄膜上。
图3～5为本发明一实施例所提供的半导体器件的制作方法的各步骤结构示意图，下文将结合图3～5详细说明本发明提出的半导体器件的制作方法。
首先，提供一第一基底100。所述第一基底100为半导体材料基底，所述第一基底100可以为硅基底，也可以是锗、锗硅、砷化镓基底或绝缘体上硅基底，本领域技术人员可以根据需要选择第一基底100的材料，因此第一基 底100的类型不应限制本发明的保护范围。所述第一基底100例如为平板状结构，进一步的，所述第一基底100的俯视形状可以为圆形、矩形或其他形状，本发明不对所述第一基底100的形状进行特别限定。本实施例中，所述第一基底100为硅基底，所述第一基底100的形状为圆形。所述第一基底100主要用于承载对位标记，后续被切割形成包含对位标记的对位晶粒以用于对位，其上并不需要形成任何的半导体器件结构。
接着，在所述第一基底100上形成多个对位标记200，形成如图3所示的结构。具体的，可以先在所述第一基底100上形成由不透光材料所形成的遮光层，例如，可采用PVD(Physical Vapor Deposition，物理气相沉积)等方法在所述第一基底100上形成由所述不透光材料所形成的遮光层。其中，所述不透光材料(即所述遮光层)通常可以为金属材料，如可以为铝层、钨层、铬层，所述不透光材料(即所述遮光层)也可以是金属化合物导电层。然后在所述遮光层上形成第一光刻胶层，并利用掩膜板对所述第一光刻胶层进行曝光与显影以形成图形化的第一光刻胶层，再以图形化的第一光刻胶层为掩膜对所述遮光层进行刻蚀，以在所述第一基底100上形成多个对位标记200。最后，可以通过灰化工艺去除图形化的所述第一光刻胶层。
在一实施例中，在形成所述对位标记200之前或之后，还可以在所述第一基底100上形成切割道(未图示)，以方便后续对所述第一基底100的切割。具体的，在所述第一基底100上形成第二光刻胶层，利用掩膜板对所述第二光刻胶层进行曝光与显影以形成图形化的第二光刻胶层，暴露出切割道区域内的所述第一基底100。接着，以图形化的第二光刻胶层为掩膜对所述第一基底100进行刻蚀，以形成凹槽，所述凹槽即为切割道。最后，可以通过灰化工艺去除图形化的所述第二光刻胶层。
在另一实施例中，也可以在形成所述对位标记200的过程中形成所述切割道，即所述切割道与所述对位标记200在同一工艺过程中形成。具体的，利用掩膜板对所述第一光刻胶层进行曝光与显影以形成图形化的第一光刻胶层，图形化的所述第一光刻胶层不仅暴露出预定形成所述对位标记的区域，还暴露出切割道区域。接着，以图形化的所述第一光刻胶层为掩膜对所述遮 光层进行刻蚀，刻蚀预定形成对位标记的区域内的所述遮光层，以在所述第一基底100上形成多个对位标记200，同时刻蚀切割道区域内的所述遮光层，形成凹槽以构成切割道。最后，通过灰化工艺去除图形化的所述的第一光刻胶层。
这些对位标记200的形状可以相同，也可以不同。优选方案中，可以用一张掩模板形成多个形状不同的对位标记200，由此可以减少制作掩模板的成本，也有利于简化工艺。
所述对位标记的形状可以是十字型、米字型、圆形、椭圆形、长方形、正方形中的一种或多种的任意组合。请参看图6a所示，所述对位标记200的形状可以为十字型，其中，该十字型的横条和竖条的尺寸优选是相同的。请参考图6b所示，所述对位标记200的形状也可以为米字型，即为十字型与椭圆形的组合，其中，该十字型的横条和竖条的尺寸优选是相同的，以及，该米字型中的四个椭圆形的尺寸亦优选是相同的。请参考图6c所示，所述对位标记200的形状为圆形。请参考图6d所示，所述对位标记200的形状为正方形与圆形的组合，例如是一个正方形中均匀分布四个尺寸相同的圆形。以上结合图6a-6d介绍了几种形状的标记，在具体实施例时并不限于上述举例，所述对位标记200可以是同一种形状多种数量的组合，也可以是不同形状的组合。
所述对位标记200的最大尺寸介于0.5mm*0.5mm～10mm*10mm之间，例如，当所述对位标记200为如图6a所示的形状时，十字型中横条与竖条的尺寸均介于0.5mm*0.5mm～10mm*10mm之间。当所述对位标记200为如图6d所示的形状时，正方形的尺寸介于0.5mm*0.5mm～10mm*10mm之间。
所述对比标记200均匀分布于所述第一基底100上，以便于后续对所述第一基底100的切割。在其他实施例中，所述第一基底100上，也可以将不同形状的所述对位标记200进行排版，最大程度的利用所述第一基底100，当然，要以后续可以切割所述第一基底100以分离相邻所述对位标记200为前提。
在所述第一基底100上形成多个对位标记200之后，切割所述第一基底 100，以形成多个用于对位的对位晶粒300，每个所述对位晶粒300包括切割后的第一基底100以及形成于所述切割后的第一基底100上的至少一个对位标记200。其中，每一对位晶粒300包含至少一个对位标记200，作为优选实施例，每一对位晶粒300中包含一个对位标记200，具体如图4所示。切割后的所述第一基底100的形状例如是方形，所述对位标记200的形状例如是十字形。
接着，提供一需要对位的第二基底400，所述第二基底400可以为硅基底，也可以是锗、锗硅、砷化镓基底或绝缘体上硅基底。本领域技术人员可以根据需要选择第二基底，因此第二基底的类型不应限制本发明的保护范围。优选的，所述第二基底400为硅基底。所述第二基底400可以是需要完成对位的任意基底，在所述第二基底400上可以形成有任意的半导体器件，例如可以包括存储器、逻辑电路、功率器件、双极器件、单独的MOS晶体管、微机电系统(MEMS)等有源器件，甚至也可以包括发光二极管等光电器件，其也可以包括无源器件，例如电阻、电容等，本发明对此不做限定。当然，所述第二基底400也可以是裸基底，后续完成对位与键合之后，可以剥离并重复使用。
然后，如图5所示，在所述第二基底400上形成键合薄膜500。可以采用滚压、旋涂、喷涂、印刷、非旋转涂覆、热压、真空压合、浸泡、压力贴合等方法在所述第二基底400上形成键合薄膜500。所述键合薄膜500可以为临时键合薄膜，例如可以为热塑或热固型有机材料，也可以是含有Cu(铜)、Ni(镍)、Cr(铬)、Co(钴)等成分的无机材料，可以通过加热、机械、化学、激光、冷冻等方式拆除。所述键合薄膜500也可以为永久键合薄膜，例如可以为粘片膜(Die Attach Film，DAF)或干膜(dry film)。所述粘片膜例如可以是树脂胶，特别是高导热的树脂胶，以起到粘接作用。所述干膜是一种高分子的化合物，它通过紫外线的照射后能够产生一种聚合反应形成一种稳定的物质附着于所述第二基底400的待键合表面，以起到粘接作用。
接着，请继续参考图5所示，采用晶粒贴附(die attach)工艺将所述对位晶粒300贴附于所述第二基底400的对位区域的所述键合薄膜500上。本实 施例中，所述晶粒贴附工艺包括：将所述对位晶粒300放置于所述第二基底400的对位区域的所述键合薄膜500上并施加压力完成贴附。在贴附过程中，施加的压力为0.1N～5N，施加压力时的温度为23℃～80℃，施加压力的时间为0.1s～5s，以使所述对位晶粒300完全贴附于所述第二基底400的所述键合薄膜500上，提高贴附的成功率。
所述第二基底400上设置有至少两个对位区域，优选为两个对位区域，两个所述对位区域位于所述第二基底400的相对两侧。每个所述对位晶粒300贴附于一个对位区域内，较佳方案中，所述对位晶粒300的贴附精度小于等于3μm。所述贴附精度是指实际贴附位置相对于理想贴附位置的偏移量，从而可以保证所述对位晶粒300精确的贴附于所述对位区域内，以完成所述的第二基底400与后续基底的对位，使得对位精度提高，以提高半导体器件的性能。
在一实施例中，还包括：将所述第二基底400贴附有所述对位晶粒300的一面与一第三基底进行对位与键合。利用所述对位晶粒300完成所述第二基底400与所述第三基底的对位，利用所述键合薄膜500完成所述第二基底400与所述第三基底的键合。所述键合可以是临时键合与永久键合，若是临时键合，则所述第二基底400能够重复使用。即完成对位与临时键合，并完成后续工艺制程后，将所述第二基底400与所述第三基底分离，并剥离所述第二基底400上剩余的键合薄膜500与对位晶粒300，然后可以在所述第二基底上再次形成键合薄膜并贴附对位晶粒以再次进行对位与键合。
所述第三基底可以是以下所提到的半导体材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。所述第三基底为需要完成对位与键合的基底，所述第三基底上可以形成有任意的半导体器件，所述第三基底也可以为裸基底，本发明对此不作限定。
在另一实施例中，还包括：在所述第二基底400贴附有所述对位晶粒300 的一面上粘贴芯片。利用所述对位晶粒300完成所述第二基底400与所述芯片底的对位，利用所述键合薄膜500完成所述第二基底400与所述芯片的粘贴。
将图1与图5进行比较可知，在图1中，键合薄膜30形成于所述对位标记20之上，需要对所述键合薄膜30进行切割，由此形成空白区域30’，而在图5中，对位晶粒300形成于所述键合薄膜500之上，并不需要对键合薄膜500进行切割，节省了工艺步骤与工艺时间，并节省了键合薄膜500，同时提高了第二基底400的可用面积。并且若所述键合为临时键合，针对图1所示的结构，承载晶圆10被剥离之后，若其上的对位标记20还保留在所述承载晶圆10上，则该承载晶圆10仅能用于相同类型的对位与键合，若其上的对位标记20被从承载晶圆10上剥离时，则需要在所述承载晶圆10上重新制作对位标记，即要么受限于对位与键合的类型，要么重新制作对位标记。而针对图5所示的结构，所述第二基底400被剥离之后，由于对位晶粒300形成于所述键合薄膜500之上，所述对位晶粒300同样会被剥离，则只需要在所述第二基底400上重新贴附对位晶粒300即可，并且，可以贴附具有不同形状的对位标记的对位晶粒300，即仅需要贴附对位晶粒300即可，并不受对位与键合的类型的限制，也无需增加制作对位标记的工艺步骤。因此，与图1所记载的方法相比，本实施例所提供的半导体器件的制作方法，提高了第二基底的利用率，并进一步节省了工艺步骤，降低了生产成本，提高了生产效率。
需要说明的是，在本发明实施例中，需要将包含有切割后的第一基底以及形成于所述切割后的第一基底上的对位标记的对位晶粒贴附于第二基底上，而现有技术是直接在对位基底上形成对位标记，本申请实施例中所述对位晶粒的厚度要大于现有技术中对位标记的厚度，因此，所述承载基底的厚度不应该太厚，否则所述对位晶粒的厚度太厚会对后续的对位造成影响，另一方面，所述承载基底的厚度也不应该太薄，否则会影响在其上形成对位标记的步骤。因此所述承载基底的厚度需要根据实际情况来确定。
综上所述，本发明实施例提供的半导体器件的制作方法中，提供一第一 基底100，并在所述第一基底100上形成多个对位标记200，然后切割所述第一基底100，以形成多个用于对位的对位晶粒300，每个所述对位晶粒300包括切割后的第一基底100以及形成于所述切割后的第一基底100上的至少一个对位标记200，接着提供一需要对位的第二基底400，并在所述第二基底400上形成键合薄膜500；采用晶粒贴附工艺将所述对位晶粒300贴附于所述第二基底400的对位区域的所述键合薄膜500上。本发明先制作多个包含对位标记200的对位晶粒300，在第二基底400需要对位时，只需将对位晶粒300贴附于第二基底400上即可，并不需要每次都在第二基底400上采用掩模板制作对位标记，节省了工艺步骤，降低了生产成本，提高了生产效率。并且，在将对位晶粒300贴附于所述第二基底400之前，在所述第二基底400上形成键合薄膜500，对位晶粒300形成于所述键合薄膜500之上，从而避免对所述键合薄膜500的切割，节省了工艺步骤，并节省了键合薄膜500，同时提高了第二基底400的可用面积。
相应的，本发明还提供一种半导体器件，采用如上所述的方法制造而成，请参考图4与图5所示，所述半导体器件包括：
第二基底400，所述第二基底400上形成有键合薄膜500；
用于所述第二基底400对位的对位晶粒300，位于所述第二基底400的对位区域的所述键合薄膜500之上，所述对位晶粒300包含切割后的第一基底100以及形成于所述切割后的第一基底100上的至少一个对位标记200，所述切割后的第一基底100贴附于所述键合薄膜500上。
在图4与图5中，所述对位标记200的形状均采用十字型，所述对位标记200的形状还可以采用米字型、圆形、椭圆形、长方形、正方形中的一种或多种的任意组合。请参看图6a所示，所述对位标记200的形状可以为十字型，其中，该十字型的横条和竖条的尺寸优选是相同的。请参考图6b所示，所述对位标记200的形状也可以为米字型，即为十字型与椭圆形的组合，其中，该十字型的横条和竖条的尺寸优选是相同的，以及，该米字型中的四个椭圆形的尺寸亦优选是相同的。请参考图6c所示，所述对位标记200的形状 为圆形。请参考图6d所示，所述对位标记200的形状为正方形与圆形的组合，例如是一个正方形中均匀分布四个尺寸相同的圆形。以上结合图6a-6d介绍了几种形状的标记，在具体实施例时并不限于上述举例，所述对位标记200可以是同一形状多种数量的组合，也可以是多种形状的组合。
所述对位标记200的最大尺寸介于0.5mm*0.5mm～10mm*10mm之间。例如，当所述对位标记200为如图6a所示的形状时，十字型中横条与竖条的尺寸均介于0.5mm*0.5mm～10mm*10mm之间。当所述对位标记200为如图6d所示的形状时，正方形的尺寸介于0.5mm*0.5mm～10mm*10mm之间。
进一步的，所述第一基底100为半导体材料基底，所述第一基底100可以为硅基底，也可以是锗、锗硅、砷化镓基底或绝缘体上硅基底，本领域技术人员可以根据需要选择第一基底100的材料，因此第一基底100的类型不应限制本发明的保护范围。本实施例中，所述第一基底100为硅基底。
所述第二基底400上设置有至少两个对位区域，两个所述对位区域位于所述的第二基底400的相对两侧。在图5中，所述第二基底400呈圆形，两个所述对位区域位于所述对位基底400的直径的任意两点上，两个所述对位晶粒30分别位于两个所述对位区域内。
进一步的，所述半导体器件还包括第三基底，所述第三基底与所述第二基底400贴附有所述对位晶粒300的一面对位键合。或者，所述半导体器件还包括芯片，粘贴于所述第二基底400贴附有所述对位晶粒300的一面上。
相应的，本发明还提供一种对位标记的制作方法，包括：提供半导体材料基底，在所述半导体材料基底上形成多个对位标记，所述多个对位标记遍布所述半导体材料基底。
具体的，在所述半导体材料基底上形成由不透光材料所形成的遮光层，例如，可采用PVD(Physical Vapor Deposition，物理气相沉积)等方法在所述半导体材料基底上形成由所述不透光材料所形成的遮光层。其中，所述不透光材料(即所述遮光层)通常可以为金属材料，如可以为铝层、钨层、铬层，所述不透光材料(即所述遮光层)也可以是金属化合物导电层。然后在所述 遮光层上形成第一光刻胶层，并利用掩膜板对所述第一光刻胶层进行曝光与显影以形成图形化的第一光刻胶层，再以图形化的第一光刻胶层为掩膜对所述遮光层进行刻蚀，以在所述半导体材料基底上形成多个对位标记，所述多个对位标记遍布所述半导体材料基底。最后，可以通过灰化工艺去除图形化的所述第一光刻胶层。
在一实施例中，在形成所述对位标记之前或之后，还可以在所述半导体材料基底上形成切割道，以方便后续对所述半导体材料基底的切割。具体的，在所述半导体材料基底上形成第二光刻胶层，利用掩膜板对所述第二光刻胶层进行曝光与显影以形成图形化的第二光刻胶层，暴露出切割道区域内的所述半导体材料基底。接着，以图形化的第二光刻胶层为掩膜对所述半导体材料基底进行刻蚀，以形成凹槽，所述凹槽即为切割道。最后，可以通过灰化工艺去除图形化的所述第二光刻胶层。
在另一实施例中，也可以在形成所述对位标记的过程中形成所述切割道，即所述切割道与所述对位标记在同一工艺过程中形成。具体的，利用掩膜板对所述第一光刻胶层进行曝光与显影以形成图形化的第一光刻胶层，图形化的所述第一光刻胶层不仅暴露出预定形成所述对位标记的区域，还暴露出切割道区域。接着，以图形化的所述第一光刻胶层为掩膜对所述遮光层进行刻蚀，刻蚀预定形成对位标记的区域内的所述遮光层，以在所述半导体材料基底上形成多个对位标记，同时刻蚀切割道区域内的所述遮光层，形成凹槽以构成切割道。最后，通过灰化工艺去除图形化的所述的第一光刻胶层。
所述对位标记的制作方法还包括：形成多个对位标记后，切割所述半导体材料基底，以形成多个用于对位的对位晶粒。在后续需要进行对位与键合时，在需要对位键合的基底上形成键合薄膜之后，可以直接将所述对位晶粒贴附于所述基底的对位区域上，采用对位晶粒即可以完成基底的对位，并不需要每次都在基底上采用掩模板制作对位标记，节省了工艺步骤，降低了生产成本，提高了生产效率，并且由于对位晶粒位于所述键合薄膜上，可以避免对所述键合薄膜的切割，节省了工艺步骤，并节省了键合薄膜，同时提高了基底的可用面积。
综上所述，本发明提供的半导体器件及其制作方法、对位标记的制作方法中，先制作多个包含对位标记的对位晶粒，在第二基底需要对位时，只需将对位晶粒贴附于第二基底上即可，并不需要每次都在第二基底上采用掩模板制作对位标记，节省了工艺步骤，降低了生产成本，提高了生产效率。并且，在将对位晶粒贴附于所述第二基底之前，在所述第二基底上形成键合薄膜，对位晶粒形成于所述键合薄膜之上，从而避免对所述键合薄膜的切割，节省了工艺步骤，并节省了键合薄膜，同时提高了第二基底的可用面积。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (21)

  1. 一种半导体器件的制作方法，其特征在于，包括以下步骤：
    提供第一基底，并在所述第一基底上形成多个对位标记；
    切割所述第一基底，以形成多个用于对位的对位晶粒，每个所述对位晶粒包括切割后的第一基底以及形成于所述切割后的第一基底上的至少一个对位标记；
    提供一需要对位的第二基底，并在所述第二基底上形成键合薄膜；
    采用晶粒贴附工艺将所述对位晶粒贴附于所述第二基底的对位区域的所述键合薄膜上。
  2. 如权利要求1所述的半导体器件的制作方法，其特征在于，还包括：将所述第二基底贴附有所述对位晶粒的一面与一第三基底进行对位与键合。
  3. 如权利要求2所述的半导体器件的制作方法，其特征在于，所述键合为临时键合，所述第二基底与所述第三基底分离之后，能够再次在所述第二基底上形成键合薄膜并贴附对位晶粒以进行对位与键合。
  4. 如权利要求1所述的半导体器件的制作方法，其特征在于，还包括：在所述第二基底贴附有所述对位晶粒的一面上粘贴芯片。
  5. 如权利要求1所述的半导体器件的制作方法，其特征在于，所述晶粒贴附工艺包括：将所述对位晶粒放置于所述第二基底的对位区域的所述键合薄膜上并施加压力。
  6. 如权利要求5所述的半导体器件的制作方法，其特征在于，施加的压力为0.1N～5N，施加压力时的温度为23℃～80℃，施加压力的时间为0.1s～5s。
  7. 如权利要求1所述的半导体器件的制作方法，其特征在于，所述第一基底为半导体材料基底；所述键合薄膜的材料为：热塑或热固型有机材料，含有铜、镍、铬或钴成分的无机材料，粘片膜或干膜。
  8. 如权利要求1所述的半导体器件的制作方法，其特征在于，在所述第一基底上形成多个对位标记的方法包括：
    依次形成遮光层与第一光刻胶层在所述第一基底上；
    图形化所述第一光刻胶层；
    以图形化的所述第一光刻胶层为掩膜，刻蚀所述遮光层，以形成多个对位标记；
    去除图形化的所述第一光刻胶层。
  9. 如权利要求8所述的半导体器件的制作方法，其特征在于，还包括：在所述第一基底上形成切割道，所述切割道与所述对位标记在同一工艺过程中形成；刻蚀所述遮光层以形成多个对位标记的过程中，同时刻蚀切割道区域内的所述遮光层，形成凹槽以构成切割道。
  10. 如权利要求8所述的半导体器件的制作方法，其特征在于，在形成所述对位标记之前或之后，还包括：
    形成第二光刻胶层在所述第一基底上；
    图形化所述第二光刻胶层，暴露出切割道区域内的所述第一基底；
    以图形化的所述第二光刻胶层为掩膜，刻蚀所述第一基底，形成凹槽以构成切割道；
    去除图形化的所述第二光刻胶层。
  11. 如权利要求1所述的半导体器件的制作方法，其特征在于，所述第二基底上设置有至少两个对位区域，两个所述对位区域位于所述第二基底的相对两侧。
  12. 如权利要求1所述的半导体器件的制作方法，其特征在于，所述对位晶粒的贴附精度小于等于3μm。
  13. 如权利要求1所述的半导体器件的制作方法，其特征在于，所述对位标记的形状包含：十字型、米字型、圆形、椭圆形、长方形、正方形中的一种或多种。
  14. 如权利要求1所述的半导体器件的制作方法，其特征在于，所述对位标记的最大尺寸介于0.5mm*0.5mm～10mm*10mm之间。
  15. 一种半导体器件，其特征在于，包括：
    第二基底，所述第二基底上形成有键合薄膜；
    用于所述第二基底对位的对位晶粒，位于所述第二基底的对位区域的所 述键合薄膜之上，所述对位晶粒包含切割后的第一基底以及形成于所述切割后的第一基底上的至少一个对位标记，所述切割后的第一基底贴附于所述键合薄膜上。
  16. 如权利要求15所述的半导体器件，其特征在于，所述第一基底为半导体材料基底；所述第二基底上设置有至少两个对位区域，两个所述对位区域位于所述第二基底的相对两侧。
  17. 如权利要求15所述的半导体器件，其特征在于，所述对位标记的形状包含：十字型、米字型、圆形、椭圆形、长方形、正方形中的一种或多种。
  18. 如权利要求17所述的半导体器件，其特征在于，所述对位标记的最大尺寸介于0.5mm*0.5mm～10mm*10mm之间。
  19. 一种对位标记的制作方法，其特征在于，包括：
    提供半导体材料基底；
    在所述半导体材料基底上形成多个对位标记，所述多个对位标记遍布所述半导体材料基底。
  20. 如权利要求19所述的对位标记的制作方法，其特征在于，还包括：形成多个对位标记后，切割所述半导体材料基底，以形成多个用于对位的对位晶粒。
  21. 如权利要求19所述的对位标记的制作方法，其特征在于，形成多个对位标记的方法包括：
    依次形成遮光层与光刻胶层在所述半导体材料基底上；
    图形化所述光刻胶层；
    以图形化的所述光刻胶层为掩膜，刻蚀所述遮光层，以形成多个对位标记；
    去除图形化的所述光刻胶层。
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