JP7757223B2 - メモリデバイス - Google Patents

メモリデバイス

Info

Publication number
JP7757223B2
JP7757223B2 JP2022048021A JP2022048021A JP7757223B2 JP 7757223 B2 JP7757223 B2 JP 7757223B2 JP 2022048021 A JP2022048021 A JP 2022048021A JP 2022048021 A JP2022048021 A JP 2022048021A JP 7757223 B2 JP7757223 B2 JP 7757223B2
Authority
JP
Japan
Prior art keywords
region
electrode portion
pad
electrode
bpd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022048021A
Other languages
English (en)
Japanese (ja)
Other versions
JP2023141616A5 (https=
JP2023141616A (ja
Inventor
絢子 川西
伸也 荒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Priority to JP2022048021A priority Critical patent/JP7757223B2/ja
Priority to TW111130066A priority patent/TWI834241B/zh
Priority to US17/822,248 priority patent/US12388031B2/en
Priority to CN202211070105.5A priority patent/CN116867274A/zh
Publication of JP2023141616A publication Critical patent/JP2023141616A/ja
Publication of JP2023141616A5 publication Critical patent/JP2023141616A5/ja
Priority to US19/224,980 priority patent/US20250293181A1/en
Application granted granted Critical
Publication of JP7757223B2 publication Critical patent/JP7757223B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Non-Volatile Memory (AREA)
JP2022048021A 2022-03-24 2022-03-24 メモリデバイス Active JP7757223B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2022048021A JP7757223B2 (ja) 2022-03-24 2022-03-24 メモリデバイス
TW111130066A TWI834241B (zh) 2022-03-24 2022-08-10 記憶裝置
US17/822,248 US12388031B2 (en) 2022-03-24 2022-08-25 Memory device
CN202211070105.5A CN116867274A (zh) 2022-03-24 2022-08-30 存储器装置
US19/224,980 US20250293181A1 (en) 2022-03-24 2025-06-02 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2022048021A JP7757223B2 (ja) 2022-03-24 2022-03-24 メモリデバイス

Publications (3)

Publication Number Publication Date
JP2023141616A JP2023141616A (ja) 2023-10-05
JP2023141616A5 JP2023141616A5 (https=) 2024-09-26
JP7757223B2 true JP7757223B2 (ja) 2025-10-21

Family

ID=88096429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022048021A Active JP7757223B2 (ja) 2022-03-24 2022-03-24 メモリデバイス

Country Status (4)

Country Link
US (2) US12388031B2 (https=)
JP (1) JP7757223B2 (https=)
CN (1) CN116867274A (https=)
TW (1) TWI834241B (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240057523A (ko) * 2022-10-24 2024-05-03 삼성전자주식회사 반도체 패키지
EP4566095A1 (en) * 2023-09-25 2025-06-11 Yangtze Memory Technologies Co., Ltd. Semiconductor device having dummy pad and method for forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021136320A (ja) 2020-02-26 2021-09-13 キオクシア株式会社 半導体装置およびその製造方法
JP2022035158A (ja) 2020-08-20 2022-03-04 キオクシア株式会社 半導体記憶装置
US20220085052A1 (en) 2020-09-17 2022-03-17 Kioxia Corporation Semiconductor memory device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106910746B (zh) * 2017-03-08 2018-06-19 长江存储科技有限责任公司 一种3d nand存储器件及其制造方法、封装方法
US11114171B2 (en) * 2017-11-08 2021-09-07 Samsung Electronics Co., Ltd. Non-volatile memory device
JP2019153675A (ja) 2018-03-02 2019-09-12 ルネサスエレクトロニクス株式会社 固体撮像装置およびその製造方法
KR102624170B1 (ko) * 2018-04-30 2024-01-12 삼성전자주식회사 3차원 반도체 메모리 장치
JP7273488B2 (ja) 2018-12-04 2023-05-15 ソニーセミコンダクタソリューションズ株式会社 半導体装置、及び電子機器
US10665607B1 (en) 2019-01-18 2020-05-26 Sandisk Technologies Llc Three-dimensional memory device including a deformation-resistant edge seal structure and methods for making the same
WO2021003635A1 (en) * 2019-07-08 2021-01-14 Yangtze Memory Technologies Co., Ltd. Structure and method for forming capacitors for three-dimensional nand
KR102739662B1 (ko) * 2019-09-02 2024-12-10 삼성전자주식회사 3차원 반도체 메모리 소자
US11233043B2 (en) * 2019-09-02 2022-01-25 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory device
JP2021136271A (ja) 2020-02-25 2021-09-13 キオクシア株式会社 半導体装置およびその製造方法
JP2021150511A (ja) * 2020-03-19 2021-09-27 キオクシア株式会社 半導体記憶装置
KR102942729B1 (ko) * 2021-05-21 2026-03-24 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
US12581930B2 (en) * 2021-11-29 2026-03-17 Samsung Electronics Co., Ltd. Semiconductor device including electrodes each having a pad part and electronic system including the same
US20230255037A1 (en) * 2022-02-04 2023-08-10 Samsung Electronics Co., Ltd. Three-dimensional non-volatile memory device including peripheral circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021136320A (ja) 2020-02-26 2021-09-13 キオクシア株式会社 半導体装置およびその製造方法
JP2022035158A (ja) 2020-08-20 2022-03-04 キオクシア株式会社 半導体記憶装置
US20220085052A1 (en) 2020-09-17 2022-03-17 Kioxia Corporation Semiconductor memory device

Also Published As

Publication number Publication date
TWI834241B (zh) 2024-03-01
TW202339225A (zh) 2023-10-01
JP2023141616A (ja) 2023-10-05
CN116867274A (zh) 2023-10-10
US20250293181A1 (en) 2025-09-18
US20230307387A1 (en) 2023-09-28
US12388031B2 (en) 2025-08-12

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