JP7728174B2 - 試験装置、電気的マージン試験方法及びマージン・テスタ - Google Patents

試験装置、電気的マージン試験方法及びマージン・テスタ

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Publication number
JP7728174B2
JP7728174B2 JP2021544930A JP2021544930A JP7728174B2 JP 7728174 B2 JP7728174 B2 JP 7728174B2 JP 2021544930 A JP2021544930 A JP 2021544930A JP 2021544930 A JP2021544930 A JP 2021544930A JP 7728174 B2 JP7728174 B2 JP 7728174B2
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Prior art keywords
margin
dut
link
test
selectable option
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JP2021544930A
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English (en)
Japanese (ja)
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JP2022524715A5 (https=
JP2022524715A (ja
Inventor
ダニエル・エス・フローリック
シェーン・エイ・ハザード
サラ・アール・ボーエン
ジェド・エイチ・アンドリュース
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Tektronix Inc
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Tektronix Inc
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Publication of JP2022524715A5 publication Critical patent/JP2022524715A5/ja
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dc Digital Transmission (AREA)
JP2021544930A 2019-01-31 2020-01-31 試験装置、電気的マージン試験方法及びマージン・テスタ Active JP7728174B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201962799720P 2019-01-31 2019-01-31
US62/799,720 2019-01-31
US201962804942P 2019-02-13 2019-02-13
US62/804,942 2019-02-13
PCT/US2020/016220 WO2020160477A1 (en) 2019-01-31 2020-01-31 Systems, methods and devices for high-speed input/output margin testing

Publications (3)

Publication Number Publication Date
JP2022524715A JP2022524715A (ja) 2022-05-10
JP2022524715A5 JP2022524715A5 (https=) 2022-12-28
JP7728174B2 true JP7728174B2 (ja) 2025-08-22

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JP2021544930A Active JP7728174B2 (ja) 2019-01-31 2020-01-31 試験装置、電気的マージン試験方法及びマージン・テスタ

Country Status (6)

Country Link
US (2) US12117486B2 (https=)
JP (1) JP7728174B2 (https=)
KR (1) KR20210119422A (https=)
CN (1) CN113396396B (https=)
DE (1) DE112020000640T5 (https=)
WO (1) WO2020160477A1 (https=)

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US11546128B2 (en) 2020-06-16 2023-01-03 SK Hynix Inc. Device and computing system including the device
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US12061232B2 (en) * 2020-09-21 2024-08-13 Tektronix, Inc. Margin test data tagging and predictive expected margins
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KR102635457B1 (ko) 2021-05-24 2024-02-13 에스케이하이닉스 주식회사 PCIe 장치 및 이를 포함하는 컴퓨팅 시스템
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KR102559387B1 (ko) * 2021-05-25 2023-07-26 에스케이하이닉스 주식회사 PCIe 인터페이스 장치 및 그 동작 방법
JP7381519B2 (ja) * 2021-06-09 2023-11-15 アンリツ株式会社 誤り率測定装置および誤り率測定方法
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JP7418388B2 (ja) * 2021-12-16 2024-01-19 株式会社日立製作所 演算装置、マージン測定方法
KR102926641B1 (ko) * 2022-08-22 2026-02-13 주식회사 엑시콘 테스트 슬롯 병렬 진단 장치
CN115525495B (zh) * 2022-10-21 2024-12-24 中科可控信息产业有限公司 一种高速串行总线的余量测试方法、装置、设备及介质
CN116048897B (zh) * 2022-12-30 2024-04-02 成都电科星拓科技有限公司 一种高速串行信号接收端压力眼图构造和测试方法及系统
CN115904849B (zh) * 2023-01-09 2023-05-12 苏州浪潮智能科技有限公司 Pcie链路信号测试方法、系统、计算机设备及介质
TWI883789B (zh) * 2024-01-17 2025-05-11 慧榮科技股份有限公司 記憶體控制器、固態儲存裝置及監看固態儲存裝置的鏈路信號品質的方法
CN120915871A (zh) * 2025-09-08 2025-11-07 深圳豪成科技有限公司 一种用于智能手机主板的测试方法及测试系统

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Also Published As

Publication number Publication date
CN113396396A (zh) 2021-09-14
US11946970B2 (en) 2024-04-02
US20200250368A1 (en) 2020-08-06
KR20210119422A (ko) 2021-10-05
US12117486B2 (en) 2024-10-15
US20200249275A1 (en) 2020-08-06
DE112020000640T5 (de) 2021-11-25
WO2020160477A1 (en) 2020-08-06
CN113396396B (zh) 2026-04-03
JP2022524715A (ja) 2022-05-10

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