CN113396396B - 高速输入/输出裕度测试的系统、方法和设备 - Google Patents
高速输入/输出裕度测试的系统、方法和设备Info
- Publication number
- CN113396396B CN113396396B CN202080011816.8A CN202080011816A CN113396396B CN 113396396 B CN113396396 B CN 113396396B CN 202080011816 A CN202080011816 A CN 202080011816A CN 113396396 B CN113396396 B CN 113396396B
- Authority
- CN
- China
- Prior art keywords
- margin
- test
- link
- channel
- dut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201962799720P | 2019-01-31 | 2019-01-31 | |
| US62/799720 | 2019-01-31 | ||
| US201962804942P | 2019-02-13 | 2019-02-13 | |
| US62/804942 | 2019-02-13 | ||
| PCT/US2020/016220 WO2020160477A1 (en) | 2019-01-31 | 2020-01-31 | Systems, methods and devices for high-speed input/output margin testing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113396396A CN113396396A (zh) | 2021-09-14 |
| CN113396396B true CN113396396B (zh) | 2026-04-03 |
Family
ID=69740777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080011816.8A Active CN113396396B (zh) | 2019-01-31 | 2020-01-31 | 高速输入/输出裕度测试的系统、方法和设备 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US12117486B2 (https=) |
| JP (1) | JP7728174B2 (https=) |
| KR (1) | KR20210119422A (https=) |
| CN (1) | CN113396396B (https=) |
| DE (1) | DE112020000640T5 (https=) |
| WO (1) | WO2020160477A1 (https=) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11940483B2 (en) | 2019-01-31 | 2024-03-26 | Tektronix, Inc. | Systems, methods and devices for high-speed input/output margin testing |
| US11828787B2 (en) * | 2020-02-28 | 2023-11-28 | Advantest Corporation | Eye diagram capture test during production |
| KR102518285B1 (ko) | 2021-04-05 | 2023-04-06 | 에스케이하이닉스 주식회사 | PCIe 인터페이스 및 인터페이스 시스템 |
| KR102519480B1 (ko) * | 2021-04-01 | 2023-04-10 | 에스케이하이닉스 주식회사 | PCIe 장치 및 이를 포함하는 컴퓨팅 시스템 |
| US11546128B2 (en) | 2020-06-16 | 2023-01-03 | SK Hynix Inc. | Device and computing system including the device |
| KR102415309B1 (ko) | 2020-06-16 | 2022-07-01 | 에스케이하이닉스 주식회사 | 인터페이스 장치 및 그 동작 방법 |
| JP2023535406A (ja) * | 2020-07-20 | 2023-08-17 | テクトロニクス・インコーポレイテッド | 再構成変更可能な処理コンポーネントを有する試験測定装置アクセサリ |
| CN112218324B (zh) * | 2020-09-02 | 2023-04-18 | 高新兴物联科技股份有限公司 | 一种无线终端的自动调测系统及调测方法 |
| US12061232B2 (en) * | 2020-09-21 | 2024-08-13 | Tektronix, Inc. | Margin test data tagging and predictive expected margins |
| TW202225714A (zh) * | 2020-11-09 | 2022-07-01 | 美商泰克特洛尼克斯公司 | 用於高速輸入/輸出餘裕測試的系統、方法和裝置 |
| US12055584B2 (en) | 2020-11-24 | 2024-08-06 | Tektronix, Inc. | Systems, methods, and devices for high-speed input/output margin testing |
| KR102635457B1 (ko) | 2021-05-24 | 2024-02-13 | 에스케이하이닉스 주식회사 | PCIe 장치 및 이를 포함하는 컴퓨팅 시스템 |
| US11960367B2 (en) | 2021-05-24 | 2024-04-16 | SK Hynix Inc. | Peripheral component interconnect express device and operating method thereof |
| KR102559387B1 (ko) * | 2021-05-25 | 2023-07-26 | 에스케이하이닉스 주식회사 | PCIe 인터페이스 장치 및 그 동작 방법 |
| JP7381519B2 (ja) * | 2021-06-09 | 2023-11-15 | アンリツ株式会社 | 誤り率測定装置および誤り率測定方法 |
| US20220200712A1 (en) * | 2021-10-14 | 2022-06-23 | Intel Corporation | Link monitoring and indication of potential link failure |
| JP7418388B2 (ja) * | 2021-12-16 | 2024-01-19 | 株式会社日立製作所 | 演算装置、マージン測定方法 |
| KR102926641B1 (ko) * | 2022-08-22 | 2026-02-13 | 주식회사 엑시콘 | 테스트 슬롯 병렬 진단 장치 |
| CN115525495B (zh) * | 2022-10-21 | 2024-12-24 | 中科可控信息产业有限公司 | 一种高速串行总线的余量测试方法、装置、设备及介质 |
| CN116048897B (zh) * | 2022-12-30 | 2024-04-02 | 成都电科星拓科技有限公司 | 一种高速串行信号接收端压力眼图构造和测试方法及系统 |
| CN115904849B (zh) * | 2023-01-09 | 2023-05-12 | 苏州浪潮智能科技有限公司 | Pcie链路信号测试方法、系统、计算机设备及介质 |
| TWI883789B (zh) * | 2024-01-17 | 2025-05-11 | 慧榮科技股份有限公司 | 記憶體控制器、固態儲存裝置及監看固態儲存裝置的鏈路信號品質的方法 |
| CN120915871A (zh) * | 2025-09-08 | 2025-11-07 | 深圳豪成科技有限公司 | 一种用于智能手机主板的测试方法及测试系统 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103487623A (zh) * | 2012-06-11 | 2014-01-01 | 特克特朗尼克公司 | 串行数据链路测量与模拟系统 |
Family Cites Families (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5243273A (en) * | 1990-09-12 | 1993-09-07 | Hewlett-Packard Company | General purpose, reconfigurable system for processing serial bit streams |
| JPH0712896A (ja) * | 1993-06-14 | 1995-01-17 | Fujitsu Ltd | マージン試験回路 |
| JPH07264248A (ja) * | 1994-03-17 | 1995-10-13 | Fujitsu Ltd | アイ開口の測定方法及び装置 |
| US6351827B1 (en) | 1998-04-08 | 2002-02-26 | Kingston Technology Co. | Voltage and clock margin testing of memory-modules using an adapter board mounted to a PC motherboard |
| US6449742B1 (en) | 1999-08-11 | 2002-09-10 | Intel Corporation | Test and characterization of source synchronous AC timing specifications by trace length modulation of accurately controlled interconnect topology of the test unit interface |
| US6765877B1 (en) | 1999-08-30 | 2004-07-20 | Cisco Technology, Inc. | System and method for detecting unidirectional links |
| US7076714B2 (en) | 2000-07-31 | 2006-07-11 | Agilent Technologies, Inc. | Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors |
| US6694462B1 (en) | 2000-08-09 | 2004-02-17 | Teradyne, Inc. | Capturing and evaluating high speed data streams |
| CN100378465C (zh) | 2001-10-05 | 2008-04-02 | 松下电器产业株式会社 | Lsi检查方法及装置、lsi检测器 |
| US7099438B2 (en) * | 2002-06-14 | 2006-08-29 | Ixia | Multi-protocol, multi-interface communications device testing system |
| US7139949B1 (en) | 2003-01-17 | 2006-11-21 | Unisys Corporation | Test apparatus to facilitate building and testing complex computer products with contract manufacturers without proprietary information |
| US7505862B2 (en) | 2003-03-07 | 2009-03-17 | Salmon Technologies, Llc | Apparatus and method for testing electronic systems |
| US7398514B2 (en) | 2004-09-29 | 2008-07-08 | Microsoft Corporation | Test automation stack layering |
| US7313496B2 (en) | 2005-02-11 | 2007-12-25 | Advantest Corporation | Test apparatus and test method for testing a device under test |
| US7941718B2 (en) | 2006-03-07 | 2011-05-10 | Freescale Semiconductor, Inc. | Electronic device testing system |
| TW200821589A (en) | 2006-07-14 | 2008-05-16 | Dft Microsystems Inc | Signal integrity measurement systems and methods using a predominantly digital time-base generator |
| DE602006016659D1 (de) | 2006-12-22 | 2010-10-14 | Verigy Pte Ltd Singapore | Tester, verfahren zum testen einer zu prüfenden einrichtung und computerprogramm |
| WO2008098202A2 (en) | 2007-02-09 | 2008-08-14 | Dft Microsystems, Inc. | Physical-layer testing of high-speed serial links in their mission environments |
| US8289839B2 (en) | 2007-07-05 | 2012-10-16 | Cisco Technology, Inc. | Scaling BFD sessions for neighbors using physical / sub-interface relationships |
| TWI342403B (en) | 2007-09-29 | 2011-05-21 | Ind Tech Res Inst | Jitter measuring system and method |
| US7808252B2 (en) * | 2007-12-13 | 2010-10-05 | Advantest Corporation | Measurement apparatus and measurement method |
| JP5148690B2 (ja) | 2008-04-14 | 2013-02-20 | 株式会社アドバンテスト | 半導体試験装置および試験方法 |
| US8726112B2 (en) | 2008-07-18 | 2014-05-13 | Mentor Graphics Corporation | Scan test application through high-speed serial input/outputs |
| US8793541B2 (en) * | 2008-10-10 | 2014-07-29 | Teledyne Lecroy, Inc. | Link equalization tester |
| US20120043968A1 (en) | 2010-03-31 | 2012-02-23 | Advantest Corporation | Variable equalizer circuit |
| US8626474B2 (en) | 2010-04-19 | 2014-01-07 | Altera Corporation | Simulation tool for high-speed communications links |
| JP2012073166A (ja) * | 2010-09-29 | 2012-04-12 | Advantest Corp | 試験装置および試験方法 |
| JP2012118002A (ja) | 2010-12-03 | 2012-06-21 | Yokogawa Electric Corp | デバイステスタ |
| WO2012123969A2 (en) | 2011-03-14 | 2012-09-20 | Indian Institute Of Technology Bombay | Methods for generating multi-level pseudo-random sequences |
| US9275187B2 (en) | 2011-03-21 | 2016-03-01 | Ridgetop Group, Inc. | Programmable test chip, system and method for characterization of integrated circuit fabrication processes |
| US20130033285A1 (en) | 2011-08-02 | 2013-02-07 | Globalfoundries Inc. | Methods for reliability testing of semiconductor devices |
| CN106681938B (zh) | 2012-10-22 | 2020-08-18 | 英特尔公司 | 用于控制多时隙链路层微片中的消息收发的装置和系统 |
| US9536626B2 (en) | 2013-02-08 | 2017-01-03 | Intel Corporation | Memory subsystem I/O performance based on in-system empirical testing |
| GB2530518A (en) | 2014-09-24 | 2016-03-30 | Ibm | Method and apparatus for generating a multi-level Pseudo-Random Test |
| TW201809712A (zh) | 2014-10-29 | 2018-03-16 | 因諾帝歐股份有限公司 | 積體電路晶片測試裝置,方法及系統 |
| KR101618822B1 (ko) | 2014-10-29 | 2016-05-18 | (주)이노티오 | 스캔 테스트 시간 최소화 방법 및 그 장치 |
| US9551746B2 (en) | 2015-03-11 | 2017-01-24 | Dell Products L.P. | Backplane testing system |
| US9692589B2 (en) * | 2015-07-17 | 2017-06-27 | Intel Corporation | Redriver link testing |
| JP6741947B2 (ja) | 2016-09-29 | 2020-08-19 | 富士通株式会社 | 情報処理装置、診断制御装置および通信装置 |
| US10255151B1 (en) * | 2016-12-19 | 2019-04-09 | Amazon Technologies, Inc. | Security testing using a computer add-in card |
| US10198331B2 (en) | 2017-03-31 | 2019-02-05 | Stmicroelectronics International N.V. | Generic bit error rate analyzer for use with serial data links |
| US10475677B2 (en) | 2017-08-22 | 2019-11-12 | Globalfoundries Inc. | Parallel test structure |
| US10859626B2 (en) * | 2018-07-19 | 2020-12-08 | Futurewei Technologies, Inc. | Receiver equalization and stressed eye testing system |
| US11940483B2 (en) * | 2019-01-31 | 2024-03-26 | Tektronix, Inc. | Systems, methods and devices for high-speed input/output margin testing |
| US11774496B2 (en) | 2021-03-23 | 2023-10-03 | Indian Institute Of Technology | Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof |
| CN116110336A (zh) * | 2021-11-11 | 2023-05-12 | 三星电子株式会社 | 显示驱动电路、包括其的显示设备以及操作其的方法 |
-
2020
- 2020-01-31 US US16/778,262 patent/US12117486B2/en active Active
- 2020-01-31 KR KR1020217025025A patent/KR20210119422A/ko not_active Withdrawn
- 2020-01-31 JP JP2021544930A patent/JP7728174B2/ja active Active
- 2020-01-31 US US16/778,249 patent/US11946970B2/en active Active
- 2020-01-31 CN CN202080011816.8A patent/CN113396396B/zh active Active
- 2020-01-31 DE DE112020000640.9T patent/DE112020000640T5/de active Pending
- 2020-01-31 WO PCT/US2020/016220 patent/WO2020160477A1/en not_active Ceased
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103487623A (zh) * | 2012-06-11 | 2014-01-01 | 特克特朗尼克公司 | 串行数据链路测量与模拟系统 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113396396A (zh) | 2021-09-14 |
| US11946970B2 (en) | 2024-04-02 |
| JP7728174B2 (ja) | 2025-08-22 |
| US20200250368A1 (en) | 2020-08-06 |
| KR20210119422A (ko) | 2021-10-05 |
| US12117486B2 (en) | 2024-10-15 |
| US20200249275A1 (en) | 2020-08-06 |
| DE112020000640T5 (de) | 2021-11-25 |
| WO2020160477A1 (en) | 2020-08-06 |
| JP2022524715A (ja) | 2022-05-10 |
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