KR20210119422A - 고속 입력/출력 마진 테스팅을 위한 시스템, 방법 및 디바이스 - Google Patents

고속 입력/출력 마진 테스팅을 위한 시스템, 방법 및 디바이스 Download PDF

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KR20210119422A
KR20210119422A KR1020217025025A KR20217025025A KR20210119422A KR 20210119422 A KR20210119422 A KR 20210119422A KR 1020217025025 A KR1020217025025 A KR 1020217025025A KR 20217025025 A KR20217025025 A KR 20217025025A KR 20210119422 A KR20210119422 A KR 20210119422A
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Prior art keywords
margin
lane
link
speed
dut
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Korean (ko)
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대니얼 에스. 프롤리치
셰인 에이. 해저드
사라 알. 보엔
제드 에이치. 앤드류스
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텍트로닉스 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dc Digital Transmission (AREA)
KR1020217025025A 2019-01-31 2020-01-31 고속 입력/출력 마진 테스팅을 위한 시스템, 방법 및 디바이스 Withdrawn KR20210119422A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201962799720P 2019-01-31 2019-01-31
US62/799,720 2019-01-31
US201962804942P 2019-02-13 2019-02-13
US62/804,942 2019-02-13
PCT/US2020/016220 WO2020160477A1 (en) 2019-01-31 2020-01-31 Systems, methods and devices for high-speed input/output margin testing

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KR20210119422A true KR20210119422A (ko) 2021-10-05

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KR1020217025025A Withdrawn KR20210119422A (ko) 2019-01-31 2020-01-31 고속 입력/출력 마진 테스팅을 위한 시스템, 방법 및 디바이스

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Country Link
US (2) US12117486B2 (https=)
JP (1) JP7728174B2 (https=)
KR (1) KR20210119422A (https=)
CN (1) CN113396396B (https=)
DE (1) DE112020000640T5 (https=)
WO (1) WO2020160477A1 (https=)

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CN113396396A (zh) 2021-09-14
US11946970B2 (en) 2024-04-02
JP7728174B2 (ja) 2025-08-22
US20200250368A1 (en) 2020-08-06
US12117486B2 (en) 2024-10-15
US20200249275A1 (en) 2020-08-06
DE112020000640T5 (de) 2021-11-25
WO2020160477A1 (en) 2020-08-06
CN113396396B (zh) 2026-04-03
JP2022524715A (ja) 2022-05-10

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