JP7661663B2 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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JP7661663B2
JP7661663B2 JP2021097292A JP2021097292A JP7661663B2 JP 7661663 B2 JP7661663 B2 JP 7661663B2 JP 2021097292 A JP2021097292 A JP 2021097292A JP 2021097292 A JP2021097292 A JP 2021097292A JP 7661663 B2 JP7661663 B2 JP 7661663B2
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conductive pad
core ball
conductive
main surface
semiconductor device
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JP2022188977A (ja
JP2022188977A5 (enExample
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信一朗 関島
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2021097292A priority Critical patent/JP7661663B2/ja
Priority to US17/805,302 priority patent/US12406953B2/en
Priority to CN202210638855.1A priority patent/CN115472589A/zh
Priority to KR1020220069339A priority patent/KR20220167226A/ko
Publication of JP2022188977A publication Critical patent/JP2022188977A/ja
Publication of JP2022188977A5 publication Critical patent/JP2022188977A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
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    • H01L2224/81053—Bonding environment
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
JP2021097292A 2021-06-10 2021-06-10 半導体装置及び半導体装置の製造方法 Active JP7661663B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2021097292A JP7661663B2 (ja) 2021-06-10 2021-06-10 半導体装置及び半導体装置の製造方法
US17/805,302 US12406953B2 (en) 2021-06-10 2022-06-03 Semiconductor apparatus and method of making semiconductor apparatus
CN202210638855.1A CN115472589A (zh) 2021-06-10 2022-06-07 半导体装置及半导体装置的制造方法
KR1020220069339A KR20220167226A (ko) 2021-06-10 2022-06-08 반도체 장치 및 반도체 장치의 제조 방법

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JP2021097292A JP7661663B2 (ja) 2021-06-10 2021-06-10 半導体装置及び半導体装置の製造方法

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JP2022188977A JP2022188977A (ja) 2022-12-22
JP2022188977A5 JP2022188977A5 (enExample) 2024-04-11
JP7661663B2 true JP7661663B2 (ja) 2025-04-15

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US (1) US12406953B2 (enExample)
JP (1) JP7661663B2 (enExample)
KR (1) KR20220167226A (enExample)
CN (1) CN115472589A (enExample)

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Publication number Priority date Publication date Assignee Title
US20250323136A1 (en) * 2024-04-12 2025-10-16 Qualcomm Incorporated Integrated circuit (ic) package including two substrates and vertical interconnects coupling the two substrates, the vertical interconnects comprising a metal ball and metal pin combination to address an increased distance between substrates

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007069606A1 (ja) 2005-12-14 2007-06-21 Shinko Electric Industries Co., Ltd. チップ内蔵基板およびチップ内蔵基板の製造方法
JP2011187635A (ja) 2010-03-08 2011-09-22 Hitachi Metals Ltd 半導体装置およびその製造方法
JP2012099642A (ja) 2010-11-02 2012-05-24 Hitachi Metals Ltd 半導体装置、それを用いた電子部品およびそれらの製造方法

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JP3270813B2 (ja) * 1995-07-11 2002-04-02 株式会社ピーエフユー 半導体装置とその製造方法
US5926694A (en) * 1996-07-11 1999-07-20 Pfu Limited Semiconductor device and a manufacturing method thereof
JPH10270496A (ja) * 1997-03-27 1998-10-09 Hitachi Ltd 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法
US6610591B1 (en) * 2000-08-25 2003-08-26 Micron Technology, Inc. Methods of ball grid array
US20080142968A1 (en) * 2006-12-15 2008-06-19 International Business Machines Corporation Structure for controlled collapse chip connection with a captured pad geometry
JP5525793B2 (ja) * 2009-10-19 2014-06-18 パナソニック株式会社 半導体装置
JP5421863B2 (ja) 2010-06-28 2014-02-19 新光電気工業株式会社 半導体パッケージの製造方法
US20130043573A1 (en) * 2011-08-15 2013-02-21 Advanced Analogic Technologies (Hong Kong) Limited Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores
JP6352644B2 (ja) * 2014-02-12 2018-07-04 新光電気工業株式会社 配線基板及び半導体パッケージの製造方法
US10157850B1 (en) * 2017-07-28 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007069606A1 (ja) 2005-12-14 2007-06-21 Shinko Electric Industries Co., Ltd. チップ内蔵基板およびチップ内蔵基板の製造方法
JP2011187635A (ja) 2010-03-08 2011-09-22 Hitachi Metals Ltd 半導体装置およびその製造方法
JP2012099642A (ja) 2010-11-02 2012-05-24 Hitachi Metals Ltd 半導体装置、それを用いた電子部品およびそれらの製造方法

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JP2022188977A (ja) 2022-12-22
KR20220167226A (ko) 2022-12-20
US20220399293A1 (en) 2022-12-15
US12406953B2 (en) 2025-09-02
CN115472589A (zh) 2022-12-13

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