JP7517989B2 - 表示装置、表示モジュール、及び電子機器 - Google Patents
表示装置、表示モジュール、及び電子機器 Download PDFInfo
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- JP7517989B2 JP7517989B2 JP2020540867A JP2020540867A JP7517989B2 JP 7517989 B2 JP7517989 B2 JP 7517989B2 JP 2020540867 A JP2020540867 A JP 2020540867A JP 2020540867 A JP2020540867 A JP 2020540867A JP 7517989 B2 JP7517989 B2 JP 7517989B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
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- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
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- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
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- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
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- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/018—Bonding of wafers
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- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
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- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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- H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
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- H10H20/01—Manufacture or treatment
- H10H20/036—Manufacture or treatment of packages
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- H10H20/80—Constructional details
- H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
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- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
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- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
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- H10H20/80—Constructional details
- H10H20/85—Packages
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- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
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- H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
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- General Physics & Mathematics (AREA)
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Human Computer Interaction (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
- Led Device Packages (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024107866A JP7679531B2 (ja) | 2018-09-05 | 2024-07-04 | 表示装置 |
| JP2025077156A JP2025114706A (ja) | 2018-09-05 | 2025-05-07 | 表示装置 |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018166335 | 2018-09-05 | ||
| JP2018166336 | 2018-09-05 | ||
| JP2018166336 | 2018-09-05 | ||
| JP2018166335 | 2018-09-05 | ||
| PCT/IB2019/057065 WO2020049392A1 (ja) | 2018-09-05 | 2019-08-22 | 表示装置、表示モジュール、電子機器、及び表示装置の作製方法 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024107866A Division JP7679531B2 (ja) | 2018-09-05 | 2024-07-04 | 表示装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2020049392A1 JPWO2020049392A1 (ja) | 2021-09-24 |
| JP7517989B2 true JP7517989B2 (ja) | 2024-07-17 |
Family
ID=69722321
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020540867A Active JP7517989B2 (ja) | 2018-09-05 | 2019-08-22 | 表示装置、表示モジュール、及び電子機器 |
| JP2024107866A Active JP7679531B2 (ja) | 2018-09-05 | 2024-07-04 | 表示装置 |
| JP2025077156A Pending JP2025114706A (ja) | 2018-09-05 | 2025-05-07 | 表示装置 |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024107866A Active JP7679531B2 (ja) | 2018-09-05 | 2024-07-04 | 表示装置 |
| JP2025077156A Pending JP2025114706A (ja) | 2018-09-05 | 2025-05-07 | 表示装置 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US11908850B2 (enExample) |
| JP (3) | JP7517989B2 (enExample) |
| KR (1) | KR20210043641A (enExample) |
| CN (2) | CN112639937B (enExample) |
| TW (1) | TWI829746B (enExample) |
| WO (1) | WO2020049392A1 (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108493209B (zh) * | 2018-05-24 | 2020-06-23 | 京东方科技集团股份有限公司 | 一种显示基板、显示装置以及显示基板的制作方法 |
| CN117316973A (zh) | 2018-09-07 | 2023-12-29 | 株式会社半导体能源研究所 | 显示装置、显示模块及电子设备 |
| KR20200091818A (ko) * | 2019-01-23 | 2020-07-31 | 소후 인코포레이티드 | 도포성이 우수한 치과용 도재 페이스트 |
| WO2020217959A1 (ja) * | 2019-04-23 | 2020-10-29 | 京セラ株式会社 | マイクロled素子基板および表示装置 |
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