JP7380697B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP7380697B2
JP7380697B2 JP2021551077A JP2021551077A JP7380697B2 JP 7380697 B2 JP7380697 B2 JP 7380697B2 JP 2021551077 A JP2021551077 A JP 2021551077A JP 2021551077 A JP2021551077 A JP 2021551077A JP 7380697 B2 JP7380697 B2 JP 7380697B2
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JP
Japan
Prior art keywords
power
line
power line
power supply
semiconductor device
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JP2021551077A
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English (en)
Japanese (ja)
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JPWO2021070366A5 (https=
JPWO2021070366A1 (https=
Inventor
ウェンゼン ワン
淳 岡本
紘宜 武野
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Socionext Inc
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Socionext Inc
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Priority to JP2023186192A priority Critical patent/JP7529121B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/481—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes on the rear surfaces of the wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/981—Power supply lines

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2021551077A 2019-10-11 2019-10-11 半導体装置 Active JP7380697B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023186192A JP7529121B2 (ja) 2019-10-11 2023-10-31 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/040258 WO2021070366A1 (ja) 2019-10-11 2019-10-11 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2023186192A Division JP7529121B2 (ja) 2019-10-11 2023-10-31 半導体装置

Publications (3)

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JPWO2021070366A1 JPWO2021070366A1 (https=) 2021-04-15
JPWO2021070366A5 JPWO2021070366A5 (https=) 2022-12-01
JP7380697B2 true JP7380697B2 (ja) 2023-11-15

Family

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Family Applications (2)

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JP2021551077A Active JP7380697B2 (ja) 2019-10-11 2019-10-11 半導体装置
JP2023186192A Active JP7529121B2 (ja) 2019-10-11 2023-10-31 半導体装置

Family Applications After (1)

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JP2023186192A Active JP7529121B2 (ja) 2019-10-11 2023-10-31 半導体装置

Country Status (4)

Country Link
US (2) US12119301B2 (https=)
JP (2) JP7380697B2 (https=)
CN (1) CN114514604B (https=)
WO (1) WO2021070366A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7272426B2 (ja) * 2019-04-25 2023-05-12 株式会社ソシオネクスト 半導体装置
US20220328409A1 (en) * 2021-04-08 2022-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Targeted power grid structure and method
US11929325B2 (en) * 2021-08-18 2024-03-12 Qualcomm Incorporated Mixed pitch track pattern
JPWO2024252660A1 (https=) * 2023-06-09 2024-12-12
US20250006663A1 (en) * 2023-06-30 2025-01-02 International Business Machines Corporation Double-sided integrated circuit with electrostatic guard ring
WO2025079229A1 (ja) * 2023-10-13 2025-04-17 株式会社ソシオネクスト 半導体装置
WO2025079230A1 (ja) * 2023-10-13 2025-04-17 株式会社ソシオネクスト 半導体装置
WO2025079231A1 (ja) * 2023-10-13 2025-04-17 株式会社ソシオネクスト 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302198A (ja) 2008-06-11 2009-12-24 Elpida Memory Inc 半導体チップ、半導体チップ群および半導体装置
JP2012044042A (ja) 2010-08-20 2012-03-01 Kawasaki Microelectronics Inc 半導体集積回路および半導体集積回路装置
JP2014165358A (ja) 2013-02-26 2014-09-08 Panasonic Corp 半導体装置及びその製造方法
US20150187642A1 (en) 2013-12-30 2015-07-02 International Business Machines Corporation Double-sided segmented line architecture in 3d integration

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326689A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Semiconductor integrated circuit unit
JP2972425B2 (ja) * 1992-01-30 1999-11-08 日本電気アイシーマイコンシステム株式会社 半導体集積回路
JPH11102910A (ja) * 1997-09-29 1999-04-13 Hitachi Ltd 半導体集積回路
JP2009177200A (ja) * 1998-05-01 2009-08-06 Sony Corp 半導体記憶装置
JP2004186666A (ja) * 2002-10-09 2004-07-02 Fujitsu Ltd 半導体集積回路装置
JP2008098353A (ja) * 2006-10-11 2008-04-24 Nec Electronics Corp 半導体集積回路
JP2009124667A (ja) * 2007-01-25 2009-06-04 Panasonic Corp 双方向スイッチ及びその駆動方法
JP5519120B2 (ja) * 2008-05-27 2014-06-11 ルネサスエレクトロニクス株式会社 半導体装置
US8530273B2 (en) * 2010-09-29 2013-09-10 Guardian Industries Corp. Method of making oxide thin film transistor array
DE102013207324A1 (de) 2012-05-11 2013-11-14 Semiconductor Energy Laboratory Co., Ltd. Halbleitervorrichtung und elektronisches Gerät
US9793080B2 (en) * 2013-08-23 2017-10-17 Inoso, Llc Electromechanical power switch integrated circuits and devices and methods thereof
EP2884542A3 (en) 2013-12-10 2015-09-02 IMEC vzw Integrated circuit device with power gating switch in back end of line
JP6672626B2 (ja) * 2015-07-22 2020-03-25 富士通株式会社 半導体装置および半導体装置の制御方法
US9754923B1 (en) 2016-05-09 2017-09-05 Qualcomm Incorporated Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)
EP3324436B1 (en) 2016-11-21 2020-08-05 IMEC vzw An integrated circuit chip with power delivery network on the backside of the chip
JP6825476B2 (ja) * 2017-04-28 2021-02-03 株式会社ソシオネクスト 半導体装置
US10950546B1 (en) 2019-09-17 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including back side power supply circuit
US11004789B2 (en) 2019-09-30 2021-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including back side power supply circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302198A (ja) 2008-06-11 2009-12-24 Elpida Memory Inc 半導体チップ、半導体チップ群および半導体装置
JP2012044042A (ja) 2010-08-20 2012-03-01 Kawasaki Microelectronics Inc 半導体集積回路および半導体集積回路装置
JP2014165358A (ja) 2013-02-26 2014-09-08 Panasonic Corp 半導体装置及びその製造方法
US20150187642A1 (en) 2013-12-30 2015-07-02 International Business Machines Corporation Double-sided segmented line architecture in 3d integration

Also Published As

Publication number Publication date
WO2021070366A1 (ja) 2021-04-15
CN114514604B (zh) 2024-10-29
US12119301B2 (en) 2024-10-15
US20250006635A1 (en) 2025-01-02
JP7529121B2 (ja) 2024-08-06
JP2024001284A (ja) 2024-01-09
JPWO2021070366A1 (https=) 2021-04-15
CN114514604A (zh) 2022-05-17
US20220230954A1 (en) 2022-07-21

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