JP7340965B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP7340965B2
JP7340965B2 JP2019110519A JP2019110519A JP7340965B2 JP 7340965 B2 JP7340965 B2 JP 7340965B2 JP 2019110519 A JP2019110519 A JP 2019110519A JP 2019110519 A JP2019110519 A JP 2019110519A JP 7340965 B2 JP7340965 B2 JP 7340965B2
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Japan
Prior art keywords
opening
substrate
etching
taper angle
hole
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JP2019110519A
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English (en)
Japanese (ja)
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JP2020202353A5 (https=
JP2020202353A (ja
Inventor
達也 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
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Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2019110519A priority Critical patent/JP7340965B2/ja
Priority to US16/890,289 priority patent/US11437299B2/en
Publication of JP2020202353A publication Critical patent/JP2020202353A/ja
Publication of JP2020202353A5 publication Critical patent/JP2020202353A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H10P50/244—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials comprising alternated and repeated etching and passivation steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/216—Through-semiconductor vias, e.g. TSVs characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/241—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements
    • H10W44/248—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2019110519A 2019-06-13 2019-06-13 半導体装置およびその製造方法 Active JP7340965B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2019110519A JP7340965B2 (ja) 2019-06-13 2019-06-13 半導体装置およびその製造方法
US16/890,289 US11437299B2 (en) 2019-06-13 2020-06-02 Semiconductor apparatus and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019110519A JP7340965B2 (ja) 2019-06-13 2019-06-13 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2020202353A JP2020202353A (ja) 2020-12-17
JP2020202353A5 JP2020202353A5 (https=) 2022-06-20
JP7340965B2 true JP7340965B2 (ja) 2023-09-08

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JP2019110519A Active JP7340965B2 (ja) 2019-06-13 2019-06-13 半導体装置およびその製造方法

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JP (1) JP7340965B2 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240120425A1 (en) * 2022-10-06 2024-04-11 Canon Kabushiki Kaisha Semiconductor element and terahertz wave system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100013060A1 (en) 2008-06-22 2010-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench
JP2011204915A (ja) 2010-03-25 2011-10-13 Sony Corp 半導体装置、半導体装置の製造方法、半導体装置の設計方法、及び電子機器
JP2011222596A (ja) 2010-04-05 2011-11-04 Fujikura Ltd 半導体装置及びその製造方法
WO2016159320A1 (ja) 2015-03-31 2016-10-06 浜松ホトニクス株式会社 半導体装置及びその製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7081408B2 (en) * 2004-10-28 2006-07-25 Intel Corporation Method of creating a tapered via using a receding mask and resulting structure
JP5810921B2 (ja) 2012-01-06 2015-11-11 凸版印刷株式会社 半導体装置の製造方法
JP2013246021A (ja) * 2012-05-25 2013-12-09 Seiko Epson Corp 熱型電磁波検出素子、熱型電磁波検出素子の製造方法、熱型電磁波検出装置および電子機器
JP6443362B2 (ja) 2016-03-03 2018-12-26 株式会社デンソー 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100013060A1 (en) 2008-06-22 2010-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench
JP2011204915A (ja) 2010-03-25 2011-10-13 Sony Corp 半導体装置、半導体装置の製造方法、半導体装置の設計方法、及び電子機器
JP2011222596A (ja) 2010-04-05 2011-11-04 Fujikura Ltd 半導体装置及びその製造方法
WO2016159320A1 (ja) 2015-03-31 2016-10-06 浜松ホトニクス株式会社 半導体装置及びその製造方法

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US11437299B2 (en) 2022-09-06
JP2020202353A (ja) 2020-12-17
US20200395274A1 (en) 2020-12-17

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