JP7334849B2 - シリコン単結晶基板中のドナー濃度の制御方法 - Google Patents

シリコン単結晶基板中のドナー濃度の制御方法 Download PDF

Info

Publication number
JP7334849B2
JP7334849B2 JP2022508124A JP2022508124A JP7334849B2 JP 7334849 B2 JP7334849 B2 JP 7334849B2 JP 2022508124 A JP2022508124 A JP 2022508124A JP 2022508124 A JP2022508124 A JP 2022508124A JP 7334849 B2 JP7334849 B2 JP 7334849B2
Authority
JP
Japan
Prior art keywords
donor
single crystal
concentration
silicon single
crystal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022508124A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2021186944A1 (enExample
Inventor
博 竹野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of JPWO2021186944A1 publication Critical patent/JPWO2021186944A1/ja
Application granted granted Critical
Publication of JP7334849B2 publication Critical patent/JP7334849B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2022508124A 2020-03-17 2021-02-08 シリコン単結晶基板中のドナー濃度の制御方法 Active JP7334849B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020046938 2020-03-17
JP2020046938 2020-03-17
PCT/JP2021/004559 WO2021186944A1 (ja) 2020-03-17 2021-02-08 シリコン単結晶基板中のドナー濃度の制御方法

Publications (2)

Publication Number Publication Date
JPWO2021186944A1 JPWO2021186944A1 (enExample) 2021-09-23
JP7334849B2 true JP7334849B2 (ja) 2023-08-29

Family

ID=77771836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022508124A Active JP7334849B2 (ja) 2020-03-17 2021-02-08 シリコン単結晶基板中のドナー濃度の制御方法

Country Status (4)

Country Link
EP (1) EP4123686A4 (enExample)
JP (1) JP7334849B2 (enExample)
CN (1) CN115280472B (enExample)
WO (1) WO2021186944A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025084305A1 (ja) * 2023-10-17 2025-04-24 富士電機株式会社 半導体基板の評価方法および半導体装置の製造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006344977A (ja) 2005-06-08 2006-12-21 Infineon Technologies Ag 阻止ゾーンを半導体基板に製造する方法、および、阻止ゾーンを有する半導体部品
WO2007055352A1 (ja) 2005-11-14 2007-05-18 Fuji Electric Device Technology Co., Ltd. 半導体装置およびその製造方法
WO2011052787A1 (ja) 2009-11-02 2011-05-05 富士電機システムズ株式会社 半導体装置および半導体装置の製造方法
WO2013141221A1 (ja) 2012-03-19 2013-09-26 富士電機株式会社 半導体装置の製造方法
JP2015037194A (ja) 2013-08-14 2015-02-23 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ 半導体ディスクの後ドーピング方法
JP2016096338A (ja) 2014-11-14 2016-05-26 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ 半導体装置を形成する方法および半導体装置
JP2017063187A (ja) 2015-08-26 2017-03-30 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ 半導体デバイス、シリコンウェハ、及びシリコンウェハの製造方法
JP2019062189A (ja) 2017-08-18 2019-04-18 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ Ｃｚ半導体ボディを含む半導体装置およびｃｚ半導体ボディを含む半導体装置を製造する方法
WO2019239762A1 (ja) 2018-06-12 2019-12-19 信越半導体株式会社 シリコン単結晶基板中の欠陥密度の制御方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3341378B2 (ja) * 1993-08-25 2002-11-05 富士通株式会社 シリコン結晶中の水素濃度測定方法及びシリコン結晶の製造方法
JPH07301592A (ja) * 1994-05-09 1995-11-14 Fujitsu Ltd 半導体装置の製造方法及び気体中の水素濃度測定方法
JP3684962B2 (ja) 1999-12-01 2005-08-17 富士電機デバイステクノロジー株式会社 半導体装置の製造方法
CN107195677B (zh) * 2011-12-15 2021-02-05 富士电机株式会社 半导体装置和半导体装置的制造方法
EP2790208B1 (en) * 2012-03-19 2020-12-02 Fuji Electric Co., Ltd. Production method for semiconductor device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006344977A (ja) 2005-06-08 2006-12-21 Infineon Technologies Ag 阻止ゾーンを半導体基板に製造する方法、および、阻止ゾーンを有する半導体部品
WO2007055352A1 (ja) 2005-11-14 2007-05-18 Fuji Electric Device Technology Co., Ltd. 半導体装置およびその製造方法
WO2011052787A1 (ja) 2009-11-02 2011-05-05 富士電機システムズ株式会社 半導体装置および半導体装置の製造方法
WO2013141221A1 (ja) 2012-03-19 2013-09-26 富士電機株式会社 半導体装置の製造方法
JP2015037194A (ja) 2013-08-14 2015-02-23 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ 半導体ディスクの後ドーピング方法
JP2016096338A (ja) 2014-11-14 2016-05-26 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ 半導体装置を形成する方法および半導体装置
JP2017063187A (ja) 2015-08-26 2017-03-30 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ 半導体デバイス、シリコンウェハ、及びシリコンウェハの製造方法
JP2019062189A (ja) 2017-08-18 2019-04-18 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ Ｃｚ半導体ボディを含む半導体装置およびｃｚ半導体ボディを含む半導体装置を製造する方法
WO2019239762A1 (ja) 2018-06-12 2019-12-19 信越半導体株式会社 シリコン単結晶基板中の欠陥密度の制御方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025084305A1 (ja) * 2023-10-17 2025-04-24 富士電機株式会社 半導体基板の評価方法および半導体装置の製造方法

Also Published As

Publication number Publication date
EP4123686A4 (en) 2024-05-01
WO2021186944A1 (ja) 2021-09-23
CN115280472A (zh) 2022-11-01
CN115280472B (zh) 2025-07-25
EP4123686A1 (en) 2023-01-25
JPWO2021186944A1 (enExample) 2021-09-23

Similar Documents

Publication Publication Date Title
US8815708B2 (en) Method for improving the quality of a SiC crystal
KR102029647B1 (ko) 실리콘 단결정 기판의 결함 농도 평가 방법
JP6083412B2 (ja) 再結合ライフタイムの制御方法及びシリコン基板の製造方法
JP6292131B2 (ja) シリコン基板の選別方法
JP7334849B2 (ja) シリコン単結晶基板中のドナー濃度の制御方法
CN115315784B (zh) 单晶硅基板中的施主浓度的控制方法
JP6881292B2 (ja) 再結合ライフタイムの制御方法
US9312120B2 (en) Method for processing an oxygen containing semiconductor body
JP2016111044A (ja) シリコンウェーハの評価方法
Ozturk et al. Very shallow p+‐n junction formation by low‐energy BF+ 2 ion implantation into crystalline and germanium preamorphized silicon
EP3808879B1 (en) Method for controlling defect density in silicon single crystal substrate
CN111033709B (zh) 复合寿命的控制方法
US20240153829A1 (en) Method for manufacturing semiconductor device
WO2019208013A1 (ja) シリコン単結晶基板の選別方法及びシリコン単結晶基板
WO2019102759A1 (ja) シリコン単結晶基板の選別方法及びシリコン単結晶基板
JP5737202B2 (ja) 半導体素子、及びその形成方法
RU2176422C2 (ru) Способ геттерирующей обработки эпитаксиальных слоев полупроводниковых структур
Antonova et al. Thermal donor and oxygen precipitate formation in silicon during 450° C treatments under atmospheric and enhanced pressure
JP2020092169A (ja) シリコン単結晶基板中の窒素濃度評価方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220823

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230718

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230731

R150 Certificate of patent or registration of utility model

Ref document number: 7334849

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150