JP7312073B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

Info

Publication number
JP7312073B2
JP7312073B2 JP2019175001A JP2019175001A JP7312073B2 JP 7312073 B2 JP7312073 B2 JP 7312073B2 JP 2019175001 A JP2019175001 A JP 2019175001A JP 2019175001 A JP2019175001 A JP 2019175001A JP 7312073 B2 JP7312073 B2 JP 7312073B2
Authority
JP
Japan
Prior art keywords
voltage
down power
power supply
circuit
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019175001A
Other languages
English (en)
Japanese (ja)
Other versions
JP2021052122A5 (https=
JP2021052122A (ja
Inventor
悠 川越
洋一郎 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Astemo Ltd
Original Assignee
Hitachi Astemo Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Astemo Ltd filed Critical Hitachi Astemo Ltd
Priority to JP2019175001A priority Critical patent/JP7312073B2/ja
Publication of JP2021052122A publication Critical patent/JP2021052122A/ja
Publication of JP2021052122A5 publication Critical patent/JP2021052122A5/ja
Application granted granted Critical
Publication of JP7312073B2 publication Critical patent/JP7312073B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2019175001A 2019-09-26 2019-09-26 半導体集積回路装置 Active JP7312073B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019175001A JP7312073B2 (ja) 2019-09-26 2019-09-26 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019175001A JP7312073B2 (ja) 2019-09-26 2019-09-26 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2021052122A JP2021052122A (ja) 2021-04-01
JP2021052122A5 JP2021052122A5 (https=) 2022-02-22
JP7312073B2 true JP7312073B2 (ja) 2023-07-20

Family

ID=75158066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019175001A Active JP7312073B2 (ja) 2019-09-26 2019-09-26 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JP7312073B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023240503A1 (zh) * 2022-06-15 2023-12-21 北京小米移动软件有限公司 显示驱动模块、显示设备、异常处理方法、装置及介质
CN120283168A (zh) 2022-12-06 2025-07-08 爱德万测试株式会社 引脚电子装置、测试装置及方法
CN120265997A (zh) * 2022-12-06 2025-07-04 爱德万测试株式会社 引脚电子装置、测试装置及方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035193A (ja) 1999-07-16 2001-02-09 Mitsubishi Electric Corp 半導体記憶装置
JP2002074944A (ja) 1999-12-03 2002-03-15 Nec Corp 半導体記憶装置及びそのテスト方法
JP2005024502A (ja) 2003-07-03 2005-01-27 Nec Micro Systems Ltd 電源電圧検出回路及び半導体集積回路装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2945508B2 (ja) * 1991-06-20 1999-09-06 三菱電機株式会社 半導体装置
JP4146930B2 (ja) * 1998-04-28 2008-09-10 株式会社 沖マイクロデザイン 半導体集積回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035193A (ja) 1999-07-16 2001-02-09 Mitsubishi Electric Corp 半導体記憶装置
JP2002074944A (ja) 1999-12-03 2002-03-15 Nec Corp 半導体記憶装置及びそのテスト方法
JP2005024502A (ja) 2003-07-03 2005-01-27 Nec Micro Systems Ltd 電源電圧検出回路及び半導体集積回路装置

Also Published As

Publication number Publication date
JP2021052122A (ja) 2021-04-01

Similar Documents

Publication Publication Date Title
US11686759B2 (en) Functional tester for printed circuit boards, and associated systems and methods
US20080133165A1 (en) Test apparatus and device interface
JP7312073B2 (ja) 半導体集積回路装置
CN104583787B (zh) 用于诊断电路装置的设备
JP2022515286A (ja) 集積回路ｉ／ｏの完全性および劣化監視
US7317324B2 (en) Semiconductor integrated circuit testing device and method
US20110043233A1 (en) Wafer level contactor
TWI660183B (zh) Component inspection method, probe card, interposer and inspection device
JP5183447B2 (ja) 試験装置および診断方法
US10048306B1 (en) Methods and apparatus for automated integrated circuit package testing
US7427870B2 (en) Test system for testing integrated circuits and a method for configuring a test system
WO2020212262A1 (en) Reconfigurable system-on-chip
US9958507B2 (en) Channel verification of multiple channels on one chip
US11156672B2 (en) Semiconductor device
US20050030056A1 (en) Apparatus for measuring VS parameters in a wafer burn-in system
US11762034B2 (en) Abnormal power supply voltage detection device and method for detecting abnormal power supply voltage
TW202346880A (zh) 汽車設備的缺陷偵測系統
WO2009024172A1 (en) Chip tester, chip test system, chip test setup, method for identifying an open-line failure and computer program
JP3483130B2 (ja) 集積回路の検査方法
US20070186131A1 (en) Low cost imbedded load board diagnostic test fixture
KR20060089948A (ko) 아날로그 반도체 장치를 테스트하는 디지털 테스트 장치
KR20220124566A (ko) 멀티플렉서를 이용한 다수의 기기 고장진단 장치 및 방법
JP4727641B2 (ja) テスター装置
WO2025186884A1 (ja) 診断回路、診断方法
KR100798123B1 (ko) 다수의 클램프 저항 소자를 구비하는 클램프 회로

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220214

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220214

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20230118

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230228

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230323

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230704

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230707

R150 Certificate of patent or registration of utility model

Ref document number: 7312073

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150