JP7294594B2 - 集積型マルチデバイスチップおよびパッケージ - Google Patents
集積型マルチデバイスチップおよびパッケージ Download PDFInfo
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- JP7294594B2 JP7294594B2 JP2021564226A JP2021564226A JP7294594B2 JP 7294594 B2 JP7294594 B2 JP 7294594B2 JP 2021564226 A JP2021564226 A JP 2021564226A JP 2021564226 A JP2021564226 A JP 2021564226A JP 7294594 B2 JP7294594 B2 JP 7294594B2
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- 239000004065 semiconductor Substances 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 31
- 230000001681 protective effect Effects 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 230000004075 alteration Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H01L23/495—Lead-frames or other flat leads
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- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thyristors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
Claims (21)
- 半導体基板と、
前記半導体基板内に形成された前記半導体基板の第1の主面から前記半導体基板の第2の主面まで延在するサイリスタ型デバイスであって、前記半導体基板内に形成され且つ前記サイリスタ型デバイスの一部を形成する第1のPNダイオードを含む、サイリスタ型デバイスと、
前記半導体基板内に形成された第2のPNダイオードであって、前記サイリスタ型デバイスが前記第1のPNダイオードと前記第2のPNダイオードとの間に電気的に直列で配置された、第2のPNダイオードと、
を備える、保護デバイス。 - 前記保護デバイスは、前記第2の主面に沿って配設されたリードフレームをさらに備え、前記リードフレームは前記保護デバイスの下面で露出されている、請求項1に記載の保護デバイス。
- 前記サイリスタ型デバイスは、前記第2の主面から延在するP型層を含み、
前記P型層は互いから電気的に分離された第1の複数のP型領域と、互いから電気的に分離された第2の複数のN型領域とに分割され、前記第1の複数のP型領域が第1の方向に沿って延伸し、
前記リードフレームの複数のリード線は、前記第1の複数のP型領域および前記第2の複数のN型領域と接触して、前記第1の方向に沿って延在する、請求項2に記載の保護デバイス。 - 前記保護デバイスは、平面の構成である、請求項1から3のいずれか一項に記載の保護デバイス。
- 前記第2のPNダイオードが前記第1の主面から前記第2の主面まで延在する、請求項1から4のいずれか一項に記載の保護デバイス。
- 前記第1の主面から前記第2の主面まで延在し、前記第2のPNダイオードと前記サイリスタ型デバイスとの間に配設された、電気的分離バリアを更に備える、請求項1から5のいずれか一項に記載の保護デバイス。
- 前記第1のPNダイオードが、前記第2の主面から延在する、請求項1から6のいずれか一項に記載の保護デバイス。
- 前記第1の主面上に配設され、前記サイリスタ型デバイスおよび前記第2のPNダイオードと接触して配設された、表面金属層を更に備える、請求項1から7のいずれか一項に記載の保護デバイス。
- 前記第2の主面が、
互いから電気的に分離された第1の複数のP型領域と、互いから電気的に分離された、前記第1の複数のP型領域と等しい数の第2の複数のN型領域と
を有する、請求項1から8のいずれか一項に記載の保護デバイス。 - 第1の主面および第2の主面を有する半導体基板であって、
前記第1の主面から前記第2の主面まで延在するサイリスタ型デバイスであって、前記第2の主面から延在し且つ前記サイリスタ型デバイスの一部を形成する第1のPNダイオードを含む、サイリスタ型デバイスと、
第2のPNダイオードであって、前記サイリスタ型デバイスが前記第1のPNダイオードと前記第2のPNダイオードとの間に電気的に直列で配置された、第2のPNダイオードと、を有する、半導体基板と、
前記第1の主面上に配設された表面金属層と、
前記第2の主面と接触して配設されたリードフレームと、
を備える、保護デバイスアセンブリ。 - 前記リードフレームが、
前記第2の主面と接触して配設された複数のリード線を有する、
請求項10に記載の保護デバイスアセンブリ。 - 前記第2の主面が、
互いから電気的に分離された第1の複数のP型領域と、互いから電気的に分離された、前記第1の複数のP型領域と等しい数の第2の複数のN型領域と、を有し、前記第1の複数のP型領域が第1の方向に沿って延伸し、
前記複数のリード線が、前記第1の複数のP型領域および前記第2の複数のN型領域と接触して、前記第1の方向に沿って延在する、
請求項11に記載の保護デバイスアセンブリ。 - 前記リードフレームが4つのリード線を有する、請求項10から12のいずれか一項に記載の保護デバイスアセンブリ。
- 前記第2のPNダイオードが前記第1の主面から前記第2の主面まで延在する、請求項10から13のいずれか一項に記載の保護デバイスアセンブリ。
- 前記半導体基板が更に、前記第1の主面から前記第2の主面まで延在し、前記第2のPNダイオードと前記サイリスタ型デバイスとの間に配設された、電気的分離バリアを有する、請求項10から14のいずれか一項に記載の保護デバイスアセンブリ。
- 前記半導体基板の周りで、前記複数のリード線のうち隣接するリード線の間に延在する、絶縁ハウジングを更に備える、請求項11または12に記載の保護デバイスアセンブリ。
- 第1の主面および第2の主面を有する半導体基板であって、
前記第1の主面から前記第2の主面まで延在するサイリスタ型デバイスであって、前記第2の主面から延在し且つ前記サイリスタ型デバイスの一部を形成する第1のPNダイオードを含む、サイリスタ型デバイスと、
第2のPNダイオードであって、前記サイリスタ型デバイスが前記第1のPNダイオードと前記第2のPNダイオードとの間に電気的に直列で配置された、第2のPNダイオードと、
前記第1の主面から前記第2の主面まで延在し、前記第2のPNダイオードと前記サイリスタ型デバイスとの間に配設された、電気的分離バリアと、を有する、半導体基板と、
前記第1の主面上に配設された表面金属層と、
前記第2の主面と接触して配設されたリードフレームであって、互いに電気的に並列で配置された複数のリード線を有する、リードフレームと、
を備える、保護デバイス。 - 前記第2の主面が、
互いから電気的に分離された第1の複数のP型領域と、互いから電気的に分離された、前記第1の複数のP型領域と等しい数の第2の複数のN型領域と、を有し、前記第1の複数のP型領域が第1の方向に沿って延伸し、
前記複数のリード線が、前記第1の複数のP型領域および前記第2の複数のN型領域と接触して、前記第1の方向に沿って延在する、
請求項17に記載の保護デバイス。 - 前記リードフレームが4つのリード線を有する、請求項17または18に記載の保護デバイス。
- 前記第2のPNダイオードが前記第1の主面から前記第2の主面まで延在する、請求項17から19のいずれか一項に記載の保護デバイス。
- 前記半導体基板の周りで、前記複数のリード線のうち隣接するリード線の間に延在する、絶縁ハウジングを更に備える、請求項17から20のいずれか一項に記載の保護デバイス。
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PCT/CN2019/089797 WO2020243875A1 (en) | 2019-06-03 | 2019-06-03 | Integrated mult-device chip and package |
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EP (1) | EP3977518A4 (ja) |
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US20160336744A1 (en) | 2015-05-15 | 2016-11-17 | Analog Devices, Inc. | Electrostatic discharge protection circuits for radio frequency communication systems |
CN108550573A (zh) | 2018-05-29 | 2018-09-18 | 矽力杰半导体技术(杭州)有限公司 | 静电保护器件及其制造方法 |
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FR2729008B1 (fr) * | 1994-12-30 | 1997-03-21 | Sgs Thomson Microelectronics | Circuit integre de puissance |
JPH1098202A (ja) * | 1996-09-19 | 1998-04-14 | Origin Electric Co Ltd | 半導体サージ防護素子 |
FR2783353A1 (fr) * | 1998-09-16 | 2000-03-17 | St Microelectronics Sa | Mur d'isolement entre composants de puissance |
TW419808B (en) * | 1999-07-31 | 2001-01-21 | Winbond Electronics Corp | Electrostatic discharge device capable of avoiding latch up effect |
FR2818805B1 (fr) * | 2000-12-21 | 2003-04-04 | St Microelectronics Sa | Commutateur statique bidirectionnel sensible |
CN1321457C (zh) * | 2001-11-07 | 2007-06-13 | 新电元件工业株式会社 | 浪涌保护半导体装置 |
US9337178B2 (en) * | 2012-12-09 | 2016-05-10 | Semiconductor Components Industries, Llc | Method of forming an ESD device and structure therefor |
EP3051592A1 (en) * | 2015-01-27 | 2016-08-03 | Nxp B.V. | Semiconductor device |
FR3039014B1 (fr) * | 2015-07-13 | 2019-06-14 | Stmicroelectronics (Tours) Sas | Protection de ligne telephonique contre les surtensions |
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US20160336744A1 (en) | 2015-05-15 | 2016-11-17 | Analog Devices, Inc. | Electrostatic discharge protection circuits for radio frequency communication systems |
CN108550573A (zh) | 2018-05-29 | 2018-09-18 | 矽力杰半导体技术(杭州)有限公司 | 静电保护器件及其制造方法 |
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EP3977518A1 (en) | 2022-04-06 |
US20220320072A1 (en) | 2022-10-06 |
EP3977518A4 (en) | 2023-01-11 |
KR20220004187A (ko) | 2022-01-11 |
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JP2022535500A (ja) | 2022-08-09 |
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