JP7275112B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP7275112B2
JP7275112B2 JP2020514791A JP2020514791A JP7275112B2 JP 7275112 B2 JP7275112 B2 JP 7275112B2 JP 2020514791 A JP2020514791 A JP 2020514791A JP 2020514791 A JP2020514791 A JP 2020514791A JP 7275112 B2 JP7275112 B2 JP 7275112B2
Authority
JP
Japan
Prior art keywords
region
layer
insulating layer
semiconductor layer
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020514791A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2019202430A1 (ja
JPWO2019202430A5 (https=
Inventor
舜平 山崎
健一 岡崎
正美 神長
行徳 島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of JPWO2019202430A1 publication Critical patent/JPWO2019202430A1/ja
Publication of JPWO2019202430A5 publication Critical patent/JPWO2019202430A5/ja
Application granted granted Critical
Publication of JP7275112B2 publication Critical patent/JP7275112B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional [2D] radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional [2D] radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks

Landscapes

  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2020514791A 2018-04-20 2019-04-08 半導体装置 Active JP7275112B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2018081381 2018-04-20
JP2018081381 2018-04-20
PCT/IB2019/052855 WO2019202430A1 (ja) 2018-04-20 2019-04-08 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2019202430A1 JPWO2019202430A1 (ja) 2021-05-13
JPWO2019202430A5 JPWO2019202430A5 (https=) 2022-03-31
JP7275112B2 true JP7275112B2 (ja) 2023-05-17

Family

ID=68240045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020514791A Active JP7275112B2 (ja) 2018-04-20 2019-04-08 半導体装置

Country Status (4)

Country Link
US (1) US11552111B2 (https=)
JP (1) JP7275112B2 (https=)
TW (1) TWI841560B (https=)
WO (1) WO2019202430A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022090361A (ja) * 2020-12-07 2022-06-17 株式会社ジャパンディスプレイ 半導体装置及びその製造方法
US12363952B2 (en) * 2021-12-09 2025-07-15 AUP Corporation Active device substrate and manufacturing method of active device substrate

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003257864A (ja) 2001-12-28 2003-09-12 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の生産システム
JP2015035590A (ja) 2013-07-12 2015-02-19 株式会社半導体エネルギー研究所 半導体装置
WO2015075985A1 (ja) 2013-11-25 2015-05-28 シャープ株式会社 半導体装置およびその書き込み方法
JP2015144266A (ja) 2013-12-27 2015-08-06 株式会社半導体エネルギー研究所 半導体装置
JP2015181162A (ja) 2014-03-06 2015-10-15 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2017112374A (ja) 2015-12-16 2017-06-22 株式会社半導体エネルギー研究所 トランジスタ、半導体装置、および電子機器
JP2017224813A (ja) 2016-06-09 2017-12-21 株式会社半導体エネルギー研究所 トランジスタ
JP2018006734A (ja) 2016-03-11 2018-01-11 株式会社半導体エネルギー研究所 半導体装置、当該半導体装置の作製方法、及び当該半導体装置を有する表示装置
JP2018063743A (ja) 2015-12-29 2018-04-19 株式会社半導体エネルギー研究所 半導体装置、電子機器、半導体ウエハ

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6933527B2 (en) 2001-12-28 2005-08-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device production system
US20080254613A1 (en) 2007-04-10 2008-10-16 Applied Materials, Inc. Methods for forming metal interconnect structure for thin film transistor applications
WO2011043194A1 (en) * 2009-10-09 2011-04-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN102668098B (zh) 2009-12-28 2015-07-22 株式会社半导体能源研究所 制造半导体装置的方法
JP5708910B2 (ja) 2010-03-30 2015-04-30 ソニー株式会社 薄膜トランジスタおよびその製造方法、並びに表示装置
US8916867B2 (en) 2011-01-20 2014-12-23 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor element and semiconductor device
CN107591316B (zh) 2012-05-31 2021-06-08 株式会社半导体能源研究所 半导体装置
JP6400336B2 (ja) 2013-06-05 2018-10-03 株式会社半導体エネルギー研究所 半導体装置
US20150008428A1 (en) 2013-07-08 2015-01-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
TWI666770B (zh) * 2013-12-19 2019-07-21 日商半導體能源研究所股份有限公司 半導體裝置
US9366953B2 (en) 2014-01-17 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Lithography mask
TWI702187B (zh) 2014-02-21 2020-08-21 日商半導體能源研究所股份有限公司 半導體膜、電晶體、半導體裝置、顯示裝置以及電子裝置
CN111048509B (zh) 2014-03-28 2023-12-01 株式会社半导体能源研究所 半导体装置
KR102380829B1 (ko) 2014-04-23 2022-03-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 촬상 장치
KR102865410B1 (ko) 2015-02-06 2025-09-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
JPWO2017085591A1 (ja) 2015-11-20 2018-09-06 株式会社半導体エネルギー研究所 半導体装置、該半導体装置を有する表示装置、及び該半導体装置を有する電子機器
KR102403389B1 (ko) 2016-09-12 2022-06-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 전자 기기

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003257864A (ja) 2001-12-28 2003-09-12 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の生産システム
JP2015035590A (ja) 2013-07-12 2015-02-19 株式会社半導体エネルギー研究所 半導体装置
WO2015075985A1 (ja) 2013-11-25 2015-05-28 シャープ株式会社 半導体装置およびその書き込み方法
JP2015144266A (ja) 2013-12-27 2015-08-06 株式会社半導体エネルギー研究所 半導体装置
JP2015181162A (ja) 2014-03-06 2015-10-15 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2017112374A (ja) 2015-12-16 2017-06-22 株式会社半導体エネルギー研究所 トランジスタ、半導体装置、および電子機器
JP2018063743A (ja) 2015-12-29 2018-04-19 株式会社半導体エネルギー研究所 半導体装置、電子機器、半導体ウエハ
JP2018006734A (ja) 2016-03-11 2018-01-11 株式会社半導体エネルギー研究所 半導体装置、当該半導体装置の作製方法、及び当該半導体装置を有する表示装置
JP2017224813A (ja) 2016-06-09 2017-12-21 株式会社半導体エネルギー研究所 トランジスタ

Also Published As

Publication number Publication date
US11552111B2 (en) 2023-01-10
JPWO2019202430A1 (ja) 2021-05-13
US20210020665A1 (en) 2021-01-21
TW202005099A (zh) 2020-01-16
TWI841560B (zh) 2024-05-11
WO2019202430A1 (ja) 2019-10-24

Similar Documents

Publication Publication Date Title
JP7682962B2 (ja) 半導体装置の作製方法
JP7612791B2 (ja) 半導体装置の作製方法
JP7194122B2 (ja) 半導体装置
JP7475282B2 (ja) 半導体装置
JP7300442B2 (ja) 半導体装置の作製方法
JP7183184B2 (ja) 半導体装置
JP7599859B2 (ja) 半導体装置
JP7397789B2 (ja) 半導体装置の作製方法
JP2024086738A (ja) 半導体装置
JP2023106446A (ja) 半導体装置
JP2026065018A (ja) 半導体装置の作製方法
JP7686827B2 (ja) 半導体装置
JP2023060293A (ja) 半導体装置
JP7275112B2 (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220323

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220323

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20221025

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221222

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230131

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230316

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230411

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230502

R150 Certificate of patent or registration of utility model

Ref document number: 7275112

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150