JP7259046B2 - ディスプレイ、電子デバイス、及びディスプレイ製造方法 - Google Patents
ディスプレイ、電子デバイス、及びディスプレイ製造方法 Download PDFInfo
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- JP7259046B2 JP7259046B2 JP2021537755A JP2021537755A JP7259046B2 JP 7259046 B2 JP7259046 B2 JP 7259046B2 JP 2021537755 A JP2021537755 A JP 2021537755A JP 2021537755 A JP2021537755 A JP 2021537755A JP 7259046 B2 JP7259046 B2 JP 7259046B2
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Description
Claims (14)
- ディスプレイであって、
前記ディスプレイの構成要素を支えるように構成された基板と、
複数のドライバ回路ユニットを含むドライバ回路バックプレーンであって、前記ドライバ回路バックプレーンは前記基板の上に配置されている、ドライバ回路バックプレーンと、
複数のピクセルを含む第1ピクセル層であって、前記第1ピクセル層の各ピクセルは複数のサブピクセルを含み、前記第1ピクセル層の各サブピクセルは1つの有機発光ダイオードOLED構成要素を含み、前記第1ピクセル層は前記ドライバ回路バックプレーンの上に配置され、前記第1ピクセル層の各サブピクセルの前記OLED構成要素は、前記ドライバ回路バックプレーンの少なくとも1つのドライバ回路ユニットに接続されている、第1ピクセル層と、
第1電極層と、第2電極層と、前記第1電極層及び前記第2電極層の間に配置された複数のピクセルとを含む第2ピクセル層であって、前記第2ピクセル層の各ピクセルは複数のサブピクセルを含み、前記第2ピクセル層の各サブピクセルは1つのマイクロ発光ダイオード・マイクロLED構成要素を含み、前記第2ピクセル層は、前記基板の上に配置され且つ前記第1ピクセル層を包囲し、前記第2ピクセル層の面積は前記第1ピクセル層の面積より小さい、第2ピクセル層と
を含み、各ドライバ回路ユニットは複数のトランジスタを含み、前記ドライバ回路バックプレーンの全てのトランジスタのソース電極及びドレイン電極は第3電極層を形成し、前記ドライバ回路バックプレーンの前記全てのトランジスタのゲート電極は第4電極層を形成し、前記第1電極層は前記第3電極層又は前記第4電極層と同じ層に位置しているディスプレイ。 - 前記マイクロLED構成要素は縦型マイクロLED構成要素であり、前記縦型マイクロLED構成要素はトップ電極とボトム電極とを含み、前記第2電極層は前記第1電極層より上にあり、前記縦型マイクロLED構成要素の前記ボトム電極は前記第1電極層に接続され、前記縦型マイクロLED構成要素の前記トップ電極は前記第2電極層に接続されている、請求項1に記載のディスプレイ。
- 前記第2ピクセル層はパッシベーション層を更に含み、前記パッシベーション層は、前記第1電極層と前記第2電極層との間に配置され、前記縦型マイクロLED構成要素の側面を覆っている、請求項2に記載のディスプレイ。
- 前記パッシベーション層は、前記縦型マイクロLED構成要素のトップ電極の上にある開口とともに提供され、前記トップ電極は前記開口を介して前記第2電極層に接続されている、請求項3に記載のディスプレイ。
- 前記第1電極層は電源の正電位に接続され、前記第2電極層は前記電源の負電位に接続されている、請求項1-4のうちの何れか1項に記載のディスプレイ。
- 前記第2ピクセル層のサブピクセル配置方式は、ペンタイル配置又はベイヤー配置である、請求項1-4のうちの何れか1項に記載のディスプレイ。
- 前記ディスプレイは薄膜パッケージ層を更に含み、前記薄膜パッケージ層は前記第2電極層の上に配置され且つ前記第2電極層を覆っているか;又は
前記ディスプレイは光遮蔽層を更に含み、前記光遮蔽層は前記ドライバ回路バックプレーンの上に配置され且つ前記第1電極層を覆っているか;又は
前記縦型マイクロLED構成要素はnドープ層及びpドープ層を含み、前記nドープ層は前記縦型マイクロLED構成要素の前記トップ電極に接続され、前記pドープ層は前記縦型マイクロLED構成要素の前記ボトム電極に接続されている;
請求項3に記載のディスプレイ。 - ディスプレイであって、
前記ディスプレイの構成要素を支えるように構成された基板と、
複数のドライバ回路ユニットを含むドライバ回路バックプレーンであって、前記ドライバ回路バックプレーンは前記基板の上に配置されている、ドライバ回路バックプレーンと、
複数のピクセルを含む第1ピクセル層であって、前記第1ピクセル層の各ピクセルは複数のサブピクセルを含み、前記第1ピクセル層の各サブピクセルは1つの有機発光ダイオードOLED構成要素を含み、前記第1ピクセル層は前記ドライバ回路バックプレーンの上に配置され、前記第1ピクセル層の各サブピクセルの前記OLED構成要素は、前記ドライバ回路バックプレーンの少なくとも1つのドライバ回路ユニットに接続されている、第1ピクセル層と、
第1電極層と、第2電極層と、前記第1電極層及び前記第2電極層の間に配置された複数のピクセルとを含む第2ピクセル層であって、前記第2ピクセル層の各ピクセルは複数のサブピクセルを含み、前記第2ピクセル層の各サブピクセルは1つのマイクロ発光ダイオード・マイクロLED構成要素を含み、前記第2ピクセル層は、前記ドライバ回路バックプレーンの上に配置され且つ前記第1ピクセル層を包囲し、前記第2ピクセル層の面積は前記第1ピクセル層の面積より小さく、前記第2ピクセル層の各サブピクセルの前記マイクロLED構成要素は、前記ドライバ回路バックプレーンの少なくとも1つのドライバ回路ユニットに接続されており、各ドライバ回路ユニットは複数のトランジスタを含み、前記ドライバ回路バックプレーンの全てのトランジスタのソース電極及びドレイン電極は第3電極層を形成し、前記ドライバ回路バックプレーンの前記全てのトランジスタのゲート電極は第4電極層を形成し、前記第1電極層は前記第3電極層又は前記第4電極層と同じ層に位置している、第2ピクセル層と
を含むディスプレイ。 - 前記マイクロLED構成要素はフリップ・タイプのマイクロLED構成要素であり、前記フリップ・タイプのマイクロLED構成要素はP電極及びN電極を含み、前記P電極及び前記N電極は前記フリップ・タイプのマイクロLED構成要素と同じ側に位置している、請求項8に記載のディスプレイ。
- 前記フリップ・タイプのマイクロLED構成要素の前記P電極又は前記N電極は、少なくとも1つのドライバ回路ユニットに接続されている、請求項9に記載のディスプレイ。
- 前記ディスプレイは薄膜パッケージ層を更に含み、前記薄膜パッケージ層は前記第1ピクセル層と前記第2ピクセル層とを覆っている、請求項10に記載のディスプレイ。
- 前記ドライバ回路ユニットは、2T1Cドライバ回路ユニット又は5T1Cドライバ回路ユニットである、請求項11に記載のディスプレイ。
- 前記フリップ・タイプのマイクロLED構成要素のドライバ回路ユニットは、電源の負電位に接続され、前記フリップ・タイプのマイクロLED構成要素の前記P電極は、前記電源の正電位に接続されている、請求項12に記載のディスプレイ。
- 前記フリップ・タイプのマイクロLED構成要素はボンディングにより前記ドライバ回路ユニットに接続されているか;又は
前記薄膜パッケージ層は第1無機パッケージ層、第2有機パッケージ層、及び第3無機パッケージ層を含んでいるか;又は
前記ディスプレイはパッシベーション層を更に含み、前記パッシベーション層は、前記ドライバ回路バックプレーンより上に、且つ第1ピクセル層及び前記第2ピクセル層より下に配置されているか;又は
前記ディスプレイはパッシベーション層を更に含み、平坦化層が、前記ドライバ回路バックプレーンより上に、且つ第1ピクセル層及び前記第2ピクセル層より下に配置されているか;又は
前記ディスプレイは、前記第1電極層を覆う光遮蔽層を更に含み、前記光遮蔽層は前記ドライバ回路バックプレーンより上にある、
請求項13に記載のディスプレイ。
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