JP7248660B2 - 裏面シリサイド化によるバルク層転写処理 - Google Patents

裏面シリサイド化によるバルク層転写処理 Download PDF

Info

Publication number
JP7248660B2
JP7248660B2 JP2020517136A JP2020517136A JP7248660B2 JP 7248660 B2 JP7248660 B2 JP 7248660B2 JP 2020517136 A JP2020517136 A JP 2020517136A JP 2020517136 A JP2020517136 A JP 2020517136A JP 7248660 B2 JP7248660 B2 JP 7248660B2
Authority
JP
Japan
Prior art keywords
bulk semiconductor
dielectric layer
layer
semiconductor wafer
trench isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020517136A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020535647A (ja
JP2020535647A5 (https=
Inventor
シナン・ゴクテペリ
ジョージ・ピート・イムサーン
スティーヴン・アラン・ファネリ
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2020535647A publication Critical patent/JP2020535647A/ja
Publication of JP2020535647A5 publication Critical patent/JP2020535647A5/ja
Application granted granted Critical
Publication of JP7248660B2 publication Critical patent/JP7248660B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/481—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes on the rear surfaces of the wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2020517136A 2017-09-29 2018-08-27 裏面シリサイド化によるバルク層転写処理 Active JP7248660B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762565495P 2017-09-29 2017-09-29
US62/565,495 2017-09-29
US15/975,434 2018-05-09
US15/975,434 US10559520B2 (en) 2017-09-29 2018-05-09 Bulk layer transfer processing with backside silicidation
PCT/US2018/048125 WO2019067129A1 (en) 2017-09-29 2018-08-27 MASSIVE LAYER TRANSFER TREATMENT WITH SILICIURATION ON THE REAR PANEL

Publications (3)

Publication Number Publication Date
JP2020535647A JP2020535647A (ja) 2020-12-03
JP2020535647A5 JP2020535647A5 (https=) 2021-09-24
JP7248660B2 true JP7248660B2 (ja) 2023-03-29

Family

ID=65896847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020517136A Active JP7248660B2 (ja) 2017-09-29 2018-08-27 裏面シリサイド化によるバルク層転写処理

Country Status (6)

Country Link
US (1) US10559520B2 (https=)
EP (1) EP3688795B1 (https=)
JP (1) JP7248660B2 (https=)
KR (1) KR102675753B1 (https=)
CN (1) CN111133565B (https=)
WO (1) WO2019067129A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199461B2 (en) * 2015-10-27 2019-02-05 Texas Instruments Incorporated Isolation of circuit elements using front side deep trench etch
US10615252B2 (en) * 2018-08-06 2020-04-07 Nxp Usa, Inc. Device isolation
CN115036325A (zh) * 2019-10-14 2022-09-09 长江存储科技有限责任公司 用于三维nand的位线驱动器的隔离的结构和方法
CN111052380B (zh) * 2019-11-28 2021-01-29 长江存储科技有限责任公司 局部字线驱动器件、存储器件及其制造方法
US11568052B2 (en) 2020-05-31 2023-01-31 Microsoft Technology Licensing, Llc Undetectable sandbox for malware
CN111883476B (zh) * 2020-09-18 2023-04-14 上海华虹宏力半导体制造有限公司 深沟槽隔离结构的形成方法及半导体器件的形成方法
US11721883B2 (en) * 2021-02-25 2023-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with antenna and method of forming the same
US12136627B2 (en) * 2021-06-24 2024-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure for high voltage device on a SOI substrate
CN114999998A (zh) * 2022-05-23 2022-09-02 长江存储科技有限责任公司 存储器件、制造存储器件的方法和包括其的存储器系统
US12575111B2 (en) * 2022-06-30 2026-03-10 Intel Corporation Back-end-of-line 2D memory cell
CN120565491B (zh) * 2025-07-31 2025-10-10 杭州富芯半导体有限公司 一种半导体结构、制备方法及半导体器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278646A (ja) 2005-03-29 2006-10-12 Sanyo Electric Co Ltd 半導体装置の製造方法
US20120091593A1 (en) 2010-10-14 2012-04-19 International Business Machines Corporation Structure and method for simultaneously forming a through silicon via and a deep trench structure
JP2014207252A (ja) 2011-08-17 2014-10-30 株式会社村田製作所 半導体装置およびその製造方法ならびに携帯電話機
JP2015050339A (ja) 2013-09-02 2015-03-16 ソニー株式会社 半導体装置およびその製造方法
JP2015527733A (ja) 2012-07-09 2015-09-17 クアルコム，インコーポレイテッド 集積回路のウェハ裏面の層からの基板貫通ビアの統合

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3681862D1 (de) * 1985-08-23 1991-11-14 Siemens Ag Verfahren zur herstellung einer hochsperrenden diodenanordnung auf der basis von a-si:h fuer bildsensorzeilen.
JP3587537B2 (ja) * 1992-12-09 2004-11-10 株式会社半導体エネルギー研究所 半導体装置
JP4289146B2 (ja) * 2003-03-27 2009-07-01 セイコーエプソン株式会社 三次元実装型半導体装置の製造方法
JP2006108520A (ja) * 2004-10-08 2006-04-20 Sharp Corp 半導体装置及び半導体装置の製造方法
JP4869664B2 (ja) 2005-08-26 2012-02-08 本田技研工業株式会社 半導体装置の製造方法
US7285477B1 (en) 2006-05-16 2007-10-23 International Business Machines Corporation Dual wired integrated circuit chips
JP2007335642A (ja) * 2006-06-15 2007-12-27 Fujifilm Corp パッケージ基板
TWI382515B (zh) * 2008-10-20 2013-01-11 鈺程科技股份有限公司 無線收發模組
JP4945545B2 (ja) * 2008-11-10 2012-06-06 株式会社日立製作所 半導体装置の製造方法
US8299583B2 (en) 2009-03-05 2012-10-30 International Business Machines Corporation Two-sided semiconductor structure
US8455875B2 (en) * 2010-05-10 2013-06-04 International Business Machines Corporation Embedded DRAM for extremely thin semiconductor-on-insulator
US8779559B2 (en) * 2012-02-27 2014-07-15 Qualcomm Incorporated Structure and method for strain-relieved TSV
US20130249011A1 (en) * 2012-03-22 2013-09-26 Texas Instruments Incorporated Integrated circuit (ic) having tsvs and stress compensating layer
US9093462B2 (en) * 2013-05-06 2015-07-28 Qualcomm Incorporated Electrostatic discharge diode
CN104241279B (zh) * 2013-06-18 2017-09-01 中芯国际集成电路制造(上海)有限公司 一种集成电路及其制造方法
CN104241267B (zh) * 2013-06-18 2017-08-01 中芯国际集成电路制造(上海)有限公司 一种集成电路及其制造方法
US9252077B2 (en) * 2013-09-25 2016-02-02 Intel Corporation Package vias for radio frequency antenna connections
EP2887387A1 (en) * 2013-12-20 2015-06-24 Nxp B.V. Semiconductor device and associated method
EP3373329B1 (en) * 2014-02-28 2023-04-05 LFoundry S.r.l. Integrated circuit comprising a laterally diffused mos field effect transistor
US9368479B2 (en) * 2014-03-07 2016-06-14 Invensas Corporation Thermal vias disposed in a substrate proximate to a well thereof
US9324632B2 (en) * 2014-05-28 2016-04-26 Globalfoundries Inc. Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
JP2015228473A (ja) * 2014-06-03 2015-12-17 パナソニックＩｐマネジメント株式会社 半導体装置およびその製造方法
KR102235613B1 (ko) * 2014-11-20 2021-04-02 삼성전자주식회사 Mos 커패시터를 구비하는 반도체 소자
US9673084B2 (en) * 2014-12-04 2017-06-06 Globalfoundries Singapore Pte. Ltd. Isolation scheme for high voltage device
US9570494B1 (en) * 2015-09-29 2017-02-14 Semiconductor Components Industries, Llc Method for forming a semiconductor image sensor device
US9755029B1 (en) 2016-06-22 2017-09-05 Qualcomm Incorporated Switch device performance improvement through multisided biased shielding
US20180138081A1 (en) * 2016-11-15 2018-05-17 Vanguard International Semiconductor Corporation Semiconductor structures and method for fabricating the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278646A (ja) 2005-03-29 2006-10-12 Sanyo Electric Co Ltd 半導体装置の製造方法
US20120091593A1 (en) 2010-10-14 2012-04-19 International Business Machines Corporation Structure and method for simultaneously forming a through silicon via and a deep trench structure
JP2014207252A (ja) 2011-08-17 2014-10-30 株式会社村田製作所 半導体装置およびその製造方法ならびに携帯電話機
JP2015527733A (ja) 2012-07-09 2015-09-17 クアルコム，インコーポレイテッド 集積回路のウェハ裏面の層からの基板貫通ビアの統合
JP2015050339A (ja) 2013-09-02 2015-03-16 ソニー株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
CA3073721A1 (en) 2019-04-04
JP2020535647A (ja) 2020-12-03
KR102675753B1 (ko) 2024-06-14
CN111133565B (zh) 2023-10-13
KR20200057714A (ko) 2020-05-26
BR112020005804A2 (pt) 2020-09-24
WO2019067129A1 (en) 2019-04-04
EP3688795A1 (en) 2020-08-05
US10559520B2 (en) 2020-02-11
EP3688795B1 (en) 2025-06-18
CN111133565A (zh) 2020-05-08
US20190103339A1 (en) 2019-04-04
EP3688795C0 (en) 2025-06-18

Similar Documents

Publication Publication Date Title
JP7248660B2 (ja) 裏面シリサイド化によるバルク層転写処理
CN110088891B (zh) 利用双面处理的逻辑电路块布局
US9812580B1 (en) Deep trench active device with backside body contact
US10431558B2 (en) Method and apparatus for back-biased switch transistors
CN112236865A (zh) 利用背侧硅化的基于体层转印的开关
US9917062B1 (en) Self-aligned transistors for dual-side processing
US20180068886A1 (en) Porous semiconductor layer transfer for an integrated circuit structure
CN111164760A (zh) 用于改善谐波性能的晶体管布局
US10707866B1 (en) Capacitance balance in dual sided contact switch
US10043752B2 (en) Substrate contact using dual sided silicidation
US10483392B2 (en) Capacitive tuning using backside gate
CA3073721C (en) Bulk layer transfer processing with backside silicidation
CN121569618A (zh) 松饼形状的射频（rf）开关
HK40009868B (en) Logic circuit block layouts with dual-sided processing
HK40009868A (en) Logic circuit block layouts with dual-sided processing
BR112020005804B1 (pt) Processamento de transferência de camada em volume com silicetação de fundo

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210810

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210810

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220831

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220905

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221124

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230220

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230316

R150 Certificate of patent or registration of utility model

Ref document number: 7248660

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250