JP7239051B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP7239051B2 JP7239051B2 JP2022504390A JP2022504390A JP7239051B2 JP 7239051 B2 JP7239051 B2 JP 7239051B2 JP 2022504390 A JP2022504390 A JP 2022504390A JP 2022504390 A JP2022504390 A JP 2022504390A JP 7239051 B2 JP7239051 B2 JP 7239051B2
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- 239000004065 semiconductor Substances 0.000 title claims description 161
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000463 material Substances 0.000 claims description 76
- 229910052751 metal Inorganic materials 0.000 claims description 72
- 239000002184 metal Substances 0.000 claims description 72
- 239000000470 constituent Substances 0.000 claims description 43
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 36
- 229910052709 silver Inorganic materials 0.000 claims description 36
- 239000004332 silver Substances 0.000 claims description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052802 copper Inorganic materials 0.000 claims description 22
- 239000010949 copper Substances 0.000 claims description 22
- 239000002245 particle Substances 0.000 claims description 14
- 239000002904 solvent Substances 0.000 claims description 14
- 238000005245 sintering Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000005304 joining Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims 1
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 12
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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Description
しかしながら、半導体チップがMOSFET素子やIGBT素子等の半導体素子が形成されたものである場合、半導体チップは、第2支持部材側である一面側に一面電極が形成されると共にゲート配線等が形成される。このため、半導体チップの一面側は、一面電極およびゲート配線等によって構成される凸部が形成された状態となっている。なお、半導体チップのうちの第1支持部材側である他面側は、全体に他面電極が形成され、平坦な状態となっている。MOSFETは、Metal Oxide Semiconductor Field Effect Transistorの略であり、IGBTは、Insulated Gate Bipolar Transistorの略である。
第1実施形態について、図面を参照しつつ説明する。本実施形態の半導体装置は、図1に示されるように、第1支持部材10、第2支持部材20、および半導体チップ30を備えた構成とされている。また、半導体装置は、下層接合部材40および上層接合部材50等を備えた構成とされている。
本開示は、実施形態に準拠して記述されたが、本開示は当該実施形態や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。
また、上記第1実施形態において、中間金属層71、72は、銀または銅を主成分とする焼結層によって構成されていてもよい。この場合、上記図2Bの第1構成材料110を配置する際には、予め焼結反応させてフィルム状とした焼結層を中間金属層71とし、当該中間金属層71が第1シート111および第2シート112で挟まれた第1構成材料110が配置される。同様に、上記図2Dの第2構成材料120を配置する際には、予め焼結反応させてフィルム状とした焼結層を中間金属層72とし、当該中間金属層72が第1シート121および第2シート122で挟まれた第2構成材料120が配置される。
これによれば、中間金属層71、72を構成する焼結層が第1シート111、121および第2シート121、122よりも原子密度が高くなるようにした場合には、熱伝導性の向上を図ることができる。また、中間金属層71、72を構成する焼結層が第1シート111、121および第2シート121、122よりも原子密度が低くなるようにした場合には、中間金属層71、72を低弾性率な接合層とできる。このため、半導体チップ30への発生応力を低減でき、信頼性の向上を図ることができる。また、中間金属層71、72が低弾性率な接合層とされている場合には、中間金属層71、72の強度が小さくなる。このため、半導体装置に何らかの不具合が発生した際には、中間金属層71、72が破壊されることで半導体チップ30が破壊されることを抑制できる。
Claims (6)
- 対向する第1支持部材(10)と第2支持部材(20)との間に半導体チップ(30)が配置された半導体装置の製造方法であって、
一面(30a)および前記一面と反対側の他面(30b)を有し、前記一面側に凸部(31)が構成された前記半導体チップを用意することと、
前記半導体チップの他面が前記第1支持部材と対向するように、前記第1支持部材と前記半導体チップの他面とを加圧焼結層を含む下層接合部材(40)を介して接合することと、
前記半導体チップの一面が前記第2支持部材と対向するように、前記第2支持部材と前記半導体チップの一面とを加圧焼結層を含む上層接合部材(50)を介して接合することと、を行い、
前記上層接合部材を介して接合することでは、
前記半導体チップの一面上に、焼結材料を含む第1構成材料(110)が加圧焼結されることで構成され、前記凸部の間に入り込むと共に前記凸部と接触しており、前記半導体チップ側と反対側の面が平坦化された事前接合層(51)を配置することと、
前記事前接合層上に、焼結材料を含む第2構成材料(120)を介して前記第2支持部材を配置することと、
加熱しながら加圧して前記第2構成材料を加圧焼結することにより、前記事前接合層と共に前記上層接合部材を構成することと、を行う半導体装置の製造方法。 - 前記事前接合層を配置することでは、前記半導体チップの一面側に前記第1構成材料を配置することと、加熱しながら緩衝部材(200)を介して前記第1構成材料を加圧することにより、前記第1構成材料から前記事前接合層を構成することと、を行う請求項1に記載の半導体装置の製造方法。
- 前記下層接合部材を介して接合することでは、前記第1支持部材上に、焼結材料を含む下層接合材料(100)を介して前記半導体チップを配置することと、加熱しながら加圧することにより、前記下層接合材料から前記下層接合部材を構成することと、を行い、
前記下層接合材料から前記下層接合部材を構成することにおける加圧することは、前記第1構成材料から前記事前接合層を構成することにおける加圧することと同じ工程で行う請求項2に記載の半導体装置の製造方法。 - 前記第1構成材料は、銀粒子が溶媒に混入している銀ペースト、前記銀ペーストから溶媒が除去された銀シート、支持層となる中間金属層(71)が前記銀シートに挟まれたプリフォーム構造、銅粒子が溶媒に混入している銅ペースト、前記銅ペーストから溶媒が除去された銅シート、および支持層となる中間金属層(71)が前記銅シートに挟まれたプリフォーム構造のいずれかで構成され、
前記中間金属層は、銀、銅、およびアルミニウムのいずれかのバルク金属層、または銀もしくは銅を主成分とする焼結層のいずれかで構成されている請求項1ないし3のいずれか1つに記載の半導体装置の製造方法。 - 対向する第1支持部材(10)と第2支持部材(20)との間に半導体チップ(30)が配置された半導体装置であって、
前記第1支持部材と、
前記第2支持部材と、
一面(30a)および前記一面と反対側の他面(30b)を有し、前記一面側に凸部(31)が構成され、前記一面が前記第1支持部材と対向すると共に前記他面が前記第2支持部材と対向する状態で前記第1支持部材と前記第2支持部材との間に配置される前記半導体チップと、
前記第1支持部材と前記半導体チップとの間に配置され、加圧焼結層で構成される下層接合部材(40)と、
前記第2支持部材と前記半導体チップとの間に配置された上層接合部材(50)と、を備え、
前記上層接合部材は、支持層となる中間金属層(71、72)と、前記第1支持部材と前記第2支持部材との積層方向において前記中間金属層を挟むように配置され、加圧焼結層で構成される焼結層(61~63)とを有し、
前記半導体チップ側の焼結層は、前記半導体チップと前記中間金属層とを接合すると共に、前記凸部の間に入り込みつつ前記凸部と接触するように配置され、
前記第2支持部材側の焼結層は、前記中間金属層と前記第2支持部材とを接合し、
前記中間金属層は、前記焼結層よりも原子密度が低い焼結層とされている半導体装置。 - 前記上層接合部材は、複数の前記中間金属層を有している請求項5に記載の半導体装置。
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