JP7212783B2 - 電子素子実装用基板、電子装置、電子モジュールおよび電子素子実装用基板の製造方法 - Google Patents
電子素子実装用基板、電子装置、電子モジュールおよび電子素子実装用基板の製造方法 Download PDFInfo
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- JP7212783B2 JP7212783B2 JP2021535388A JP2021535388A JP7212783B2 JP 7212783 B2 JP7212783 B2 JP 7212783B2 JP 2021535388 A JP2021535388 A JP 2021535388A JP 2021535388 A JP2021535388 A JP 2021535388A JP 7212783 B2 JP7212783 B2 JP 7212783B2
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Description
以下、本開示のいくつかの例示的な実施形態について図面を参照して説明する。なお、以下の説明では、電子素子実装用基板に電子素子が実装された構成を電子装置とする。また、電子素子実装用基板に備わる電子装置を覆う筐体を備える構成を電子モジュールとする。電子素子実装用基板、電子装置および電子モジュールは、いずれの方向が上方若しくは下方とされてもよいが、便宜的に、直交座標系xyzを定義するとともに、z方向の正側を上方とする。また、上方から下方に向かう方向を第1方向とする。
図1~図9を参照して本開示の第1の実施形態に係る電子素子実装用基板、並びにそれを備えた電子装置について説明する。なお、図1は電子装置21の上面図および断面図を示しており、図2は電子モジュール31の上面図および断面図を示している。また、図3~図5には、図1における要部A、および図1における要部Aに相当する位置の拡大図の例を示している。また、図6~図9には、電子素子実装用基板1の製造方法における概略図を示している。
図1に電子装置21の例を示す。電子装置21は、電子素子実装用基板1と、電子素子実装用基板1の上面に実装された電子素子10を備えている。
図2に電子モジュール31の例を示す。電子モジュール31は、電子装置21に備わる電子素子10を覆う筐体32を備えている。筐体32を有することでより気密性の向上または外部からの応力が直接電子装置21に加えられることを低減することが可能となる。筐体32は、例えば樹脂または金属材料等からなる。図2においては、電子素子10が蓋体接続部材14および蓋体12によって覆われ、さらに筐体32で覆われている例を示している。なお、図2に示す例において筐体32は、電子素子実装用基板1の側面をも覆っているが、電子素子実装用基板1の上面において電子素子10を覆うものであってもよい。
次に、本実施形態の電子素子実装用基板1および電子装置21の製造方法の一例について説明する。なお、下記で示す製造方法の一例は、多数個取りの例の一例の製造方法である。
第1金属層6は、例えばシグナルラインである場合がある。一般的に、シグナルラインについては、電源およびグランドの電位のパターンとは異なり、1つの貫通導体5で他の配線と導通する。そのため、貫通導体5とシグナルラインはより電気的な接続の信頼性が高く要求される。これに対し、本実施形態のようにシグナルライン(第1金属層6)が第2部6bを有している構造であることで、電気的な接続の信頼性を向上させることが可能となる。
シグナルラインの他の例を図11に示す。図11においては、第1部6aが、貫通導体5に接して位置する第2部6bよりもy方向において小さく、第2部6bを基準にすれば第2部6bからx方向の負側に延びている例を示している。
図12に示すように、第1絶縁層2aは、第1方向に直交する方向において、第1金属層6と貫通導体5とに挟まれた領域を有していてもよい。このような構成を満たすときには、貫通導体5および第1金属層6に熱が生じたり、熱が伝わったりした際に、貫通導体5と第1金属層6とのそれぞれの膨張を抑制することができる。
次に、第2部6bの他の例について図13を参照しつつ説明する。
次に、第2部6bの他の例について図14を参照しつつ説明する。
2・・・・絶縁層
2a・・・第1絶縁層
2b・・・第2絶縁層
2c・・・第3絶縁層
3・・・・電極パッド
4・・・・実装領域
5・・・・貫通導体
6・・・・第1金属層
6a・・・第1部
6b・・・第2部
6b1・・・第1層
6b2・・・第2層
6c・・・・他の金属層
7・・・・第1クリアランス部
8・・・・第2クリアランス部
9・・・・第2金属層
10・・・電子素子
12・・・蓋体
13・・・電子素子接続部材
14・・・蓋体接続部材
21・・・電子装置
31・・・電子モジュール
32・・・筐体
42・・・グリーンシート
42a・・第1グリーンシート
42b・・第2グリーンシート
45・・・貫通導体
46・・・金属層(金属ペースト)
46a・・第1部
46b・・第2部
47・・・第1積層体
48・・・第2積層体
R1・・・第1領域
R2・・・第2領域
Claims (11)
- 第1方向に並んで位置する第1絶縁層および第2絶縁層と、
前記第1絶縁層および前記第2絶縁層の間に位置する第1金属層と、
前記第1絶縁層から前記第2絶縁層にわたって前記第1方向に延びる貫通導体と、を備え、
前記第1金属層は、前記貫通導体から離れて位置する第1部と、前記貫通導体に接する第2部と、を有しており、
前記第2部の厚みは、前記第1部の厚みよりも大きい、電子素子実装用基板。 - 前記第2部は、第1クリアランス部によって前記第1部と離れて位置している、請求項1に記載の電子素子実装用基板。
- 前記第2絶縁層と前記第1方向に並んで位置する第3絶縁層と、
前記第2絶縁層および前記第3絶縁層の間に位置する第2金属層と、をさらに備え、
前記貫通導体は、前記第1絶縁層から前記第3絶縁層にわたって前記第1方向に延び、
前記貫通導体は、第2クリアランス部によって前記第2金属層と離れて位置している、請求項1または請求項2に記載の電子素子実装用基板。 - 前記第1方向における平面透視において、前記第2クリアランス部は、前記第2部内に位置する、請求項3に記載の電子素子実装用基板。
- 前記第1方向における平面透視において、前記第2部は、前記第2クリアランス部内に位置する、請求項3に記載の電子素子実装用基板。
- 前記第2部は、前記貫通導体と接する第1領域と、前記第1領域と前記第1方向に直交する方向に並んで位置するとともに前記第1領域よりも前記貫通導体から離れて位置する第2領域と、を有しており、
前記第2領域の厚みが、前記第1領域の厚みよりも小さい、請求項1乃至請求項5のいずれかに記載の電子素子実装用基板。 - 前記第1絶縁層は、前記第1方向に直交する方向において、前記第1金属層と前記貫通導体とに挟まれた領域を有する、請求項1乃至請求項6のいずれかに記載の電子素子実装用基板。
- 請求項1~7のいずれか1つに記載の電子素子実装用基板と、
電子素子実装用基板に実装された電子素子と、を備えている、電子装置。 - 請求項8に記載の電子装置と、
前記電子装置に備わる前記電子素子を覆う筐体と、を備えている、電子モジュール。 - 第1絶縁層および第2絶縁層を準備する第1工程と、
前記第2絶縁層に、厚みに違いを有する第1金属層を配置する第2工程と、
前記第1金属層を挟んで前記第2絶縁層に前記第1絶縁層を積層し、第1積層体を得る第3工程と、
積層方向において、前記第1金属層における厚みの大きい部分を貫通するように前記第1積層体を貫通する貫通孔を形成する第4工程と、
前記貫通孔内に貫通導体を形成する第5工程と、を備える、電子素子実装用基板の製造方法。 - 金属層Aと、金属層Bと、第1絶縁層および第2絶縁層とを準備する工程Aと、
前記第1絶縁層に前記金属層Aを配置し、該金属層Aの少なくとも一部に前記金属層Bを配置する工程Bと、
前記金属層Aおよび前記金属層Bが配置された前記第1絶縁層、ならびに前記第2絶縁層を順に積層して、第2積層体を得る工程Cと、
積層方向において、前記金属層Aおよび前記金属層Bが互いに重なっている部分を貫通するように前記第2積層体を貫通する貫通孔を形成する工程Dと、
前記貫通孔内に貫通導体を形成する工程Eと、を備える、電子素子実装用基板の製造方法。
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JP2009289805A (ja) | 2008-05-27 | 2009-12-10 | Kyocera Corp | 部品内蔵基板 |
JP2014033004A (ja) | 2012-08-01 | 2014-02-20 | Ngk Spark Plug Co Ltd | 多層セラミック基板及びその製造方法 |
JP2017107933A (ja) | 2015-12-08 | 2017-06-15 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
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