JPWO2021020447A1 - - Google Patents

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Publication number
JPWO2021020447A1
JPWO2021020447A1 JP2021535388A JP2021535388A JPWO2021020447A1 JP WO2021020447 A1 JPWO2021020447 A1 JP WO2021020447A1 JP 2021535388 A JP2021535388 A JP 2021535388A JP 2021535388 A JP2021535388 A JP 2021535388A JP WO2021020447 A1 JPWO2021020447 A1 JP WO2021020447A1
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Japan
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JP2021535388A
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JP7212783B2 (ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
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    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/4814Conductive parts
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    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1283After-treatment of the printed patterns, e.g. sintering or curing methods
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    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits

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JP2021535388A 2019-07-30 2020-07-29 電子素子実装用基板、電子装置、電子モジュールおよび電子素子実装用基板の製造方法 Active JP7212783B2 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165355A (ja) * 2004-12-09 2006-06-22 Matsushita Electric Ind Co Ltd 多層配線基板とその製造方法
JP2009289805A (ja) * 2008-05-27 2009-12-10 Kyocera Corp 部品内蔵基板
JP2014033004A (ja) * 2012-08-01 2014-02-20 Ngk Spark Plug Co Ltd 多層セラミック基板及びその製造方法
JP2017107933A (ja) * 2015-12-08 2017-06-15 新光電気工業株式会社 配線基板及びその製造方法

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Publication number Priority date Publication date Assignee Title
US9521754B1 (en) * 2013-08-19 2016-12-13 Multek Technologies Limited Embedded components in a substrate
JP2019079987A (ja) * 2017-10-26 2019-05-23 京セラ株式会社 電子素子実装用基板、電子装置および電子モジュール

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165355A (ja) * 2004-12-09 2006-06-22 Matsushita Electric Ind Co Ltd 多層配線基板とその製造方法
JP2009289805A (ja) * 2008-05-27 2009-12-10 Kyocera Corp 部品内蔵基板
JP2014033004A (ja) * 2012-08-01 2014-02-20 Ngk Spark Plug Co Ltd 多層セラミック基板及びその製造方法
JP2017107933A (ja) * 2015-12-08 2017-06-15 新光電気工業株式会社 配線基板及びその製造方法

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