JP7168281B2 - 超高密度集積回路における位置合わせされたビアを作成する方法 - Google Patents
超高密度集積回路における位置合わせされたビアを作成する方法 Download PDFInfo
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- JP7168281B2 JP7168281B2 JP2018160009A JP2018160009A JP7168281B2 JP 7168281 B2 JP7168281 B2 JP 7168281B2 JP 2018160009 A JP2018160009 A JP 2018160009A JP 2018160009 A JP2018160009 A JP 2018160009A JP 7168281 B2 JP7168281 B2 JP 7168281B2
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- 229910052751 metal Inorganic materials 0.000 claims description 103
- 239000002184 metal Substances 0.000 claims description 103
- 229920002120 photoresistant polymer Polymers 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 55
- 238000005530 etching Methods 0.000 claims description 49
- 238000012545 processing Methods 0.000 claims description 21
- 230000009977 dual effect Effects 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 14
- 238000004380 ashing Methods 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 10
- 238000009713 electroplating Methods 0.000 claims description 9
- 238000011112 process operation Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 239000006117 anti-reflective coating Substances 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 description 35
- 230000015572 biosynthetic process Effects 0.000 description 14
- 239000000463 material Substances 0.000 description 14
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 6
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 238000004590 computer program Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- WMIYKQLTONQJES-UHFFFAOYSA-N hexafluoroethane Chemical compound FC(F)(F)C(F)(F)F WMIYKQLTONQJES-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- ZLIBICFPKPWGIZ-UHFFFAOYSA-N pyrimethanil Chemical compound CC1=CC(C)=NC(NC=2C=CC=CC=2)=N1 ZLIBICFPKPWGIZ-UHFFFAOYSA-N 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67138—Apparatus for wiring semiconductor or solid state device
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Description
Claims (20)
- 集積回路内の金属ラインと位置合わせされたビアを形成する方法であって、
前記方法は、
誘電体層と、キャップ層と、ハードマスク層と、第1のフィルム層と、第1のフォトレジスト層とを含む第1の複数の層を含む積層体を形成する段階と、
金属ラインマスクを提供するよう前記第1のフォトレジスト層をパターニングする段階と、
前記ハードマスク層内に金属ラインマスクを形成するよう前記パターニングされた第1のフォトレジスト層に基づいて前記ハードマスク層をエッチングする段階と、
前記第1のフォトレジスト層および前記第1のフィルム層をアッシングする段階と、
第2のフィルム層と、第2のフォトレジスト層とを含む第2の複数の層を前記ハードマスク層上に形成する段階と、
前記金属ラインマスクの対向する両面を横切って延伸するビアマスクを形成するために前記第2のフォトレジスト層をパターニングする段階と、
前記パターニングされた第2のフォトレジスト層に基づいて前記第2のフィルム層および前記キャップ層をエッチングする段階と、
前記第2のフォトレジスト層および前記第2のフィルム層をアッシングする段階と、
複数のビア領域および複数の金属ライン領域を提供するよう前記ハードマスク層のパターンに基づいて前記誘電体層および前記キャップ層をエッチングする段階と、
前記ハードマスク層および前記キャップ層をエッチングする段階と、
前記複数のビア領域内および前記複数の金属ライン領域内に前記ビアおよび前記金属ラインを形成するよう、複数のデュアルダマシンプロセスのオペレーションを実行する段階とを備える方法。 - 前記第1の複数の層を形成する前記段階が、
前記誘電体層を形成する段階と、
前記誘電体層上に前記キャップ層を形成する段階と、
前記キャップ層上に前記ハードマスク層を形成する段階と、
前記ハードマスク層上に前記第1のフィルム層を形成する段階と、
前記第1のフィルム層上に前記第1のフォトレジスト層を形成する段階とを含む、請求項1に記載の方法。 - 前記第1のフィルム層がアモルファスシリコンまたは反射防止塗膜のうち少なくとも一方を含む、請求項1または2に記載の方法。
- 前記ハードマスク層が窒化チタニウムで形成される、請求項1から3のいずれか一項に記載の方法。
- 前記ハードマスク層が前記キャップ層をマスクする第1のマスク層として用いられ、前記キャップ層が前記誘電体層をマスクする第2のマスク層として用いられる、請求項1から4のいずれか一項に記載の方法。
- 前記第2の複数の層を形成する前記段階が、
前記ハードマスク層上に前記第2のフィルム層を形成する段階と、
前記第2のフィルム層上に前記第2のフォトレジスト層を形成する段階とを含む、請求項1から5のいずれか一項に記載の方法。 - 前記第2のフィルム層が、アモルファスシリコンまたは反射防止塗膜のうち少なくとも一方を含む請求項1から6のいずれか一項に記載の方法。
- 前記第2のフィルム層および前記キャップ層が、前記パターニングされた第2のフォトレジスト層に基づいて異方的にエッチングされる、請求項1から7のいずれか一項に記載の方法。
- 前記誘電体層および前記キャップ層のエッチングする前記段階が、前記ハードマスク層のパターンおよび前記キャップ層のパターンに基づいて前記誘電体層をエッチングする段階を含む、請求項1から8のいずれか一項に記載の方法。
- 前記誘電体層および前記キャップ層をエッチングする前記段階が、
前記誘電体層をエッチングする段階の後に、前記ハードマスク層のパターンに基づいて前記キャップ層をエッチングする段階と、
前記キャップ層をエッチングする段階の後に、前記ハードマスク層のパターンおよび前記キャップ層のパターンに基づいて前記誘電体層をエッチングする段階とを含む、請求項9に記載の方法。 - 前記誘電体層および前記キャップ層が前記ハードマスク層の前記パターンに基づいて異方的にエッチングされる、請求項1から10のいずれか一項に記載の方法。
- 前記誘電体層を形成する段階の前に、相互接続層を形成する段階と、前記相互接続層上にエッチングストップ層を形成する段階とをさらに備え、
前記誘電体層をエッチングする段階の後で、且つ前記複数のデュアルダマシンプロセスのオペレーションを実行する前に、前記相互接続層の最上面に到達するまで前記エッチングストップ層をエッチングする段階である、
請求項1から11のいずれか一項に記載の方法。 - 前記複数のデュアルダマシンプロセスのオペレーションが、
前記複数のビア領域および前記複数の金属ライン領域のそれぞれにバリア層を形成する段階と、
前記バリア層のそれぞれにシード層を形成する段階と、
前記シード層を電気めっきする段階とを含む、請求項1から12のいずれか一項に記載の方法。 - 基板を処理して、集積回路内に金属ラインと位置合わせされたビアを形成するための処理システムであって、前記処理システムが、
プロセッサと、
メモリと、
前記メモリに格納され、且つ複数の命令を含む1つまたは複数のアプリケーションとを備え、
前記複数の命令は、前記プロセッサによって、
誘電体層と、キャップ層と、ハードマスク層と、第1のフィルム層と、第1のフォトレジスト層とを含む、第1の複数の層を含む積層体を形成することと、
金属ラインマスクを提供するよう前記第1のフォトレジスト層をパターニングすることと、
前記ハードマスク層内に金属ラインマスクを形成するよう前記パターニングされた第1のフォトレジスト層に基づいて前記ハードマスク層をエッチングすることと、
前記第1のフォトレジスト層および前記第1のフィルム層をアッシングすることと、
第2のフィルム層と、第2のフォトレジスト層とを含む第2の複数の層を前記ハードマスク層上に形成することと、
前記金属ラインマスクの対向する両面を横切って延伸するビアマスクを形成するよう前記第2のフォトレジスト層をパターニングすることと、
前記パターニングされた第2のフォトレジスト層に基づいて前記第2のフィルム層および前記キャップ層をエッチングすることと、
前記第2のフォトレジスト層および前記第2のフィルム層をアッシングすることと、
複数のビア領域および複数の金属ライン領域を提供するよう前記ハードマスク層のパターンに基づいて、前記誘電体層および前記キャップ層をエッチングすることと、
前記ハードマスク層および前記キャップ層をエッチングすることと、
前記複数のビア領域内および前記複数の金属ライン領域内に前記ビアおよび前記金属ラインを形成するよう、複数のデュアルダマシンプロセスのオペレーションを実行することを行うように実行可能である、処理システム。 - 前記第1の複数の層を前記形成することが、
前記誘電体層を形成することと、
前記誘電体層上に前記キャップ層を形成することと、
前記キャップ層上に前記ハードマスク層を形成することと、
前記ハードマスク層上に前記第1のフィルム層を形成することと、
前記第1のフィルム層上に前記第1のフォトレジスト層を形成することとを含む、請求項14に記載の処理システム。 - 前記ハードマスク層が前記キャップ層をマスクする第1のマスク層として用いられ、前記キャップ層が前記誘電体層をマスクする第2のマスク層として用いられる、請求項14または15に記載の処理システム。
- 前記第2の複数の層を前記形成することが、
前記ハードマスク層上に前記第2のフィルム層を形成することと、
前記第2のフィルム層上に前記第2のフォトレジスト層を形成することとを含む、請求項14から16のいずれか一項に記載の処理システム。 - 前記第2のフィルム層および前記キャップ層が、前記パターニングされた第2のフォトレジスト層に基づいて異方的にエッチングされ、
前記誘電体層および前記キャップ層が前記ハードマスク層の前記パターンに基づいて異方的にエッチングされる、請求項14から17のいずれか一項に記載の処理システム。 - 前記誘電体層および前記キャップ層を前記エッチングすることが、
前記ハードマスク層のパターンおよび前記キャップ層のパターンに基づいて前記誘電体層をエッチングすることと、
前記誘電体層のエッチングの後に、前記ハードマスク層のパターンに基づいて前記キャップ層をエッチングすることと、
前記キャップ層のエッチングの後に、前記ハードマスク層のパターンおよび前記キャップ層のパターンに基づいて前記誘電体層をエッチングすることとを含む、請求項14から18のいずれか一項に記載の処理システム。 - 前記複数のデュアルダマシンプロセスのオペレーションが、
前記複数のビア領域および前記複数の金属ライン領域のそれぞれにバリア層を形成することと、
前記バリア層のそれぞれにシード層を形成することと、
前記シード層を電気めっきすることとを含む、請求項14から19のいずれか一項に記載の処理システム。
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US20190096756A1 (en) | 2019-03-28 |
US11081387B2 (en) | 2021-08-03 |
TW201923825A (zh) | 2019-06-16 |
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CN109560042B (zh) | 2024-04-12 |
KR20190035595A (ko) | 2019-04-03 |
US10522394B2 (en) | 2019-12-31 |
KR102619000B1 (ko) | 2023-12-28 |
US20200118868A1 (en) | 2020-04-16 |
JP2019062192A (ja) | 2019-04-18 |
TWI806904B (zh) | 2023-07-01 |
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