CN109560042A - 在超高密度集成电路中产生对准的过孔的方法 - Google Patents

在超高密度集成电路中产生对准的过孔的方法 Download PDF

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CN109560042A
CN109560042A CN201811116294.9A CN201811116294A CN109560042A CN 109560042 A CN109560042 A CN 109560042A CN 201811116294 A CN201811116294 A CN 201811116294A CN 109560042 A CN109560042 A CN 109560042A
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layer
capped
hard mask
metal wire
photoresist
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CN109560042B (zh
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常润滋
佘敏
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Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
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Mawier International Trade Co Ltd
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Abstract

提供了一种在集成电路中形成与金属线对准的过孔的方法。该方法包括：形成堆叠的电介质层、加帽层、硬掩模层以及第一膜层和第一光刻胶层；图案化第一光刻胶层以提供金属线掩模；基于图案化的第一光刻胶层蚀刻硬掩模层，以形成金属线掩模；灰化第一光刻胶层和第一膜层；在硬掩模层上形成第二膜层和第二光刻胶层；图案化第二光刻胶层以跨金属线掩模的相对侧形成过孔掩模；基于图案化的第二光刻胶层蚀刻第二膜层和加帽层；灰化第二光刻胶层和第二膜层；基于硬掩模层的图案蚀刻电介质层和加帽层，以提供过孔区域和金属线区域；蚀刻硬掩模层和加帽层；以及执行双镶嵌工艺操作，以在过孔区域和金属线区域中形成过孔和金属线。

Description

在超高密度集成电路中产生对准的过孔的方法
相关申请的交叉引用
本申请要求于2017年9月25日提交的美国临时申请No.62/562,846的权益。上述申请的全部公开内容通过引用并入本文。
技术领域
本公开涉及集成电路的制造，并且更具体地涉及在超高密度集成电路中的过孔的形成。
背景技术
本文中提供的背景描述是为了总体上呈现本公开的上下文。就在本背景技术部分中描述的程度而言，当前署名的发明人的工作以及在提交时可能不以其它方式视为现有技术的本描述的各方面既不明确也不隐含地被承认是本公开的现有技术。
在制造诸如某些存储器芯片等超高密度集成电路(UHDIC)期间，形成金属线和过孔以提供各种导电连接。金属线和过孔之间的节距通常是UHDIC的导电元件之间的最小节距。金属线和过孔可以使用双镶嵌工艺形成。在双镶嵌工艺期间，为金属线和过孔形成掩模。过孔的掩模可以覆盖金属线的掩模。由于处理误差、系统偏移和/或噪声，过孔的掩模可能未与金属线的掩模对准。结果，一个或多个过孔可能更靠近一个或多个金属线而间隔开，从而进一步减小金属线与过孔之间的最小节距。
这种掩模层到掩模层套刻误差由图1A至图2B图示出，图1A至图2B示出了金属线和相应的过孔。图1A和图1B示出了两个过孔100、102，两个过孔100、102在金属线104、106延伸的方向上与两个金属线104、106对准，使得过孔100、102中的每个过孔的两个相对侧108、110与每个金属线的两个相对侧112、114对准。过孔100、102沿着金属线104、106的端部116、118设置并且设置在这些端部116、118之间。两个金属线104、106可以是Vdd和Vss网(或轨)并且在同一层Mx中。第一金属线104可以连接到电压源并且处于电压Vdd。第二金属线106可以连接到参考端子(或接地)并且具有电压Vss。第一过孔100可以如图所示连接到互连线(未示出)，该互连线可以在层Mx-1中。对准的金属线104、106和过孔100、102具有相关联的金属线到过孔节距S(即，金属线104、106中的每个金属线与过孔100、102中的连接到金属线104、106中的另一金属线的对应过孔之间的距离)。
图2A和图2B示出了相对于两个金属线204、206未对准的两个过孔200、202。图2A示出了偏离金属线204、206并且具有相关联的金属线到过孔节距S'的过孔200、202。金属线204、206位于同一层Mx中。第一过孔200可以连接到电压源并且处于电压Vdd。第二过孔202可以连接到参考端子(或接地)并且具有电压Vss。第一过孔200可以连接到互连线(未示出)，该互连线可以在层Mx-1中。
UHDIC通常被设计成使电路元件之间的节距最小化。这包括最小化金属线与过孔之间的间距。金属线与过孔之间的间距可以基于光刻分辨率限值来设置。最小化间距使相关联的芯片面积最小化。然而，由于上述掩模层到掩模层套刻误差，间距在某些区域中可以进一步减小。在深亚纳米(nm)工艺中，掩模的套刻误差成为金属线到过孔边缘布局误差的很大一部分。Vdd金属线以及Vss金属线与过孔之间的间距减小可能导致电路元件之间的短路和/或金属线与过孔之间的电介质材料随时间的击穿。短路可能导致功能故障。如果电路元件之间的电介质随时间击穿(称为时间相关的电介质击穿(TDDB))，则存在可靠性问题。
发明内容
提供了一种在集成电路中形成与金属线对准的过孔的方法。该方法包括：形成包括第一层的堆叠，其中第一层包括电介质层、加帽层、硬掩模层、第一膜层和第一光刻胶层；图案化第一光刻胶层以提供金属线掩模；基于图案化的第一光刻胶层蚀刻硬掩模层，以在硬掩模层中形成金属线掩模；灰化第一光刻胶层和第一膜层；以及在硬掩模层上形成第二层，其中第二层包括第二膜层和第二光刻胶层。该方法还包括：图案化第二光刻胶层以形成过孔掩模，其中过孔掩模跨金属线掩模的相对侧延伸；基于图案化的第二光刻胶层蚀刻第二膜层和加帽层；灰化第二光刻胶层和第二膜层；基于硬掩模层的图案蚀刻电介质层和加帽层，以提供过孔区域和金属线区域；蚀刻硬掩模层和加帽层；以及执行双镶嵌工艺操作，以在过孔区域和金属线区域中形成过孔和金属线。
在其它特征中，提供了一种用于处理衬底并且在集成电路中形成与金属线对准的过孔的处理系统。处理系统包括处理器、存储器以及存储在存储器中并且包括指令的一个或多个应用。这些指令是由处理器可执行的以：形成包括第一层的堆叠，其中第一层包括电介质层、加帽层、硬掩模层、第一膜层和第一光刻胶层；图案化第一光刻胶层以提供金属线掩模；基于图案化的第一光刻胶层蚀刻硬掩模层，以在硬掩模层中形成金属线掩模；并且灰化第一光刻胶层和第一膜层。这些指令是进一步可执行的以：在硬掩模层上形成第二层，其中第二层包括第二膜层和第二光刻胶层；图案化第二光刻胶层以形成过孔掩模，其中过孔掩模跨金属线掩模的相对侧延伸；基于图案化的第二光刻胶层蚀刻第二膜层和加帽层；灰化第二光刻胶层和第二膜层；基于硬掩模层的图案蚀刻电介质层和加帽层，以提供过孔区域和金属线区域；蚀刻硬掩模层和加帽层；以及执行双镶嵌工艺操作，以在过孔区域和金属线区域中形成过孔和金属线。
根据具体实施方式、权利要求和附图，本公开的其它应用领域将变得很清楚。详细描述和具体示例仅用于说明的目的，并不旨在限制本公开的范围。
附图说明
图1A是包括对准的金属线和过孔的IC的一部分的俯视图；
图1B是穿过图1A的截线A-A'的截面图；
图2A是未对准的金属线和过孔的俯视图；
图2B是穿过图2A的截线A-A'的截面图；
图3示出了根据本公开的实施例的形成IC的对准过孔的方法；
图4A是根据本公开的实施例形成的IC的互连层的一部分的示例的穿过图4B的截线A-A'和互连的截面图；
图4B是沿着垂直于图4A的截面的方向截取的与图4A相对应的互连层的一部分的示例的截面图；
图5A是穿过图5B的截线A-A'的截面图，其示出了示例性蚀刻停止层、电介质层、加帽层和硬掩模层在图4A的互连层上的形成；
图5B是在垂直于图5A的截面的方向上的穿过图5A的互连层、蚀刻停止层、电介质层、加帽层和硬掩模层截取的截面图；
图6A是示出根据本公开的实施例的在图5A至图5B的硬掩模层上方形成第一光刻胶层的示例以提供金属线掩模的俯视图；
图6B是与图6A的截线A-A'相对应的截面图，其示出了根据本公开的实施例的第一图案化膜层和包括金属线掩模的第一光刻胶层的示例的形成；
图6C是与图6A的截线B-B'相对应的截面图，其示出了根据本公开的实施例的图6B的金属线掩模之一的形成；
图7A是示出根据本公开的实施例的蚀刻后的图5A至图5B的硬掩模层的示例的俯视图；
图7B是与图7A的截线A-A'相对应的截面图，其示出了根据本公开的实施例的蚀刻后的硬掩模层和金属线掩模、以及对图案抗蚀剂层和光刻胶层的其余部分的蚀刻去除；
图7C是与图7A的截线B-B'相对应的截面图，其示出了根据本公开的实施例的蚀刻后的硬掩模层、金属线掩模之一、以及对第一图案化膜层和第一光刻胶层的其余部分的蚀刻去除；
图8A是示出在图7B至图7C的蚀刻后的硬掩模层上方形成第二光刻胶层的示例以提供根据本公开的实施例的尺寸超大的过孔掩模的俯视图；
图8B是与图8A的截线A-A'相对应的截面图，其示出了根据本公开的实施例的在图7B至图7C蚀刻后的硬掩模层上形成第二图案化膜层和包括尺寸超大的过孔掩模之一的图8A的第二光刻胶层的示例；
图8C是与图8A的截线B-B'相对应的截面图，其示出了根据本公开的实施例的尺寸超大的过孔掩模之一的形成；
图9A是示出根据本公开的实施例的在蚀刻之后的图8B至图8C的图案化膜层的俯视图；
图9B是与图9A的截线A-A'相对应的截面图，其示出了在蚀刻之后的图8B至图8C的第二图案化膜层和加帽层；
图9C是与图9A的截线B-B'相对应的截面图，其示出了在蚀刻之后的图8B至图8C的第二图案化膜层和加帽层；
图10A是示出图9B至图9C的蚀刻后的硬掩模层的俯视图；
图10B是与图10A的第二线A-A'相对应的截面图，其示出了根据本公开的实施例的灰化去除图9B至图9C的第二图案化膜层和第二光刻胶层；
图10C是与图10B的第二线B-B'相对应的截面图，其示出了根据本公开的实施例的灰化去除图9B至图9C的第二图案化膜层和第二光刻胶层；
图11A是图9B至图9C的蚀刻后的硬掩模层的俯视图；
图11B是与图11A的截线A-A'相对应的截面图，其示出了根据本公开的实施例的蚀刻后的电介质层；
图11C是与图11A的截线B-B'相对应的截面图，其示出了根据本公开的实施例的蚀刻后的电介质层；
图12A是图9B至图9C的蚀刻后的硬掩模层的俯视图；
图12B是与图12A的截线A-A'相对应的截面图，其示出了根据本公开的实施例的蚀刻后的加帽层；
图12C是与图12A的截线B-B'相对应的截面图，其示出了根据本公开的实施例的蚀刻后的加帽层；
图13A是图9B至图9C的蚀刻后的硬掩模层的俯视图；
图13B是与图13A的截线A-A'相对应的截面图，其示出了根据本公开的实施例的蚀刻后的电介质层；
图13C是与图13A的截线B-B'相对应的截面图，其示出了根据本公开的实施例的蚀刻后的电介质层；
图14A是示出根据本公开的实施例的金属线的线开口的电介质层的俯视图；
图14B是图13B至图13C的电介质层、蚀刻停止层和互连层的截面图，其示出了根据本公开的实施例的蚀刻后的蚀刻停止层；
图14C是沿着垂直于图14B的截面的方向截取的图13B至图13C的电介质层、蚀刻停止层和互连层的截面图，其示出了根据本公开的实施例的蚀刻后的蚀刻停止层；
图15A是电介质层的俯视图，其示出了根据本公开的实施例的形成的阻挡层、种子层和电镀层，这些层提供金属线；
图15B是图14A至图14C的电介质层、蚀刻停止层和互连层的截面图，其示出了根据本公开的实施例的形成的阻挡层、种子层和电镀层、以及由某些层的化学机械平坦化提供的平坦化的顶表面；
图15C是沿着垂直于图15B的截面的方向截取的图14A至图14C的电介质层、蚀刻停止层和互连层的截面图，其示出了根据本公开的实施例的形成的阻挡层、种子层和电镀层、以及由某些层的化学机械平坦化提供的平坦化的顶表面；
图16是根据本公开的实施例形成的包括金属线和对准的过孔的IC的一部分的示例；
图17是根据本公开的实施例形成的六晶体管静态随机存取存储器单元的示例；
图18是根据本公开的实施例的被配置为执行图3的方法的处理系统的示例；以及
图19是根据本公开的实施例的控制模块的示例。
在附图中，可以重复使用附图标记来标识相似和/或相同的元件。
具体实施方式
可以通过增加金属线与过孔之间的设计间距(或节距)来防止与金属线到过孔的间距相关联的功能和可靠性问题。然而，这可能增加电路元件所使用的面积，增加相关联的IC的尺寸和成本，导致在设计中引入额外的限制，并且增加套刻误差管理和逻辑复杂性。
本文中阐述的示例包括将过孔的堆叠部分对准和将过孔与金属线对准的方法。该方法包括引入硬掩模层，提供与传统的过孔掩模层不同地图案化和成形的过孔掩模层，以及其它独特的处理操作。该方法消除了金属线与过孔之间的未对准误差，并且从而允许金属线与过孔之间的对应节距最小化。可以将节距最小化到光刻分辨率限值。结果，芯片尺寸、成本以及对应的功能和可靠性问题被最小化。该方法包括确定和调节过孔掩模的尺寸而不影响金属线到过孔(或金属到金属)的间距。过孔掩模在与对应金属线延伸的方向垂直的方向上尺寸超大。这确保了在硬掩模层的蚀刻掉的部分上去除图案化膜层，用于适当地蚀刻电介质层以实现对准过孔形成。
图3示出了形成IC的对准过孔和/或其它导电元件的方法。该方法可以被称为一种双镶嵌工艺，但是包括传统上在双镶嵌工艺期间未执行的操作。该方法可以由图18的示例处理系统执行或另一合适的处理系统来执行。操作可以由图18至图19的控制模块来控制和定时。该方法可以在制造IC和/或IC的对应层的同时执行。在一个实施例中，该方法包括将过孔的部分对准并且将过孔与金属线对准。该方法包括形成和成形过孔掩模和层堆叠以提供对准的过孔。该方法允许过孔掩模套刻误差，同时提供对准的过孔，这降低了IC制造期间的芯片和系统产量损失。在图4A至图15B中示出了可以在该方法期间执行的至少一些操作。
该方法可以在300处开始。在302处，形成互连层和/或其它层，过孔和/或金属线可以延伸到和/或终止于互连层和/或其它层。图4A至图4B示出了正在形成的IC的互连层的一部分400。部分400包括互连402、404。互连402、404由电介质材料406分隔开。
在304处，作为示例，在302处的互连层上形成包括蚀刻停止层500、电介质层502、加帽层504和硬掩模层506的多个非导电层。图5A至图5B示出了在图4A的部分400上形成层500、502、504和506。电介质层502可以是低电介质常数(低k)的电介质膜。在一个实施例中，电介质层502的电介质常数k大于1且小于2.7法拉每米(F/m)。作为示例，电介质层502可以由掺杂碳的氧化硅SiO2形成。加帽层504可以是由与电介质层502不同的材料形成的电介质膜层。作为示例，加帽层504可以由氮化硅Si3N4形成。作为示例，硬掩模层506可以由氮化钛TiN形成。
在306处，形成第一图案化膜层600和第一光刻胶层602。图6A至图6C示出了在图5A至图5B的硬掩模层上形成包括金属线掩模604的层600、602。金属线掩模604是光刻胶层602的部分606之间的开口区域。在一个实施例中，图案化膜层600由非晶硅和/或抗反射涂层膜形成。光刻胶层602可以旋涂并且使用光刻法进行图案化，以提供金属线掩模604(示出为沟槽)，金属线掩模604在随后的操作中用于蚀刻硬掩模层506。
在308处，在金属线掩模604下方的区域中使用第一蚀刻材料组合物(例如，四氟甲烷(CF4)-氧(O2)等离子体)蚀刻第一图案化膜层600和硬掩模层506的暴露部分，以在硬掩模层506中提供金属线开口(或掩模)700。开口700位于硬掩模层506的部分702之间。在加帽层504的顶表面上停止蚀刻。在310处，灰化去除第一图案化膜层600和第一光刻胶层602的其余部分。图7A至图7C示出了蚀刻后的硬掩模层506和金属线掩模604、以及对第一图案化膜层600和第一光刻胶层602的其余部分的蚀刻去除。
在312处，在硬掩模层506和加帽层504上形成第二图案化膜层800和第二光刻胶层802。图8A至图8C示出了在图7B至图7C的蚀刻后的硬掩模层506上形成第二图案化膜层800和包括尺寸超大的过孔掩模804的第二光刻胶层802。第二图案化膜层800可以由非晶硅和/或抗反射涂层膜形成。第二光刻胶层802可以旋涂并且使用光刻法进行图案化，以提供过孔掩模804。过孔掩模804的尺寸超大并且在随后的操作中用于蚀刻第二图案化膜层800和加帽层504。过孔掩模804是第二光刻胶层802的部分806之间的开口区域。过孔掩模804可以在硬掩模层506中的相应开口上方居中或不居中。例如，过孔掩模804'在图8B中被示出为在硬掩模层506中的开口807之上不居中。如图8B所示，过孔掩模804'偏移到开口807的中心线809的右侧。过孔掩模804的超大尺寸允许在使过孔掩模804在硬掩模层506中的对应金属线掩模之上居中时存在误差。
过孔掩模804被成形为在线掩模700的相对侧808之上延伸。每个过孔掩模804垂直于金属线掩模之一并且在该金属线掩模的每个相对侧808(或边缘)之上延伸。过孔掩模804在对过孔对准误差(诸如图2A和2B中所示的误差等)敏感的方向上延伸。如图所示，每个过孔掩模804可以跨金属线掩模之一并且在硬掩模层506的部分之上延伸。在一个实施例中，过孔掩模804延伸超过侧808的量大于0且小于或等于金属线掩模之间的距离S(即，要产生金属线之间的节距)的50％。过孔掩模使在正在形成的IC中的目标过孔的区域开放。该过程在双镶嵌工艺操作期间提供套刻误差容限(或套刻误差的额外余量)。
在314处，在312处形成的过孔掩模之后，基于图案化的第二光刻胶层802和第二图案化膜层800，各向异性地蚀刻第二图案化膜层800和加帽层504的暴露部分。各向异性蚀刻包括仅在竖直方向(或例如垂直于在层500、502、504和506中的两个相邻层之间延伸的平面的方向)上的定向等离子体干法蚀刻。该蚀刻可以包括使用与第一组合物不同的第二蚀刻材料组合物(例如，三氟化氮(NF3)-氧(O2)等离子体)。图9A至图9C示出了在经蚀刻的状态下的图8B至图8C的图案化膜层800和加帽层504。各向异性蚀刻在第二图案化膜层800中提供尺寸超大的过孔开口(或掩模)900，并且在加帽层504中提供过孔开口902。蚀刻后的硬掩模层506的图案用于将加帽层504中的过孔开口902对准。在电介质层502的顶表面处停止蚀刻。在由第二图案化膜层800和第二光刻胶层802覆盖的硬掩模层506中的开口(或掩模)下方的区域(例如，区域904)中不蚀刻加帽层504。
在316处，灰化去除第二光刻胶层802和第二图案化膜层800。图10A至图10C示出了从硬掩模层506去除图9B至图9C的第二图案化膜层800和第二光刻胶层802。在执行该灰化工艺之后，层502、504和506保留。
在318处，基于硬掩模层506和加帽层504的图案，各向异性地蚀刻电介质层502的暴露部分。图11A至图11C示出了各向异性蚀刻后的电介质层502。硬掩模层506和加帽层504均用作掩模层。硬掩模层506可以被称为第一掩模层，并且加帽层504可以被称为第二掩模层。如图所示，在硬掩模层506和加帽层504的先前去除的区域下方的区域中各向异性地蚀刻电介质层502。使用第三蚀刻材料组合物(例如，三氟甲烷(CHF3)等离子体)来蚀刻电介质层502。第三组合物可以与第一组合物和第二组合物不同。在该操作期间的层堆叠被蚀刻到一定深度，使得对应沟槽的深度D等于待形成的过孔的高度H减去硬掩模层506的厚度T。深度D和厚度T在图11A中示出，并且高度H在图14C中示出。
在320处，基于硬掩模层506的图案对加帽层504的暴露部分进行各向异性蚀刻。可以使用第四蚀刻材料组合物(例如，三氟化氮(NF3)-氧(O2)-氩(Ar)等离子体)蚀刻加帽层504。在图12A至图12C中，加帽层504具有额外的蚀刻掉的部分。第四蚀刻材料组合物可以与第一组合物、第二组合物和第三组合物不同。通过在加帽层504中的这种蚀刻而产生的开口标记为1200。在该操作期间未蚀刻电介质层502。
在322处，基于硬掩模层506和加帽层504的图案进一步蚀刻电介质层502。图13A至图13C示出了在该蚀刻之后的电介质层502。可以使用第五蚀刻材料组合物(例如，三氟甲烷(CHF3)等离子体)蚀刻电介质层502。第五组合物可以与第三蚀刻材料组合物匹配或不同。第五组合物可以与第一组合物和第二组合物不同。蚀刻电介质层502直到过孔区域1300到达蚀刻停止层500的顶表面。电介质层502的这种蚀刻还提供开口区域，诸如开口区域1302，用于在后续操作期间形成金属线。
在324处，基于硬掩模层506的图案、加帽层504的图案和/或电介质层502的图案来对蚀刻停止层500进行各向异性地蚀刻，以延伸过孔区域。可以使用第六蚀刻材料组合物(例如，六氟乙烷(C2F6)-氧(O2)-氩(Ar)等离子体)执行该蚀刻工艺。图14A至图14C示出了图13B至图13C的电介质层502、蚀刻停止层500和互连层402，其示出了在蚀刻之后的蚀刻停止层。第六蚀刻材料组合物可以与第一组合物、第二组合物、第三组合物、第四组合物和第五组合物不同。在326处，蚀刻掉硬掩模层506和加帽层504。这可以包括施加第七蚀刻材料组合物(例如，四氟甲烷(CF4)-氧(O2)等离子体)，并且然后施加第八蚀刻材料组合物(例如，三氟化氮(NF3)-氧(O2)等离子体)。第七组合物和第八组合物可以与第一组合物、第二组合物、第三组合物、第四组合物、第五组合物和第六组合物不同。在操作324和326期间未蚀刻电介质层502。
尽管示出为单个操作，但是操作328包括多个操作，这些操作被执行以完成双镶嵌工艺。在328处，在过孔区域1300和金属线区域1302中形成阻挡层1500(例如，氮化钛TiN层)、种子层1502和电镀层1504。图15A至图15C示出了图14A至图14C的电介质层502、蚀刻停止层500和互连层402，其示出了层1500、1502、1504的形成以及电介质层502和电镀层1504的化学机械平坦化(CMP)。种子层1502可以形成在阻挡层1500之上。然后执行电镀以填充过孔区域1300和金属线区域1302的未被阻挡层1500和种子层1502填充的其余部分，以提供电镀层1504。种子层1502和电镀层1504可以由相同或不同的材料和/或材料组合物形成。在电镀之后，可以执行CMP，以去除所得到的堆叠的顶部部分并且提供平面的整个顶表面1506。所得到的堆叠包括金属线1510和过孔1512。
如图14B至图14C所示提供的所得到的堆叠包括金属线区域与过孔区域之间的如下间距，该间距允许形成种子层1502和电镀层1504以形成具有预定最小节距S的金属线和过孔。提供预定最小节距S而没有金属线与过孔之间的对准误差。这允许设计者基于例如光刻分辨率限值来最小化节距S。这消除了可靠性误差。该方法可以在330结束。
上述方法可以应用于高密度存储器芯片、高密度IC、和/或其中要在电路元件、逻辑电路元件、模拟电路块、数字电路块等之间提供最小节距的其它应用。尽管关于将过孔与金属线对准描述了上述方法，但是当将互连与触点对准(例如，下面的开槽触点)时和/或当将其它电路元件对准时，可以应用所描述的对准。
上述操作旨在是说明性示例。这些操作可以根据应用顺序地、同步地、同时地、连续地、在重叠时间段期间或以不同顺序执行。而且，取决于事件的实现和/或顺序，可以不执行或跳过任何操作。
上述方法包括形成尺寸超大的过孔掩模以允许掩模中的套刻误差和导电元件的形成，诸如金属线、过孔、互连、触点等。该方法可扩展到不同代的芯片技术并且允许更小的芯片面积并且从而允许IC的尺寸和成本节省。
图16是根据上述方法形成的包括金属线1602和对准的过孔1604的IC的一部分1600的示例。在所示的示例中，两个金属线1602分别连接到电源和参考端子。过孔1604可以连接到互连或触点1605。电源提供电源电压Vdd。参考端子处于电压电势Vss。如图所示，过孔1604可以连接到包括p沟道金属氧化物半导体(PMOS)晶体管和n沟道金属氧化物半导体(NMOS)晶体管的互补金属氧化物半导体(CMOS)反相器电路的p+和n+掺杂区域。晶体管的P阱区域和n阱区域可以设置在基部(或最底部)层1608中。CMOS反相器电路可以在例如高密度存储器中实现。晶体管具有栅极1610。图17中示出了可以包括CMOS反相器电路和相应的堆叠的六晶体管静态随机存取存储器(SRAM)单元的示例。
图17示出了SRAM存储器的六晶体管SRAM单元1700。六晶体管SRAM存储器单元1700包括：字线WL；位线BL、BL'；分别包括晶体管P1、N1和P2、N2的CMOS反相器电路；以及NMOS晶体管N3、N4。晶体管P1、P2连接到电源并且具有在Vdd处的源极端子。晶体管N1、N2连接参考端子并且具有在Vss处的源极端子。
图18示出了被配置为执行图3的方法的处理系统1800。处理系统1800可以包括各种腔室1802和被编程为根据图3的方法处理衬底的群集工具1830。每个腔室1802可以用于执行所述过程中的一个或多个操作。为了执行制造过程的操作，可以改变腔室的布置和组合。群集工具1830优选地配备有被编程为执行图3的方法的控制模块1832。为了开始该过程，通过盒式装载锁1840引入衬底。机器人1842、1843可以具有在腔室1802之间传送衬底的叶片(例如，叶片1844)。处理系统1800可以从电源1845接收电力。
图19示出了控制模块1832的示例。控制模块1832可以包括光刻模块1900、掩模模块1902、去除模块1904、形成模块1906、双镶嵌完成模块1908、和/或用于执行图3的方法的操作的其它模块。作为示例，光刻模块1900可以执行操作306、312。掩模模块1902可以执行操作308、314。去除模块1904可以执行操作310、316。形成模块1906可以执行操作302、304、318、320、322、324、326。双镶嵌完成模块1907可以执行操作328。控制模块1832可以执行存储在存储器1910中的一个或多个应用。在一个实施例中，模块1900、1902、1903、1906和1908被实现为由控制模块1832执行的应用。
前面的描述本质上仅是说明性的，而不旨在以任何方式限制本公开、其应用或用途。本公开的广泛教导可以以各种形式实现。因此，尽管本公开包括特定示例，但是本公开的真实范围不应当受此限制，因为在研究了附图、说明书和所附权利要求之后，其它修改将变得很清楚。应当理解，在不改变本公开的原理的情况下，方法内的一个或多个步骤可以以不同的顺序(或同时)执行。此外，尽管上面将每个实施例描述为具有某些特征，但是关于本公开的任何实施例所描述的那些特征中的任何一个或多个可以在任何其它实施例中实现和/或与任何其它实施例的特征组合，即使该组合没有明确描述。换言之，所描述的实施例不是相互排斥的，并且一个或多个实施例彼此的置换仍然在本公开的范围内。
元件之间(例如，模块、电路元件、半导体层等之间)的空间和功能关系使用各种术语来描述，包括“连接”、“接合”、“耦合”、“相邻”、“靠近”、“之上”、“上方”、“下方”和“设置”。除非明确地描述为“直接”，否则当在上面的公开内容中描述第一和第二元件之间的关系时，该关系可以是直接关系，其中在第一和第二元件之间不存在其它中间元件，但该关系也可以是间接关系，其中在第一和第二元件之间存在(空间或功能上)一个或多个中间元件。如本文中使用的，短语A、B和C中的至少一个应当被解释为使用非排它性逻辑“或”表示逻辑(A或B或C)，并且不应当被解释为表示“A中的至少一个、B中的至少一个、以及C中的至少一个”。
在附图中，箭头所指示的箭头方向通常表示图示所关注的信息流(诸如数据或指令)。例如，当元件A和元件B交换各种信息但从元件A传输到元件B的信息与图示相关时，箭头可以从元件A指向元件B。这个单向箭头并不暗示没有其它信息从元件B传输到元件A。此外，对于从元件A发送到元件B的信息，元件B可以向元件A发送对信息的请求或接收对信息的确认。
在本申请中，包括以下定义，术语“模块”或术语“控制器”可以用术语“电路”代替。术语“模块”是指：专用集成电路(ASIC)；数字分立电路、模拟分立电路或混合模拟/数字分立电路；数字集成电路、模拟集成电路或混合模拟/数字集成电路；组合逻辑电路；现场可编程门阵列(FPGA)；执行代码的处理器电路(共享、专用或组)；存储由处理器电路执行的代码的存储器电路(共享、专用或组)；提供所描述的功能的其它合适的硬件组件；或者上述各项中的部分或全部的组合，诸如在片上系统中。
模块可以包括一个或多个接口电路。在一些示例中，接口电路可以包括连接到局域网(LAN)、因特网、广域网(WAN)或其组合的有线或无线接口。本公开的任何给定模块的功能可以分布在经由接口电路连接的多个模块之间。例如，多个模块可以允许负载平衡。在另一示例中，服务器(也称为远程或云)模块可以代表客户端模块完成某些功能。
如以上使用的术语“代码”可以包括软件、固件和/或微代码，并且可以是指程序、例程、函数、类、数据结构和/或对象。术语“共享处理器电路”涵盖执行来自多个模块的一些或所有代码的单个处理器电路。术语“组处理器电路”包括与附加处理器电路组合地执行来自一个或多个模块的一些或所有代码的处理器电路。对多个处理器电路的引用涵盖分立管芯上的多个处理器电路、单个管芯上的多个处理器电路、单个处理器电路的多个核、单个处理器电路的多个线程、或上述各项的组合。术语“共享存储器电路”涵盖存储来自多个模块的一些或所有代码的单个存储器电路。术语“组存储器电路”涵盖与附加存储器组合地存储来自一个或多个模块的一些或所有代码的存储器电路。
术语“存储器电路”是术语“计算机可读介质”的子集。本文中使用的术语“计算机可读介质”不涵盖通过介质(诸如在载波上)传播的瞬时电信号或电磁信号；因此，术语“计算机可读介质”可以被认为是有形的和非瞬态的。非瞬态有形计算机可读介质的非限制性示例是非易失性存储器电路(诸如闪存电路、可擦除可编程只读存储器电路或掩模只读存储器电路)、易失性存储器电路(诸如静态随机存取存储器电路或动态随机存取存储器电路)、磁存储介质(诸如模拟或数字磁带或硬盘驱动器)和光存储介质(诸如CD、DVD或蓝光光盘)。
在本申请中，被描述为具有特定属性或执行特定操作的装置元件被具体配置为具有那些特定属性并且执行那些特定操作。具体地，对用于执行动作的元件的描述表示该元件被配置为执行该动作。元件的配置可以包括对元件的编程，诸如通过在与元件相关联的非瞬态有形计算机可读介质上编码指令。
本申请中描述的装置和方法可以由通过配置通用计算机以执行计算机程序中实现的一个或多个特定功能而创建的专用计算机部分地或全部地来实现。上述功能块、流程图组件和其它元件用作软件规范，其可以通过熟练技术人员或程序员的例行工作转换成计算机程序。
计算机程序包括存储在至少一个非瞬态有形计算机可读介质上的处理器可执行指令。计算机程序还可以包括或依赖于存储的数据。计算机程序可以涵盖与专用计算机的硬件交互的基本输入/输出系统(BIOS)、与专用计算机的特定设备交互的设备驱动器、一个或多个操作系统、用户应用、后台服务、后台应用等。
计算机程序可以包括：(i)要解析的描述性文本，诸如HTML(超文本标记语言)、XML(可扩展标记语言)、或JSON(JavaScript对象表示法)，(ii)汇编代码，(iii)由编译器从源代码生成的对象代码，(iv)用于由解译器执行的源代码，(v)用于由即时编译器编译和执行的源代码等。仅作为示例，可以使用来自以下语言的语法来编写源代码，包括C、C++、C#、Objective-C、Swift、Haskell、Go、SQL、R、Lisp、Fortran、Perl、Pascal、Curl、OCaml、HTML5(超文本标记语言第5版)、Ada、ASP(动态服务器网页)、PHP(PHP：超文本预处理器)、Scala、Eiffel、Smalltalk、Erlang、Ruby、VisualLua、MATLAB、SIMULINK和

Claims (20)

1.一种在集成电路中形成与金属线对准的过孔的方法，所述方法包括：
形成包括第一多个层的堆叠，其中所述第一多个层包括电介质层、加帽层、硬掩模层、第一膜层和第一光刻胶层；
图案化所述第一光刻胶层以提供金属线掩模；
基于经图案化的第一光刻胶层蚀刻所述硬掩模层，以在所述硬掩模层中形成金属线掩模；
灰化所述第一光刻胶层和所述第一膜层；
在所述硬掩模层上形成第二多个层，其中所述第二多个层包括第二膜层和第二光刻胶层；
图案化所述第二光刻胶层以形成过孔掩模，其中所述过孔掩模跨所述金属线掩模的相对侧延伸；
基于经图案化的第二光刻胶层蚀刻所述第二膜层和所述加帽层；
灰化所述第二光刻胶层和所述第二膜层；
基于所述硬掩模层的图案蚀刻所述电介质层和所述加帽层，以提供多个过孔区域和多个金属线区域；
蚀刻所述硬掩模层和所述加帽层；以及
执行多个双镶嵌工艺操作，以在所述多个过孔区域和所述多个金属线区域中形成所述过孔和所述金属线。
2.根据权利要求1所述的方法，其中所述第一多个层的形成包括：
形成所述电介质层；
在所述电介质层上形成所述加帽层；
在所述加帽层上形成所述硬掩模层；
在所述硬掩模层上形成所述第一膜层；以及
在所述第一膜层上形成所述第一光刻胶层。
3.根据权利要求1所述的方法，其中所述第一膜层包括非晶硅或抗反射涂层膜中的至少一项。
4.根据权利要求1所述的方法，其中所述硬掩模层由氮化钛形成。
5.根据权利要求1所述的方法，其中：
所述硬掩模层用作第一掩模层以掩蔽所述加帽层；并且
所述加帽层用作第二掩模层以掩蔽所述电介质层。
6.根据权利要求1所述的方法，其中所述第二多个层的形成包括：
在所述硬掩模层上形成所述第二膜层；以及
在所述第二膜层上形成所述第二光刻胶层。
7.根据权利要求1所述的方法，其中所述第二膜层包括非晶硅或抗反射涂层膜中的至少一项。
8.根据权利要求1所述的方法，其中基于所述经图案化的第二光刻胶层对所述第二膜层和所述加帽层进行各向异性蚀刻。
9.根据权利要求1所述的方法，其中所述电介质层和所述加帽层的蚀刻包括：基于所述硬掩模层的图案和所述加帽层的图案来蚀刻所述电介质层。
10.根据权利要求9所述的方法，其中所述电介质层和所述加帽层的蚀刻包括：
在蚀刻所述电介质层之后，基于所述硬掩模层的图案蚀刻所述加帽层；以及
在蚀刻所述加帽层之后，基于所述硬掩模层的图案和所述加帽层的图案来蚀刻所述电介质层。
11.根据权利要求1所述的方法，其中基于所述硬掩模层的图案对所述电介质层和所述加帽层进行各向异性蚀刻。
12.根据权利要求1所述的方法，还包括：在形成所述电介质层之前，形成互连层并且在所述互连层上形成蚀刻停止层，
其中在蚀刻所述电介质层之后并且在执行所述多个双镶嵌工艺操作之前，蚀刻所述蚀刻停止层直到到达所述互连层的顶表面。
13.根据权利要求1所述的方法，其中所述多个双镶嵌工艺操作包括：
在所述多个过孔区域和所述多个金属线区域中的每个区域中形成阻挡层；
在所述阻挡层中的每个阻挡层上形成种子层；以及
对所述种子层进行电镀。
14.一种用于处理衬底并且在集成电路中形成与金属线对准的过孔的处理系统，其中所述处理系统包括：
处理器；
存储器；以及
存储在所述存储器中并且包括指令的一个或多个应用，所述指令是由所述处理器可执行的以：
形成包括第一多个层的堆叠，其中所述第一多个层包括电介质层、加帽层、硬掩模层、第一膜层和第一光刻胶层，
图案化所述第一光刻胶层以提供金属线掩模，
基于经图案化的第一光刻胶层蚀刻所述硬掩模层，以在所述硬掩模层中形成金属线掩模，
灰化所述第一光刻胶层和所述第一膜层，
在所述硬掩模层上形成第二多个层，其中所述第二多个层包括第二膜层和第二光刻胶层，
图案化所述第二光刻胶层以形成过孔掩模，其中所述过孔掩模跨所述金属线掩模的相对侧延伸，
基于经图案化的第二光刻胶层蚀刻所述第二膜层和所述加帽层，
灰化所述第二光刻胶层和所述第二膜层，
基于所述硬掩模层的图案蚀刻所述电介质层和所述加帽层，以提供多个过孔区域和多个金属线区域，
蚀刻所述硬掩模层和所述加帽层，以及
执行多个双镶嵌工艺操作，以在所述多个过孔区域和所述多个金属线区域中形成所述过孔和所述金属线。
15.根据权利要求14所述的处理系统，其中所述第一多个层的形成包括：
形成所述电介质层；
在所述电介质层上形成所述加帽层；
在所述加帽层上形成所述硬掩模层；
在所述硬掩模层上形成所述第一膜层；以及
在所述第一膜层上形成所述第一光刻胶层。
16.根据权利要求14所述的处理系统，其中：
所述硬掩模层用作第一掩模层以掩蔽所述加帽层；并且
所述加帽层用作第二掩模层以掩蔽所述电介质层。
17.根据权利要求14所述的处理系统，其中所述第二多个层的形成包括：
在所述硬掩模层上形成所述第二膜层；以及
在所述第二膜层上形成所述第二光刻胶层。
18.根据权利要求14所述的处理系统，其中：
基于所述经图案化的第二光刻胶层对所述第二膜层和所述加帽层进行各向异性蚀刻；以及
基于所述硬掩模层的图案对所述电介质层和所述加帽层进行各向异性蚀刻。
19.根据权利要求14所述的处理系统，其中所述电介质层和所述加帽层的蚀刻包括：
基于所述硬掩模层的图案和所述加帽层的图案来蚀刻所述电介质层；
在蚀刻所述电介质层之后，基于所述硬掩模层的图案蚀刻所述加帽层；以及
在蚀刻所述加帽层之后，基于所述硬掩模层的图案和所述加帽层的图案来蚀刻所述电介质层。
20.根据权利要求14所述的处理系统，其中所述多个双镶嵌工艺操作包括：
在所述多个过孔区域和所述多个金属线区域中的每个区域中形成阻挡层；
在所述阻挡层中的每个阻挡层上形成种子层；以及
对所述种子层进行电镀。
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US11081387B2 (en) 2021-08-03
JP7168281B2 (ja) 2022-11-09
KR20190035595A (ko) 2019-04-03
US20200118868A1 (en) 2020-04-16
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