JP7145068B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
- Publication number
- JP7145068B2 JP7145068B2 JP2018248298A JP2018248298A JP7145068B2 JP 7145068 B2 JP7145068 B2 JP 7145068B2 JP 2018248298 A JP2018248298 A JP 2018248298A JP 2018248298 A JP2018248298 A JP 2018248298A JP 7145068 B2 JP7145068 B2 JP 7145068B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- fine
- wiring
- insulating layer
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
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- H10W70/65—
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
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- H10W70/05—
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- H10W70/611—
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- H10W70/635—
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- H10W70/685—
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- H10W90/00—
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- H10W99/00—
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
- H05K1/0227—Split or nearly split shielding or ground planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1178—Means for venting or for letting gases escape
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- H10W70/63—
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- H10W90/724—
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018248298A JP7145068B2 (ja) | 2018-12-28 | 2018-12-28 | 配線基板及びその製造方法 |
| US16/710,619 US10804210B2 (en) | 2018-12-28 | 2019-12-11 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018248298A JP7145068B2 (ja) | 2018-12-28 | 2018-12-28 | 配線基板及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2020107860A JP2020107860A (ja) | 2020-07-09 |
| JP2020107860A5 JP2020107860A5 (enExample) | 2021-12-16 |
| JP7145068B2 true JP7145068B2 (ja) | 2022-09-30 |
Family
ID=71124178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018248298A Active JP7145068B2 (ja) | 2018-12-28 | 2018-12-28 | 配線基板及びその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US10804210B2 (enExample) |
| JP (1) | JP7145068B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7589574B2 (ja) * | 2021-02-10 | 2024-11-26 | Toppanホールディングス株式会社 | 多層配線基板 |
| US11978699B2 (en) | 2021-08-19 | 2024-05-07 | Texas Instruments Incorporated | Electronic device multilevel package substrate for improved electromigration preformance |
| CN115995453A (zh) * | 2021-10-19 | 2023-04-21 | 群创光电股份有限公司 | 电子装置及电子装置的制造方法 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003332483A (ja) | 2002-05-16 | 2003-11-21 | Hitachi Ltd | 配線基板とそれを用いた電子装置 |
| JP2015162528A (ja) | 2014-02-27 | 2015-09-07 | 京セラサーキットソリューションズ株式会社 | 配線基板 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3293353A (en) * | 1964-03-30 | 1966-12-20 | Gen Electric | Shielded interconnecting wiring medium |
| US4061263A (en) * | 1976-09-22 | 1977-12-06 | International Telephone And Telegraph Corporation | Method of bonding a dielectric substrate to a metallic carrier in a printed circuit assembly |
| JP3260941B2 (ja) * | 1993-06-18 | 2002-02-25 | 株式会社日立製作所 | 多層配線基板および多層配線基板の製造方法 |
| US6106923A (en) * | 1997-05-20 | 2000-08-22 | Fujitsu Limited | Venting hole designs for multilayer conductor-dielectric structures |
| US6977345B2 (en) * | 2002-01-08 | 2005-12-20 | International Business Machines Corporation | Vents with signal image for signal return path |
| US6747216B2 (en) * | 2002-02-04 | 2004-06-08 | Intel Corporation | Power-ground plane partitioning and via connection to utilize channel/trenches for power delivery |
| US7659790B2 (en) * | 2006-08-22 | 2010-02-09 | Lecroy Corporation | High speed signal transmission line having reduced thickness regions |
| JP4916300B2 (ja) * | 2006-12-19 | 2012-04-11 | 新光電気工業株式会社 | 多層配線基板 |
| JP5931547B2 (ja) * | 2012-03-30 | 2016-06-08 | イビデン株式会社 | 配線板及びその製造方法 |
| JP6324876B2 (ja) * | 2014-07-16 | 2018-05-16 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
| JP2016051834A (ja) * | 2014-09-01 | 2016-04-11 | イビデン株式会社 | プリント配線基板およびその製造方法 |
-
2018
- 2018-12-28 JP JP2018248298A patent/JP7145068B2/ja active Active
-
2019
- 2019-12-11 US US16/710,619 patent/US10804210B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003332483A (ja) | 2002-05-16 | 2003-11-21 | Hitachi Ltd | 配線基板とそれを用いた電子装置 |
| JP2015162528A (ja) | 2014-02-27 | 2015-09-07 | 京セラサーキットソリューションズ株式会社 | 配線基板 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20200211971A1 (en) | 2020-07-02 |
| JP2020107860A (ja) | 2020-07-09 |
| US10804210B2 (en) | 2020-10-13 |
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