JP6958026B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6958026B2 JP6958026B2 JP2017129041A JP2017129041A JP6958026B2 JP 6958026 B2 JP6958026 B2 JP 6958026B2 JP 2017129041 A JP2017129041 A JP 2017129041A JP 2017129041 A JP2017129041 A JP 2017129041A JP 6958026 B2 JP6958026 B2 JP 6958026B2
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- circuit patterns
- semiconductor device
- protective film
- circuit
- front surface
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
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Description
本発明の一観点によれば、絶縁板と前記絶縁板のおもて面に形成された複数の回路パターンとを含む基板と、前記複数の回路パターンのおもて面の接合領域を露出して、平面視で、前記複数の回路パターンの少なくとも互いに対向する側部にそれぞれ形成された複数の保護膜と、前記複数の回路パターンの前記接合領域にはんだを介して接合された複数の構成部品と、を有し、前記複数の保護膜は、平面視で、前記複数の回路パターンのそれぞれの側部のうち、前記複数の回路パターンの少なくとも互いに対向する側部以外には形成されていない、半導体装置が提供される。
第1の実施の形態の半導体装置について、図1〜図3を用いて説明する。
第2の実施の形態では、第1の実施の形態の第1保護膜に加えて、第2保護膜を形成する場合について説明する。
第2の実施の形態の半導体装置10aでは、回路パターン12a〜12hのうち、隣接する回路パターンの対向する側面及び当該側面に沿ったおもて面の縁部にイオンマイグレーションによる腐食物の生成を抑制するために、第1保護膜及び第2保護膜を形成している。
11 絶縁板
12a,12b,12c,12d,12e,12f,12g,12h 回路パターン
12a1,12a2,12a7,12b1,12b2,12b3,12c1,12c2,12c3,12d1,12d2,12e1,12e2,12e3,12e4,12e11,12e12,12f1,12f2,12g1,12g2,12g3,12h1,12h2 第1保護膜
12a4,12b4,12c4,12d4,12h4,12e5 ボンディング領域
12a5,12a6,12a8,12e6,12e7,12e8,12e9,12e13,12e14 第2保護膜
12a10,12e10 第3保護膜
13 金属板
14 セラミック回路基板
15a,15b,15d 半導体素子
15c 電子部品
15a1,15b1,15d1,15c1,15c2,16a1,16b1,16c1,16d1,16e1,16f1,16g1 接合領域
16a,16b,16c,16d,16e,16f,16g コンタクト部品
17a,17b,17c,17d,17e ボンディングワイヤ
18a,18b,18c,18d,18e,18f,18g,18h,18i,18j,18k,18l はんだ
19a,19b,19c,19d,19e,19f,19g 外部接続端子
20 金属基板
21 ケース
21a 蓋部
21b 側壁部
Claims (9)
- 絶縁板と前記絶縁板のおもて面に形成された複数の回路パターンとを含む基板と、
前記複数の回路パターンのおもて面の接合領域を露出して、前記複数の回路パターンの少なくとも互いに対向する側部と共に前記側部に沿って、前記接合領域から離間して前記複数の回路パターンのおもて面の縁部にそれぞれ形成された複数の保護膜と、
前記複数の回路パターンの前記接合領域にはんだを介して接合された複数の構成部品と、
を有する半導体装置。 - 絶縁板と前記絶縁板のおもて面に形成された複数の回路パターンとを含む基板と、
前記複数の回路パターンのおもて面の接合領域を露出して、平面視で、前記複数の回路パターンの少なくとも互いに対向する側部にそれぞれ形成された複数の保護膜と、
前記複数の回路パターンの前記接合領域にはんだを介して接合された複数の構成部品と、
を有し、
前記複数の保護膜は、平面視で、前記複数の回路パターンのそれぞれの側部のうち、前記複数の回路パターンの少なくとも互いに対向する側部以外には形成されていない、
半導体装置。 - 前記複数の構成部品のいずれかが、前記複数の回路パターンのうち、隣接する回路パターンに跨って接合されている、
請求項1または2に記載の半導体装置。 - 前記複数の構成部品は、半導体素子またはコンタクト部品の少なくともいずれか一方である、
請求項1または2に記載の半導体装置。 - 前記複数の構成部品は、電子部品である、
請求項3に記載の半導体装置。 - 前記複数の回路パターンは、銅または銅合金により構成されている、
請求項1または2に記載の半導体装置。 - 前記複数の保護膜は、ニッケルまたはニッケル合金により構成されている、
請求項1または2に記載の半導体装置。 - 前記はんだは、錫−銀−銅を含む合金、錫−亜鉛−ビスマスを含む合金、錫−銅を含む合金、または錫−銀−インジウム−ビスマスを含む合金のうち、少なくともいずれかの合金を主成分とする鉛フリーはんだである、
請求項1または2に記載の半導体装置。 - 前記はんだは、ニッケル、ゲルマニウム、コバルトまたはシリコンが添加されている、
請求項8に記載の半導体装置。
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CN201810165948.0A CN109216286B (zh) | 2017-06-30 | 2018-02-28 | 半导体装置 |
US15/909,963 US10699994B2 (en) | 2017-06-30 | 2018-03-01 | Semiconductor device having bonding regions exposed through protective films provided on circuit patterns onto which components are soldered |
DE102018204921.1A DE102018204921A1 (de) | 2017-06-30 | 2018-03-29 | Halbleitervorrichtung |
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US8004075B2 (en) * | 2006-04-25 | 2011-08-23 | Hitachi, Ltd. | Semiconductor power module including epoxy resin coating |
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