JP6878930B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6878930B2 JP6878930B2 JP2017021333A JP2017021333A JP6878930B2 JP 6878930 B2 JP6878930 B2 JP 6878930B2 JP 2017021333 A JP2017021333 A JP 2017021333A JP 2017021333 A JP2017021333 A JP 2017021333A JP 6878930 B2 JP6878930 B2 JP 6878930B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- flat surface
- film
- solder
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 96
- 229910000679 solder Inorganic materials 0.000 claims description 38
- 239000002184 metal Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 230000002265 prevention Effects 0.000 claims description 28
- 239000011347 resin Substances 0.000 claims description 20
- 229920005989 resin Polymers 0.000 claims description 20
- 229910044991 metal oxide Inorganic materials 0.000 claims description 18
- 150000004706 metal oxides Chemical class 0.000 claims description 18
- 239000003963 antioxidant agent Substances 0.000 claims description 13
- 230000003078 antioxidant effect Effects 0.000 claims description 13
- 238000000034 method Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000003754 machining Methods 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Die Bonding (AREA)
Description
3:半導体チップ
3a、3b:平坦面
3c:側面
4:第1金属板
5:金属スペーサ
6:第2金属板
7、8、9、107:ハンダ
10:樹脂パッケージ
12:ゲート端子
13:金属ワイヤ
21:酸化防止膜
22:金属酸化膜(接合防止膜)
22a−22f:接合防止膜
31:シリコン基板
32:コレクタ電極
40:クラック
107:ハンダ
Claims (4)
- 平坦面の全面に電極が設けられている半導体チップと、
前記平坦面にハンダを介して接合されている金属板と、
前記半導体チップと、前記半導体チップと前記金属板との接合部分をモールドしている樹脂パッケージと、
を備えており、
前記平坦面の縁に沿って前記電極の上に前記ハンダと接合しない接合防止膜が設けられている、半導体装置。 - 前記接合防止膜は、前記電極の表面が酸化した金属酸化膜である、請求項1に記載の半導体装置。
- 前記接合防止膜は樹脂製であり、
前記平坦面を平面視したときに前記接合防止膜の内側に別の接合防止膜が設けられており、
前記別の接合防止膜は、前記電極の表面が酸化した金属酸化膜である、
請求項1に記載の半導体装置。 - 前記平坦面を平面視したときに前記接合防止膜の内側に酸化防止膜が設けられている、請求項1から3のいずれか1項に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017021333A JP6878930B2 (ja) | 2017-02-08 | 2017-02-08 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017021333A JP6878930B2 (ja) | 2017-02-08 | 2017-02-08 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018129390A JP2018129390A (ja) | 2018-08-16 |
JP6878930B2 true JP6878930B2 (ja) | 2021-06-02 |
Family
ID=63174364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017021333A Active JP6878930B2 (ja) | 2017-02-08 | 2017-02-08 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP6878930B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022059288A1 (ja) * | 2020-09-18 | 2022-03-24 | 住友電気工業株式会社 | 半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5132358Y1 (ja) * | 1969-05-08 | 1976-08-12 | ||
JP4329187B2 (ja) * | 1999-10-29 | 2009-09-09 | 富士電機デバイステクノロジー株式会社 | 半導体素子 |
JP4891556B2 (ja) * | 2005-03-24 | 2012-03-07 | 株式会社東芝 | 半導体装置の製造方法 |
JP5018013B2 (ja) * | 2006-10-25 | 2012-09-05 | 富士電機株式会社 | 樹脂封止半導体装置 |
JP5720287B2 (ja) * | 2011-02-14 | 2015-05-20 | トヨタ自動車株式会社 | 半導体装置 |
JP6028810B2 (ja) * | 2012-11-20 | 2016-11-24 | トヨタ自動車株式会社 | 半導体装置 |
JP6578900B2 (ja) * | 2014-12-10 | 2019-09-25 | 株式会社デンソー | 半導体装置及びその製造方法 |
-
2017
- 2017-02-08 JP JP2017021333A patent/JP6878930B2/ja active Active
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Publication number | Publication date |
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JP2018129390A (ja) | 2018-08-16 |
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