JP6873855B2 - Power factor improvement circuit and control method of power factor improvement circuit - Google Patents

Description

The present invention relates to a power factor improving circuit and a method for controlling the power factor improving circuit.

Conventionally, there is an interleaved power factor correction circuit (see, for example, Patent Document 1). This conventional power factor improving circuit includes a master arm circuit (which may be referred to as a first arm circuit), a slave arm circuit (which may be referred to as a second arm circuit), and a polarity switching arm circuit. , Equipped with. In this conventional power factor improving circuit, since the currents of the two inductors are out of phase, the current of one inductor flows in the direction of canceling the current of the other inductor. Therefore, the ripple current of the input capacitor and the output capacitor can be reduced. However, in this conventional power factor improving circuit, ZVS (Zero Volt Switching) operation is difficult.

Japanese Unexamined Patent Publication No. 2015-23606

An object of the present invention is to provide a power factor improving circuit capable of ZVS operation and a method for controlling the power factor improving circuit.

The power factor improving circuit of one aspect of the present invention is
A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor connected between the first input terminal and the first node, a first switch element connected between the first node and the first output terminal, and One or more first arm circuits having at least a second switch element connected between the first node and the second output terminal.
A third switch element connected between the second input terminal and the first output terminal, and a fourth connected between the second input terminal and the second output terminal. Polarity switching arm having at least the switch element of
A second inductor connected between the first input terminal and the second node, a fifth switch element connected between the second node and the first output terminal, and a fifth switch element. One or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal.
A current storage inductor connected between the first node and the second node,
A control unit that controls the switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage.
With
The control unit
The input voltage input to the first input terminal is compared with the threshold value, and when the input voltage is larger than the threshold value, a position is placed between the first arm circuit and the second arm circuit. Phase difference control for providing a phase difference is performed, and when the input voltage is equal to or lower than the threshold value, non-phase difference control is performed without providing a phase difference between the first arm circuit and the second arm circuit.
It is characterized by that.

In the power factor improvement circuit
The threshold is one half of the output voltage between the first output terminal and the second output terminal.
It is characterized by that.

In the power factor improvement circuit
The control unit
When the phase difference control is performed, the phase difference is set to a predetermined time.
It is characterized by that.

In the power factor improvement circuit
The control unit
When performing the phase difference control, the larger the input voltage is, the larger the phase difference is.
It is characterized by that.

In the power factor improvement circuit
The control unit
When the phase difference control is performed, the phase difference is set to a time directly proportional to the input voltage.
It is characterized by that.

で計算する、
ことを特徴とする。
ｔ_ｄｉｆｆは位相差時間、Ｖ_ｉｎは入力電圧、Ｖ_ｏｕｔは出力電圧、Ｃは第１から第６までのスイッチ素子の寄生容量、Ｌ_Ｒは第１及び第２インダクタのインダクタンスである。 In the power factor improvement circuit
The control unit
When performing the phase difference control, the phase difference is

Calculate with,
It is characterized by that.
t _diff phase difference _time, the _{V in} the input _{voltage, V out} is the output voltage, C is the parasitic capacitance, _{L R} of the switch element from the first to the sixth is the inductance of the first and second inductors.

The method for controlling the power factor improving circuit according to one aspect of the present invention is as follows.
A pair of first and second input terminals to which an AC voltage is input, a pair of first and second output terminals to output a DC voltage, the first output terminal, and the first output terminal. An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, the first node and the first output terminal. One or more first arm circuits having at least a first switch element connected to and a second switch element connected between the first node and the second output terminal. And a third switch element connected between the second input terminal and the first output terminal, and connected between the second input terminal and the second output terminal. A polarity switching arm having at least a fourth switch element, a second inductor connected between the first input terminal and the second node, the second node and the first output terminal. A fifth switch element connected between them, and one or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal. The current storage inductor connected between the first node and the second node, and the switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage. It is a control method of a force factor improving circuit including a control unit for controlling.
The control unit compares the input voltage input to the first input terminal with the threshold value, and when the input voltage is larger than the threshold value, the first arm circuit and the second arm circuit are used. When the input voltage is equal to or less than the threshold value, the phase difference is controlled so as to provide a phase difference between the first arm circuit and the second arm circuit. Perform phase difference control,
It is characterized by that.

The power factor improving circuit of one aspect of the present invention and the control method of the power factor improving circuit have an effect that ZVS operation can be enabled.

FIG. 1 is a diagram showing a circuit configuration of a power factor improving circuit of a comparative example. FIG. 2 is a diagram showing an example of an operation waveform of the power factor improving circuit of the comparative example. FIG. 3 is a diagram showing a circuit configuration of the power factor improving circuit according to the first embodiment. FIG. 4 is a diagram showing an example of an operation waveform of the power factor improving circuit according to the first embodiment. FIG. 5 is a diagram showing a circuit configuration of the power factor improving circuit of the second embodiment.

Hereinafter, embodiments of the power factor improving circuit of the present invention will be described in detail with reference to the drawings. The present invention is not limited to this embodiment.

(First Embodiment)
Hereinafter, the first embodiment will be described, but for the sake of easy understanding of the first embodiment, a comparative example will be described first.
[Comparison example]
FIG. 1 is a diagram showing a circuit configuration of a power factor improving circuit of a comparative example. The power factor improving circuit 1 improves the power factor by an interleave method. Power factor correction circuit 1, AC (e.g., 50 Hz or 60Hz) supplied with the input voltage _{V in} from the power supply 2 and outputs an output voltage _{V out} is higher than the input voltage _{V in} direct current to the load 4, the booster circuit Is. In the comparative example, the effective value of the input voltage _{V in} is assumed to be 200V, the target voltage of the output voltage _{V out} is assumed to be 400V. In other words, the power factor correction circuit 1 is supplied with the input voltage _{V in} effective value 200V, and outputs an output voltage _{V out} of 400V.

Power factor correction circuit 1 includes a first input terminal 11 and the second input terminal 12 of the input voltage V _in is supplied. Power factor correction circuit 1 includes a first voltage detector 13 for detecting an input voltage V _in. The first voltage detector 13 is connected between the first input terminal 11 and the second input terminal 12.

The power factor improving circuit 1 includes a first output terminal 14 and a second output terminal 15 that output an _{output voltage V out.} The power factor improving circuit 1 includes an output capacitor C _{1 for smoothing the output voltage V out} . The output capacitor C ₁ is connected between the first output terminal 14 and the second output terminal 15. Further, the power factor improving circuit 1 includes a second voltage detector 16 that detects an _{output voltage V out.} The second voltage detector 16 is connected between the first output terminal 14 and the second output terminal 15.

A load 4 is connected between the first output terminal 14 and the second output terminal 15. The load 4 is exemplified by, but is not limited to, a DC-DC converter that converts an _{output voltage V out to a different DC voltage.}

Power factor correction circuit 1 includes a first inductor L _1. The first end of the inductor L ₁ is connected to a first input terminal 11. The first end of the inductor L ₁ is connected to the first node N _1. Further, the power factor improving circuit 1 includes a second inductor L ₂ . One end of the second inductor L ₂ is connected to the first input terminal 11. The other end of the second inductor L ₂ is connected to the second node N _2.

Power factor correction circuit 1 includes first and second switching elements (for example, N-channel field effect transistor (MOSFET)) the _{Q 1} and _{Q 2.} The first node N _1, the first source of the switch element Q ₁ - through the drain path, and is connected to the first output terminal 14. Further, the first node N ₁ is connected to the second output terminal 15 via the drain-source path of the second switch element Q _2.

The first inductor L ₁ and the first and second switch elements Q ₁ and Q ₂ constitute the first arm circuit 17.

The first arm circuit 17 may be referred to as a master arm or a slave arm. Further, in the present embodiment, the power factor improving circuit 1 includes one first arm circuit 17, but the present invention is not limited to this. Power factor correction circuit 1 is connected in parallel, is controlled by the first and second gate pulse signals P ₁ and P _2, it may include two or more of the first arm circuit 17.

Further, the first arm circuit 17 has included a first switching element to Q ₁ high side one is not limited to this. The first arm circuit 17, the source - drain paths connected in parallel, is controlled by the first gate pulse signals P _1, may contain two or more switching elements of the high side. Further, the first arm circuit 17 is includes a second switching element Q ₂ of one of the low side, but is not limited thereto. The first arm circuit 17, the source - drain paths connected in parallel and controlled by a second gate pulse signals P _2, may include two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Power factor correction circuit 1 includes a third and fourth switching elements _{Q 3} and _{Q 4.} The second input terminal 12, the source of the third switching element Q ₃ - via the drain path is connected to the first output terminal 14. The second input terminal 12, the drain of the fourth switching element Q ₄ - via the source path is connected to the second output terminal 15.

Third and fourth switching elements _{Q 3} and _{Q 4} constitute a polarity switching arm circuit 18.

Polarity switching arm circuit 18 has included one third switching element Q ₃ of the high side, but is not limited thereto. Polarity switching arm circuit 18, the source - drain paths connected in parallel, is controlled by the third gate pulse signals P _3, may contain two or more switching elements of the high side. The polarity switching arm circuit 18 has included a fourth switching element Q ₄ of one of the low side, but is not limited thereto. Polarity switching arm circuit 18, the source - drain paths connected in parallel and controlled by a fourth gate pulse signal P _4, may contain two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Power factor correction circuit 1 includes a switching element _{Q 5} and _{Q 6} of the fifth and sixth. The second node N ₂ is connected to the first output terminal 14 via the source-drain path of the fifth switch element Q _5. The second node N _2, the drain of the switching element Q ₆ of the sixth - through the source path is connected to the second output terminal 15.

The second inductor _{L 2,} and the switching elements _{Q 5} and _{Q 6} of the fifth and sixth constitute the second arm circuit 19.

The second arm circuit 19 may be referred to as a slave arm or a master arm. Further, in the present embodiment, the power factor improving circuit 1 includes one second arm circuit 19, but the present invention is not limited to this. Power factor correction circuit 1 is connected in parallel, it is controlled by the gate pulse signal P ₅ and P ₆ of the fifth and sixth, may include two or more of the second arm circuit 19. The number of the second arm circuits 19 and the number of the first arm circuits 17 are preferably the same.

The second arm circuit 19 has included switching element Q ₅ of one fifth high side, but is not limited thereto. The second arm circuit 19, the source - drain paths connected in parallel, is controlled by the gate pulse signal P ₅ of the fifth, it may contain two or more switching elements of the high side. The second arm circuit 19 has included switching element Q ₆ of the sixth one of the low side, but is not limited thereto. The second arm circuit 19, the source - drain paths connected in parallel, is controlled by the gate pulse signal P ₆ of the sixth, it may contain two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Input current _{I in} is input to the first input terminal 11, a current IL ₁ flowing through the first arm circuit 17, a current IL ₂ flowing in the second arm circuit 19 is the sum of.

In this embodiment, although the first switching element Q ₁ until the switch element Q ₆ of the sixth was to be a N-channel MOSFET, but it is not limited thereto. From the first switching element _{Q 1} until the switch element _{Q 6} of the sixth, silicon power devices, GaN power devices, SiC power devices, IGBT (Insulated Gate Bipolar Transistor) or the like.

From the first switching element Q ₁ until the switch element Q ₆ of the sixth, from the first parasitic diode (body diode) D ₁ to the parasitic diode D ₆ of the sixth, respectively Yes. The parasitic diode is a pn junction between the back gate of the MOSFET and the source and drain. The first parasitic diode D ₁ to the sixth parasitic diode D ₆ are freewheels for escaping the transient counter electromotive force when the first switch element Q ₁ to the sixth switch element Q _{6 are off.} It can be used as a diode.

Power factor correction circuit 1 has a current storage inductor L _3. One end of the current storage inductor L ₃ is connected to _{the first node N 1.} The other end of the current storage inductor L ₃ is connected to _{the second node N 2.}

It is preferable that the cross-sectional area of the current storage inductor L ₃ is set smaller than the cross- _{sectional area of the first inductor L 1 and} the cross-sectional area of the second inductor L _2.

The average value of the _{current IL 3} flowing through the current storage inductor L ₃ is smaller than the average value of the current IL _{1 flowing through the first inductor L 1} and the average value of the current IL _{2 flowing through the second inductor L 2.} It is preferable that it is set to.

It is preferable that the inductance of the current storage inductor L ₃ is set to be larger than _{the inductance of the first inductor L 1 and} the inductance of the second inductor L _2.

The power factor improving circuit 1 includes a control unit 50. The control unit 50 can be realized by using a CPU (Central Processing Unit) and a program.

Control unit 50, depending on the polarity of the input voltage V _in, the gate of the first switching element Q ₁ until the switch element Q ₆ of the sixth - by controlling the voltage between the source, the first switching element Q controlling the switching operation from _one to the switch element Q ₆ of the sixth. Control unit 50, PWM (Pulse Width Modulation) is a signal, from the first gate pulse signals _{P 1} to the gate pulse signal _{P 6} of the sixth switching element _{Q 6} of the first sixth from the switch element _{Q 1} Output to each of the gates up to. Note that the first gate pulse signals P ₁ to the gate pulse signal P ₆ of the sixth, the dead time t _d is set. The dead time t _d is exemplified, but is not limited to about 1 ns to 10 ns.

Control unit 50, the output voltage _{V out} is so that the target voltage (400V), to control the first switching element _{Q 1} until the switch element _{Q 6} of the sixth.

Control unit 50, the input voltage V _in detected by the first voltage detector 13, the output voltage V _out which is detected by the second voltage detector 16, based on, first, second, the phase difference between the fifth and sixth gate pulse signal _P 1 _of, P 2, _{P 5} and the frequency of the _{P 6} (switching frequency), the on time _{T on,} the first arm circuit 17 and the second arm circuit 19 Calculate the time t _diff. The control unit 50 has the first, second, fifth, and sixth gate pulse signals P ₁ , P ₂ , and P ₅ based on the calculated frequency, the on-time _Ton, and the phase difference time t _diff. and _{P 6,} first, the second, switching element to _Q 1 fifth and _6, Q 2, the gate of _{Q 5} and _{Q 6,} respectively output.

The operation of the control unit 50 will be described.

Control unit 50, the polarity of the input voltage V _in the case of the positive phase is on the third switching element Q ₃ off and and the fourth of the switching element Q ₄ of polarity switching arm circuit 18.

Then, the control unit 50, the third switching element Q ₃ off to state and turned on the fourth switch element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / while controlling to switch off, and controls so that the switching element Q ₅ and Q ₆ of the fifth and sixth switches the complementarily turned on / off.

For example, the control unit 50, when the input voltage _{V in} is positive-phase, second, fourth and switching element _Q 2, _{Q 4} and _{Q 6} was turned on while the first sixth, third and fifth from a first state in which turning off the switch element Q _1, Q ₃ and Q ₅ of, for controlling the second switching element Q ₂ in the second state in which turned off and and the first switching element Q _1.

Further, the control unit 50, after controlling the second state, the second state is controlled to the third state of turning off the switch element Q ₆ of the sixth. Then, the control unit 50, after controlling the third state, the third state is controlled to a fourth state in which turns on the switch element Q ₅ of the fifth.

The control unit 50, after controlling the fourth state, the fourth state is controlled to a fifth state in which off the first switching element Q _1. Then, the control unit 50, after controlling the fifth state, the fifth state, and controls the sixth state of that on the second switching element Q _2.

Further, after controlling to the sixth state, the control unit 50 controls from the sixth state to the seventh state in which the _{fifth switch element Q5 is turned off.} Then, after controlling to the seventh state, the control unit 50 controls from the seventh state to the eighth state in which the _{sixth switch element Q6 is turned on.}

Further, after controlling to the eighth state, the control unit 50 controls from the eighth state to the ninth state in which the _{second switch element Q2 is turned off.} Then, after controlling to the ninth state, the control unit 50 controls from the ninth state to the tenth state in which the _{first switch element Q1 is turned on.}

By the above control, when _{the polarity of the input voltage Vin is in} the positive phase, the currents IL ₁ and IL ₂ flow to the second input terminal 12 via the fourth switch element Q _4. ..

On the other hand, the control unit 50, when the polarity of the input voltage V _in is reversed phase, turns off the third switching element Q ₃ ON and and fourth switching elements Q ₄ of polarity switching arm circuit 18 ..

Then, the control unit 50, the third switching element Q ₃ at ON and state and turning off the fourth switching element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / while controlling to switch off, and controls so that the switching element Q ₅ and Q ₆ of the fifth and sixth switches the complementarily turned on / off.

This control, when the polarity of the input voltage V _in the reverse phase, the current IL ₁ and IL ₂ is allowed to flow to the first input terminal 11 via a third switching element Q _3.

The polarity of the input voltage V _in when it is reversed phase, while controlling to switch complementarily turned on / off first and second switching elements Q ₁ and Q _2, the fifth and sixth specific operations for controlling to switch complementarily turned on / off the switch element Q ₅ and Q ₆ from a first state when the input voltage V _in the above are positive-phase up to the 10 state Similar to control.

FIG. 2 is a diagram showing an example of an operation waveform of the power factor improving circuit of the comparative example. FIG. 2 is a diagram showing an example of an operation waveform of the power factor improving circuit 1 when the polarity of the input voltage Vin is _{in the positive phase.}

Control unit 50, when the input voltage _{V in} is positive-phase, second, fourth and sixth switching element _Q 2, _{Q 4} and _{Q 6} turned on and the first to the third and fifth switch controlling the elements _Q 1, _{Q 3} and _{Q 5} in a first state in which off.

Next, the control unit 50, at the timing _{t 1,} turns off the second switching element _{Q 2.} Next, the control unit 50 at a timing t ₂ after elapse of the dead time t _d from the timing t _1, and controls the second state in which the on-first switching element Q _1. At this time, the drain of the second switching element _{Q 2} - source voltage Vdsq ₂ is the output voltage _{V out} corresponding.

Next, the control unit 50 at a timing t _3, from the second state to control the third state of turning off the switch element Q ₆ of the sixth. At this time, the drain of the switching element _{Q 6} of the sixth - source voltage Vdsq ₆ is the output voltage _{V out} corresponding.

Thus, the current storage inductor _{L 3,} a period from the timing _{t 2} to time _{t 3,} the output voltage _{V out} corresponding voltage VL ₃ is applied, the current IL ₃ stored in the current storage inductor _{L 3} To. At this time, the current storage inductor L ₃ discharges the parasitic capacitance of the parasitic diode D ₅ , and the drain-source voltage of _{the fifth switch element Q 5 becomes 0 V.}

This allows ZVS operation of the fifth switching element _{Q 5} is.

Next, the control unit 50 at a timing t ₄ after the dead time t _d has elapsed from the timing t _3, and controls the fourth state in which turns on the switch element Q ₅ of the fifth. At this time, since the current storage inductor L ₃ are short-circuited via the switch element Q ₅ of the first switching element Q ₁ and 5, the current IL ₃ of the current storage inductor L ₃ is maintained.

The period from timing t ₂ to timing t _{4 is the phase difference time t diff} between the first arm circuit 17 and the second arm circuit 19.

Next, the control unit 50, at the timing t _5, the fourth state is controlled to a fifth state in which off the first switching element Q _1. In this case, the current storage inductor _{L 3} and discharging the parasitic capacitance of the parasitic diode _{D 2,} the drain of the second switching element _{Q 2} - source voltage Vdsq ₂ becomes 0V.

This allows the second ZVS operation of the switching element _{Q 2} is.

Period from the timing _{t 2} to time _{t 5} is the on-time _{T on.}

Next, the control unit 50, at the timing t ₆ after the dead time t _d has elapsed from the timing t _5, and controls the sixth state of that on the second switching element Q _2.

Next, the control unit 50, at the timing t _7, the sixth state of controls to the seventh state of turning off the switching element Q ₅ of the fifth. Thus, the current storage inductor L _3, a period from the timing t ₆ to the time t _7, the output voltage V _out corresponding voltage of the third state and the reverse direction is applied, the current storage inductor L ₃ The current IL ₃ is accumulated. In this case, the current storage inductor _{L 3} and discharging the parasitic capacitance of the parasitic diode _{D 6,} the drain of the switching element _{Q 6} of the sixth - source voltage Vdsq ₆ becomes 0V.

This allows ZVS operation of the switching element _{Q 6} of the sixth.

Next, the control unit 50 at a timing t ₈ of the dead time t _d after the timing t _7, the seventh state, to control the state of the 8 turns on the switch element Q ₆ of the sixth. At this time, the current storage inductor L ₃ is short-circuited via the second switch element Q ₂ and the sixth switch element Q ₆ , and the current of the current storage inductor L ₃ is held.

Next, the control unit 50 at a timing t _9, the state of the 8 controls the ninth state of turning off the second switching element Q _2. In this case, the current storage inductor _{L 3} and discharging the parasitic capacitance of the parasitic diode _{D 1,} the drain of the first switching element _{Q 1} - source voltage Vdsq ₁ becomes 0V.

This allows the first ZVS operation of the switch element _{Q 1} is.

Next, the control unit 50, the dead time _{t d} has elapsed timing _{t 10} after the timing _{t 9,} the ninth state is controlled to a tenth state of the turn on the first switching element _{Q 1.}

The control unit 50 subsequently executes the same control.

Note that the second gate pulse signals P ₂ phases for controlling the second switching element Q _2, the phase and the sixth switch element Q ₆ gate pulse signal P ₆ of the sixth to control the , The phase difference time is shifted by _{t diff.} As well as, the first gate pulse signal P ₁ of the phase to control the first switching element Q _1, the fifth gate pulse signal P ₅ for controlling the switching element Q ₅ of the fifth phase Is deviated by the phase difference time t _diff.

Power factor correction circuit 1 includes a first node N ₁ and is connected between the second node N _2, the current storage inductor L _3. When the current storage diode L ₃ is off, the first switch element Q ₁ , the second switch element Q ₂ , the fifth switch element Q ₅ , or the sixth switch element Q ₆ is off. Discharge the parasitic capacitance of the parasitic diode D of Q. Therefore, the ZVS operation of the first switch element Q ₁ , the second switch element Q ₂ , the fifth switch element Q ₅ , and the sixth switch element Q _{6 becomes possible.}

However, in the power factor improving circuit 1, the current IL ₃ flows through the _{current storage inductor L 3.} The current IL ₃ causes conduction loss of the current storage inductor L ₃ and each switch element Q, and iron loss of the _{current storage inductor L 3.} It is desirable to suppress these losses.

[First Embodiment]
The power factor improving circuit of the first embodiment includes phase difference control and phase difference control in order to suppress _{conduction loss of the current storage inductor L 3} and each switch element Q and _{iron loss of the current storage inductor L 3.} The non-phase difference control and the non-phase difference control are switched and executed. The phase difference control is a control for providing a phase difference between the first arm circuit 17 and the second arm circuit 19. The non-phase difference control is a control in which a phase difference is not provided between the first arm circuit 17 and the second arm circuit 19.

FIG. 3 is a diagram showing a circuit configuration of the power factor improving circuit according to the first embodiment. The same components as those in the comparative example are designated by the same reference numerals, and the description thereof will be omitted.

The power factor improving circuit 1A of the first embodiment includes a control unit 50A instead of the control unit 50 of the comparative example. The control unit 50A includes a threshold storage unit 51, a determination unit 52, a phase difference calculation unit 53, and a drive unit 54.

_{The threshold storage unit 51 stores the voltage threshold Vth} for determining whether to perform phase difference control or non-phase difference control. The threshold value _Vth may be rewritable via wired communication or wireless communication. In the present embodiment, V _th = 1/2 · V _out , but the present invention is not limited to this. V _th ≤ 1/2 · V _out may be used.

Referring again to FIG. 3, the determination unit 52 compares the input voltage _{V in,} and the threshold _{V th,} the. Determining unit 52, when the input voltage V _in is greater than the threshold V _th is for causing the phase difference controlling the drive unit 54, it outputs a determination signals S ₁ of low level to the drive unit 54. On the other hand, when the input current I _{in is equal to or less than the selected threshold value, the determination unit 52 outputs a high-level determination signal S 1} to the drive unit 54 for causing the drive unit 54 to perform non-phase difference control.

Phase difference calculation unit 53, when the determination signal _{S 1} is at a low level, i.e., when performing the phase difference control based on the input voltage _{V in} and the output voltage _{V out,} and calculates the phase difference time _{t diff,} Output to the drive unit 54.

Phase difference calculation unit 53, the higher the input voltage V _in, for power factor improvement, it is preferable to increase the phase difference time t _diff. The phase difference calculation unit 53, for power factor correction, the phase difference time t _diff, it is preferable that the time which is directly proportional to the input voltage V _in.

For example, it is preferable that the phase difference calculation unit 53 calculates the phase difference time t _{diff by the following equation (1).} However, the present invention is not limited to this.

In the formula (1), C is a parasitic capacitance _{from the first} parasitic diode D 1 to the sixth parasitic diode D _6. L _R is the first inductor _{L 1} and the second inductance of the inductor _{L 2.}

Drive unit 54, the both cases of the phase difference controlling and non-phase difference control, so that the output voltage V _out is equal to the target voltage (400V), the switch element of the first sixth from the switch element Q ₁ Q ₆ Control up to.

Driving unit 54, in either case of the phase difference controlling and non-phase difference control, the input voltage V _in, the output voltage V _out, on the basis of, first, second, fifth and sixth gate pulse calculating a signal _{P 1, P 2, P 5} and the frequency of the _{P 6} (switching frequency), the on time _{T on,} the. Driving unit 54, the calculated frequency, and the on-time T _on, and the phase difference time t _diff calculated by the phase difference calculation unit 53, on the basis of, first, second, fifth and sixth gate pulse the signals _{P 1,} P 2, _{P 5} and _{P 6,} first, the second, switching element to _Q 1 fifth and _6, Q 2, the gate of _{Q 5} and _{Q 6,} respectively output.

Since the control operation of the phase difference control of the control unit 50A is the same as that of the control unit 50 of the comparative example, the description thereof will be omitted.

The control operation of the non-phase difference control of the control unit 50A will be described.

The first arm circuit 17 and the second arm circuit 19 have a circuit configuration similar to that of the boost chopper circuit. Therefore, the power factor improving circuit 1 operates in the same manner as the boost chopper circuit in the case of non-phase difference control.

Specifically, the control unit 50A, when the polarity of the input voltage V _in is positive phase, the third switching element Q ₃ off and and the fourth the switch element polarity switching arm circuit 18 Q ₄ Turn on.

Then, the control unit 50A, in the third state in which the off-switching element Q ₃ and turned on the fourth switch element Q _4, the switching elements Q ₁ and Q ₅ of the first and fifth, second and third a switching element Q ₂ and Q ₆ of 6, is controlled to switch complementarily turned on / off.

For example, the control unit 50A, when the input voltage _{V in} is positive-phase, second, fourth and switching element _Q 2, _{Q 4} and _{Q 6} was turned on while the first sixth, third and fifth switching elements _Q 1, _{Q 3} and _{Q 5} from a first state in which off, second and sixth switching elements _{Q 1} and _{Q 5} the switching element _{Q 2} and _{Q 6} off to and the first and fifth Is controlled to the second state in which is turned on.

Further, the control unit 50A, after controlling the second state, the second state is controlled to the third state of turning off the switch element Q ₁ and Q ₅ of the first and fifth.

Then, the control unit 50A, after controlling the third state, the third state is controlled to a fourth state in which turning on the switch element Q ₂ and Q ₆ of the second and sixth.

The control unit 50A, after controlling the fourth state, the fourth state is controlled to a fifth state in which turning off the second and switching element Q ₂ and Q ₆ of the sixth.

By the control described above, when the polarity of the input voltage V _in is positive phase, the current IL ₁ and current IL ₂ is, via the fourth switching element Q _4, and flows to the second input terminal 12 Become.

On the other hand, the control unit 50A, when the polarity of the input voltage V _in is reversed phase, turns off the third switching element Q ₃ ON and and fourth switching elements Q ₄ of polarity switching arm circuit 18 ..

Then, the control unit 50, while the third switching element Q ₃ is turned on and off the fourth switching element Q _4, the switching elements Q ₁ and Q ₅ of the first and fifth, second and third a switching element Q ₂ and Q ₆ of 6, is controlled to switch complementarily turned on / off.

This control, when the polarity of the input voltage V _in the reverse phase, the current IL ₁ and current IL ₂ is allowed to flow to the first input terminal 11 via a third switching element Q _3.

Incidentally, when the polarity of the input voltage V _in is reversed phase, a switching element Q ₁ and Q ₅ of the first and fifth, the second and the switch element Q ₂ and Q ₆ of the sixth, complementarily to specific operations for controlling to switch on / off is similar to the control from the first state when the input voltage V _in the above is the positive phase to the fifth state.

In the first arm circuit 17 of the power factor improvement circuit 1A, the parasitic capacitance C of _{the first inductor L 1} and the parasitic diode D ₂ during the period when the first _{switch element Q 1} and the second switch element Q _{2 are off.} The LC series circuit composed of and vibrates freely. During free oscillation, first center voltage of the node _{N 1} is _{V in,} the voltage amplitude is _(V out _{-V in).} The second arm circuit 19 is the same as the first arm circuit 17.

Consider the period during which V _in ≤ 1/2 · V _out. In this period, the drain of the second switching element Q ₂ - source voltage Vdsq ₂ is a reverse phase side of the free oscillation voltage, leading to 0V. Therefore, the power factor improving circuit 1A enables the ZVS operation of the _second switch element Q2 regardless of the current IL _{3 of the current storage inductor L 3.} Further, the drain-source voltage VdsQ ₁ of the first switch element Q ₁ reaches 0 V on the positive phase side of the free vibration voltage. Therefore, the power factor improving circuit 1A enables the ZVS operation of the _first switch element Q1 regardless of the current IL _{3 of the current storage inductor L 3.} The second arm circuit 19 is the same as the first arm circuit 17.

Therefore, the control unit _50A, in the period a _{V in ≦ 1/2 · V} out, the first arm circuit 17 the phase difference time _{t diff} between the second arm circuit 19 to 0 ns. That is, the control unit _50A, in the period _{V in ≦ 1/2 · V} out, the first arm circuit 17 is not provided with the phase difference between the second arm circuit 19 performs non-phase difference control ..

If 0ns phase difference time t _diff between the first arm circuit 17 and the second arm circuit 19, the potential across the current storage inductor L ₃ are the same. _{That is, the voltage VL 3} between both ends of the current storage inductor L ₃ becomes 0 V. Therefore, the current IL ₃ does not flow through the current storage inductor L _3. As a result, the power factor improving circuit 1A _{can suppress the conduction loss of the current storage inductor L 3} and each switch element Q, and the iron loss of the _{current storage inductor L 3.}

Consider the period during which V _in > 1/2 · V _out. In this period, the drain of the second switching element Q ₂ - source voltage Vdsq ₂ is a reverse phase side of the free oscillation voltage does not lead to 0V. The second arm circuit 19 is the same as the first arm circuit 17.

Therefore, the control unit _50A, in the V in> period 1/2 _{· V out,} to 0ns greater than the phase difference time _{t diff} between the first arm circuit 17 and the second arm circuit 19 .. That is, the control unit _50A, in the V in> period of 1/2 _{· V out,} perform the phase difference control. As a result, when the current storage diode L ₃ is turned off when the first switch element Q ₁ , the second switch element Q ₂ , the fifth switch element Q ₅ , or the sixth switch element Q ₆ is off, these Discharges the parasitic capacitance of the parasitic diode D of the switch element Q of the above. Therefore, the power factor improving circuit 1A, a first switching element _{Q 1,} the second switching element _{Q 2,} a fifth switch element _{Q 5,} and allows ZVS operation of the switching element _{Q 6} of the sixth.

In the present embodiment, V _th = 1/2 · V _out is set, but the present invention is not limited to this. V _th ≤ 1/2 · V _out may be used.

FIG. 4 is a diagram showing an example of an operation waveform of the power factor improving circuit according to the first embodiment. The larger the threshold value _{Vth, the} longer the non-phase difference control periods 71 and 73 without phase difference control, and the shorter the phase difference control period 72 with phase difference control. Therefore, the _{larger the threshold value Vth} , the more the conduction loss of the current storage inductor L ₃ and each switch element Q and the iron loss of the _{current storage inductor L 3 can be suppressed.} Therefore, the threshold _{V th is} the maximum within the range of _{V th ≦ 1/2 · V} out, it is preferable that the _{V th = 1/2 · V} out. In the present embodiment, since the output voltage V _out is 400 V, the threshold value V _th is preferably set to 200 V.

In this embodiment, the power factor improvement circuit 1A is provided with a threshold value storage unit 51 and the judging unit 52, determination unit 52, and the output the determination signals S ₁ to the drive unit 54. However, power factor improvement circuit 1A is not provided with a threshold value storage unit 51 and the judging unit 52, the determination signal S ₁ is may be supplied from an external circuit to the drive unit 54. As a result, the power factor improving circuit 1A can suppress the control load of the control unit 50A.

Further, the power factor improving circuit 1A can allow the control operation to be stopped if it is about 1 ms at the transition between the phase difference control and the non-phase difference control.

(Second Embodiment)
FIG. 5 is a diagram showing a circuit configuration of the power factor improving circuit of the second embodiment. The same components as those in the comparative example or the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The power factor improving circuit 1B includes a control unit 50B instead of the control unit 50A of the first embodiment. The control unit 50B includes a phase difference storage unit 56 instead of the phase difference calculation unit 53 (see FIG. 3).

The phase difference storage unit 56 stores a predetermined phase difference time t _diff when performing phase difference control. The phase difference time t _diff may be rewritable via wired communication or wireless communication. The phase difference time t _diff is exemplified, but is not limited to 300 ns.

A case where phase difference control is performed during the entire period as in the power factor improvement circuit 1 of the comparative example will be examined. In the vicinity zero crossing of the input voltage V _in, since boost width for boosting the input voltage V _in to an output voltage V _out is large, it is necessary to increase the switching frequency. When the switching frequency is high, the _{upper limit that the on-time Ton} can take is small. If the upper limit value that can be taken on-time T _on is small, the upper limit of possible phase difference time t _diff is small. Accordingly, the phase difference time t _diff in the vicinity zero crossing of the input voltage V _in by using the entire period, when performing the phase difference control, power factor improvement effect can suitably obtained in the vicinity of the peak of the input voltage V _in I can't.

On the other hand, a case where the phase difference control is performed only in the phase difference control period 72 as in the power factor improvement circuit 1B will be examined. In the vicinity of the threshold value _{V th} of the input voltage _{V in,} boost width for boosting the input voltage _{V in} to an output voltage _{V out} is, since small compared to the vicinity of zero cross, it can be lowered switching frequency. When the switching frequency is low, the _{upper limit that the on-time Ton} can take is large. If the upper limit value that can be taken on-time T _on, the greater the upper limit of possible phase difference time t _diff. Accordingly, the phase difference time t _diff in the vicinity threshold V _th of the input voltage V _in, by using the phase difference control period 72, is also possible to perform phase difference control, power factor near the peak of the input voltage V _in An improving effect can be preferably obtained.

Therefore, the power factor improving circuit 1B uses a predetermined phase difference time t _diff when performing phase difference control. As a result, the power factor improving circuit 1B _{can suppress the calculation load of the phase difference time t diff} , and can suppress the control load of the control unit 50B.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, as well as in the scope of the invention described in the claims and the equivalent scope thereof.

1, 1A, 1B Power factor improvement circuit 2 Power supply 4 Load 11 1st input terminal 12 2nd input terminal 13 1st voltage detector 14 1st output terminal 15 2nd output terminal 16 2nd voltage detection Instrument 17 1st arm circuit 18 Polarity switching arm circuit 19 2nd arm circuit 50, 50A, 50B Control unit 51 Threshold storage unit 52 Judgment unit 53 Phase difference calculation unit 54 Drive unit 56 Phase difference storage unit L ₁ First Inductor L ₂ 2nd inductor Q ₁ 1st switch element Q ₂ 2nd switch element Q ₃ 3rd switch element Q ₄ 4th switch element Q ₅ 5th switch element Q ₆ 6th switch element C ₁ Output capacitor N ₁ First node N ₂ Second node

Claims (7)

A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor connected between the first input terminal and the first node, a first switch element connected between the first node and the first output terminal, and One or more first arm circuits having at least a second switch element connected between the first node and the second output terminal.
A third switch element connected between the second input terminal and the first output terminal, and a fourth connected between the second input terminal and the second output terminal. Polarity switching arm having at least the switch element of
A second inductor connected between the first input terminal and the second node, a fifth switch element connected between the second node and the first output terminal, and a fifth switch element. One or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal.
A current storage inductor connected between the first node and the second node,
A control unit that controls the switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage.
With
The control unit
The input voltage input to the first input terminal is compared with the threshold value, and when the input voltage is larger than the threshold value, a position is placed between the first arm circuit and the second arm circuit. Phase difference control for providing a phase difference is performed, and when the input voltage is equal to or lower than the threshold value, non-phase difference control is performed without providing a phase difference between the first arm circuit and the second arm circuit.
A power factor improvement circuit characterized by this. The threshold is one half of the output voltage between the first output terminal and the second output terminal.
The power factor improving circuit according to claim 1. The control unit
When the phase difference control is performed, the phase difference is set to a predetermined time.
The power factor improving circuit according to claim 1 or 2. The control unit
When performing the phase difference control, the larger the input voltage is, the larger the phase difference is.
The power factor improving circuit according to claim 1 or 2. The control unit
When the phase difference control is performed, the phase difference is set to a time directly proportional to the input voltage.
The power factor improving circuit according to claim 4, wherein the power factor is improved. The control unit
When performing the phase difference control, the phase difference is

Calculate with,
The power factor improving circuit according to claim 5.
t _diff phase difference _{time, V in} is the input _{voltage, V out} is the output voltage, C is the parasitic capacitance of the switch element of the first through 6, _{L R} is the inductance of the first and second inductors. A pair of first and second input terminals to which an AC voltage is input, a pair of first and second output terminals to output a DC voltage, the first output terminal, and the first output terminal. An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, the first node and the first output terminal. One or more first arm circuits having at least a first switch element connected to and a second switch element connected between the first node and the second output terminal. And a third switch element connected between the second input terminal and the first output terminal, and connected between the second input terminal and the second output terminal. A polarity switching arm having at least a fourth switch element, a second inductor connected between the first input terminal and the second node, the second node and the first output terminal. A fifth switch element connected between them, and one or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal. The current storage inductor connected between the first node and the second node, and the switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage. It is a control method of a force factor improving circuit including a control unit for controlling.
The control unit compares the input voltage input to the first input terminal with the threshold value, and when the input voltage is larger than the threshold value, the first arm circuit and the second arm circuit are used. When the input voltage is equal to or less than the threshold value, the phase difference is controlled so as to provide a phase difference between the first arm circuit and the second arm circuit. Perform phase difference control,
A method of controlling a power factor improving circuit, which is characterized by the fact that.

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