JP2006353093A - Method for controlling semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving device for suppressing a surge voltage generated when a power semiconductor device interrupts or energizes electric currents, and provide a method for controlling the same. <P>SOLUTION: A driving device of a power semiconductor device that energizes or interrupts main electric current, includes first resistance variable means for changing a first resistance depending on control voltage, second resistance variable means for changing a second resistance depending on a voltage between a first and a second terminals, wherein either one of a voltage of a control power supply or a voltage between the first and the second terminals is divided by the first resistance and the second resistance, and a divided voltage is applied to a control gate terminal when a main current is energized or interrupted. A surge voltage produced during declined electric current time of period can be controlled stably and reduced by applying gate voltages divided by the first and the second resistance variable means depending a control voltage and a voltage between input and output terminals on the power semiconductor device. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive device for a semiconductor element, and more particularly to a drive device that suppresses an overvoltage that occurs during a transient in which a semiconductor element passes and cuts off current, and a control method therefor.

  In a power conversion system using a battery as a power source such as an electric vehicle, a power conversion device such as an inverter is provided between the battery and a load (motor, etc.), and the voltage is low as a power semiconductor element used in the power conversion device. In the case, a power MOSFET is used, and in the case of high, an IGBT is used. Power MOSFETs and IGBTs are both voltage-driven elements, and a further reduction in on-resistance is desired in order to reduce the loss. The voltage-driven power semiconductor element has the on-resistance formed near the surface of the element, the sum of the resistance of the channel section that limits the current according to the gate voltage and the resistance of the semiconductor substrate section that forms a depletion layer when the element is off. Determined by. Although the resistance of the channel portion decreases with miniaturization, the resistance of the substrate portion is determined by the withstand voltage of the element, and cannot be lowered unless the voltage applied to the element at the time of OFF is reduced. On the other hand, even if an attempt is made to reduce the voltage of the power semiconductor element by lowering the voltage of the power supply, if the power supply to the load is constant, the current flowing through the element increases. In this case, since a large current is cut off at high speed, the surge voltage (or called spike voltage) increases. Therefore, it is conceivable that the transient surge voltage is suppressed by circuit measures such as a snubber circuit and a gate drive circuit, and the withstand voltage of the element is reduced by lowering the power supply voltage of the continuously applied power supply voltage. .

As an example of a circuit technique for suppressing a surge voltage generated when an element is turned on or turned off, there is a driving circuit disclosed in Japanese Patent Laid-Open No. Hei 6-291631. This circuit detects the voltage between the input and output terminals of the voltage-driven power semiconductor element, changes the gate resistance in accordance with the detected value, and slows the rate at which the gate voltage of the element increases or decreases. The voltage-driven power semiconductor element has a saturation characteristic that limits the current that can be passed by the gate voltage, and if the increase or decrease of the gate voltage is suppressed, the switching speed of the current is also reduced. Although there is a parasitic capacitance between each terminal of the element, especially the feedback capacitance between the input terminal and the gate terminal is limited in charge or discharge time by the gate current in the transient state. Utilizing this, the voltage change (dV / dt) during switching is also reduced. When the current change (di / dt) or the voltage change (dV / dt) is relaxed in this way, di / dt,
The surge voltage caused by dV / dt is also reduced. Japanese Patent Application Laid-Open No. 6-291631 also describes means for detecting the gate voltage together with the voltage between the input and output terminals and changing the gate resistance in accordance with the detection result. A paper related to this prior art is described in No. 88 “Study of Soft Switching Gate Drive Circuit for IGBT Drive” in the National Conference of Industrial Applications Division of the Institute of Electrical Engineers of Japan in 1995. The drive circuit described in this paper first detects the voltage between the input and output terminals of the switching element at the time of turn-off, and changes the gate resistance from small to large. Subsequently, the gate voltage is detected and the gate resistance is changed from large to small. This drive circuit suppresses the surge voltage during switching, but the period during which the voltage and current waveforms overlap at the time of on and off becomes longer, and the switching loss is greatly increased compared to the case of using the conventional gate drive circuit. It has been reported to do.

Japanese Patent Laid-Open No. Hei 6-291631 1995 IEEJ National Application Division Annual Conference No.88 "Study of Soft Switching Gate Drive Circuit for IGBT Drive"

In order to explain the above-described problems of the prior art, the turn-off operation of the voltage-driven power semiconductor element is divided into the following four periods. Here, an inductive load such as a motor is targeted.
(1) Gate voltage discharge period: This is a period in which a gate current flows through a resistor by application of an off signal, and charges accumulated in the gate are discharged. The gate voltage decreases with time according to an exponential function having a product of gate capacitance and resistance as a time constant. During this period, the main current and voltage between the input and output terminals maintain the values at the on time.
(2) Voltage rise period: The element enters a saturation operation, the feedback capacitor is charged by the gate current, and the voltage between the input and output terminals increases according to the charge level. Since the gate current is used to charge the feedback capacitor, the gate voltage becomes a substantially constant value during this period. The feedback capacitance has voltage dependency and decreases according to the voltage between the input and output terminals, so that the voltage increase between the input and output terminals becomes faster from the middle.
(3) Current falling period: The main current starts decreasing from the time when the voltage between the input and output terminals reaches the power supply voltage. A period from when the main current starts to decrease until it becomes zero is called a current falling period. The gate voltage decreases again from the end of the feedback capacitor charging period, and the main current decreases according to the instantaneous value of the gate voltage.
(4) Off-state steady period; this is a period during which the gate voltage is reduced to a threshold value or less and the power semiconductor element is maintained in a state of interrupting current.

In the case of the above-described prior art, the gate resistance value is decreased during the gate voltage discharging period, and the gate resistance value is increased by detecting that the voltage between the input and output terminals has increased during the voltage rising period.
The gate resistance value is maintained at a large value during the voltage increase period and the current decrease period. Next, the gate voltage is detected, and when this value falls below the threshold voltage, it is detected that an OFF steady state has been entered, and the gate resistance is reduced again.

In a general gate drive circuit, the gate resistance is small and constant from the start of the gate voltage discharge period to the end of the off-stationary period, and the voltage rise period and the current fall period are as short as several tens to hundreds ns, respectively. On the other hand, when the gate resistance value changes from small to large during the voltage rise period in the prior art, each of the voltage rise period and the current drop period extends to about 1 to several μs. However, if there is a detection or operational time delay, the operation of increasing the gate resistance from small to large will not be in time. In this case, since the current is cut off with a small gate resistance, a surge voltage is generated due to a change in current (di / dt). The first problem is that the surge voltage cannot be suppressed in this way.

The second problem is an increase in delay time. If the frequency of the carrier wave is several kHz in a PWM (pulse width modulation) type inverter, the non-wrap time of the upper and lower elements of the inverter is generally 5
μs is the upper limit, and if it becomes 3 to 5 μs only in the voltage rise period as described above, it is not suitable for PWM control.

  Although the switching loss increases from the voltage rising period to the current falling period due to the increase in the gate resistance value, the third problem is to suppress the surge voltage and simultaneously reduce the switching loss as much as possible.

  Furthermore, for inductive loads, a return diode is provided between the input and output terminals of the power semiconductor element, but it is difficult to suppress the surge voltage when this diode reversely recovers.

  The present invention has been made in consideration of the above problems.

  A driving device according to the present invention applies a control voltage supplied from a control power source to a control gate terminal in accordance with an input signal, and a semiconductor element having a first terminal and a second terminal for inputting and outputting a main current, and a control gate terminal. Or a driving device for a semiconductor element comprising a driving circuit means for passing or interrupting a main current by removing the driving circuit means, the driving circuit means having a first resistance variable means and a second resistance variable means. The first variable resistance means passes or blocks the first resistance means whose resistance value changes according to the gate voltage of the control gate terminal and the current flowing through the first resistance means according to the input signal. Switch means, and the second resistance variable means has second resistance means whose resistance value changes in accordance with the voltage between the first terminal and the second terminal, and the second resistance means , A sleeve connected between the first terminal and the second terminal. Has over diode, drive circuit means applies a voltage divided by the voltage between terminals of the first resistor means and the Zener diode to the control gate terminal.

  Preferably, the first resistance variable means further includes a first voltage detection means for detecting a voltage between the control gate terminal and the second terminal, and the first resistance variable means has a first voltage according to the output of the first voltage detection means. The resistance value of the first resistance means changes. More preferably, the first resistance means includes a resistor connected between the control gate terminal and the second terminal, and a capacitance means connected in parallel to the resistor.

  Further preferably, the second resistance variable means compares the difference between the second voltage detecting means for detecting the voltage between the first and second terminals and the output of the second voltage detecting means and a preset reference value. And amplifying means.

  In another control method according to the present invention for a driving device of a semiconductor device, the semiconductor device has a control gate terminal and first and second terminals related to input / output of a main current, and a diode is provided between the first and second terminals. A method for controlling a power semiconductor device in which a control voltage is applied to or removed from a power semiconductor device to pass or cut off the main current, and is provided between a control gate terminal and a second terminal in the process of removing the control voltage. The increased resistance is increased to a predetermined value, and the displacement current flowing from the first terminal to the control gate terminal during reverse recovery of the diode and the voltage drop caused by the resistance are made equal to the gate threshold voltage of the power semiconductor element. This suppresses the surge voltage when the freewheeling diode reversely recovers.

In the method for controlling a driving device according to the present invention when a battery is used as a power source and main current is supplied from the battery to the power semiconductor element via the capacitor, the parasitic of wiring existing in the closed circuit including the capacitor and the power semiconductor element is provided. The total inductance value is L, the capacitance of the capacitor is C, the instantaneous value of the main current output from the power semiconductor element is I, the effective value of this current is Iav, the open circuit voltage of the battery is Vb, and the internal resistance of the battery is Rb The reference value of the amplifying means or the voltage clamp value of the power semiconductor element determined by the Zener diode is Vc, and the time tf when the power semiconductor element cuts off the current is tf = L × I / (Vc−Vb + Rb × Iav)
By setting the reference value or Zener diode so that the time tf is 10% or less of the time constant determined by Rb × C with respect to the instantaneous maximum value of the main current, a better surge voltage suppression effect can be obtained. It is done.

Further, when the power semiconductor element constitutes an inverter unit in which at least two of them are connected in series, and the PWM signal generator supplies a control signal to the drive device in order to perform PWM control of the inverter unit, tf = L × I / (Vc−Vb + Rb × Iav)
From the above relationship, the current interruption time tf is calculated, and the minimum delay time can be obtained by providing a non-wrap time longer than tf at the output of the PWM signal generator.

  According to the driving device of the present invention, the gate voltage divided by the first and second resistance variable means, which changes in accordance with the control voltage and the voltage between the input and output terminals, is applied to the power semiconductor element to thereby reduce the current falling period. Can be stably suppressed.

Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a configuration of a power conversion device including a power semiconductor element provided with a drive device of the present invention. The main circuit has a general three-phase inverter configuration by connecting six power semiconductor elements consisting of a power MOSFET (example Q1) and its built-in diode (example QD1) between the positive and negative electrodes of the power supply VB to a three-phase bridge. ing. The output terminals of each phase are U, V, W and are connected to the motor M. The power MOSFETs Q1 to Q6 are each provided with a driving device 1. As an internal configuration of the driving device 1, a gate charging unit is provided in which a P-channel MOSFET M1 and a resistor R1 are connected in series between the positive electrode of the control power supply Vcc and the gate terminal of Q1. A drive signal is sent from the PWM control device 5 to the control circuit 4 provided in the drive device 1, and the control circuit 4 creates an on signal Son and an off signal Soff for Q1. When the on signal Son is applied to the gate terminal of M1, M1 is turned on, a gate current is supplied to Q1 via R1, and the input capacitance Cgs between the gate and source terminals of Q1 is charged. A region 2 surrounded by a chain line is a first variable resistance means, and includes a first gate discharge circuit in which a resistor R2 and N-channel MOSFETs M4 and M2 are connected in series between the gate and the source terminal of Q1, in parallel. A second gate discharge circuit in which a resistor R3 and an N-channel MOSFET M3 are connected in series to the first gate discharge circuit is provided. Here, the gate terminals of M2 and M3 are connected in common, and the gate terminal is turned on when the off signal Soff transmitted from the control circuit 4 is given to the gate terminal. Further, inside the first resistance variable means 2, resistors R5 and R6 are connected in series between the positive electrode and the negative electrode of the control power supply Vcc, and the connection point of both resistors is connected to the polarity so that the cathode is the cathode and the gate terminal of Q1 is the anode. The diode D1 is provided. Resistors R5, R6 and D1 constitute a bias circuit for the N-channel MOSFET M4. This bias circuit compares the voltage Vcc divided by R5 and R6 (defined as V1) with the gate-source voltage Vgs of Q1, and applies the larger voltage to the gate of M4. When the signal Soff is input to M2 and M3, these elements are turned on. Immediately after Soff is applied, the gate-source voltage Vgs of Q1 is larger than the divided voltage value V1, and this value is applied to the gate of M4. Applied. With the supply of a voltage equal to Vgs, the on-resistance of M4 becomes a small value. If the combined resistance of the first gate discharge circuit (R2, M4, M2) defined above is RT1, and the combined resistance of the second gate discharge circuit (R3, M3) is RT2, the gate voltage of M4 is almost equal. Under conditions close to the rated value of Vgs, RT1 is selected to be smaller than RT2. In this case, the ratio of RT1 / RT2 is desirably 1/10 or less.

Next, a region 3 surrounded by a broken line is the second variable resistance means, and a gate charging circuit comprising a P-channel MOSFET M5 and a resistor R4 connected in series between the positive terminal of Vcc and the gate terminal of Q1 is provided therein, A capacitor C1 is provided in parallel with the resistor R4. Further, voltage dividing means constituted by resistors R7 and R8 is provided between the Q1 node rain terminal and the source terminal, and a value (V2) obtained by dividing the Q1 node rain-source voltage Vds is obtained. Here, a Zener diode ZD1 is connected to R8 in parallel, and the upper limit value of V2 is set to the breakdown voltage of ZD1. In addition, a capacitor C2 is connected in parallel to R7, and the voltage division value is determined by the impedance of C2 and R8 for a transient change in Vds. Then, when Vds settles to a steady value, the voltage is divided by R7 and R8. The value V2 is determined. Such a function of the capacitor C2 is called a speed-up capacitor. The capacitor C1 in parallel with the previously extended R4 also functions as a speed-up capacitor. That is,
At the moment when M5 is turned on, the resistor R4 is over-passed by the impedance of C1. The divided voltage value V2 and the reference value Vref are input to the (−) input terminal and the (+) input terminal of the amplifier 6, respectively. In the amplifier 6, when the divided voltage value V2 increases beyond the reference value Vref, the output potential decreases, and as a result, the P-channel MOSFET M5 is turned on.

  A detailed configuration of the amplifier 6 is shown in FIG. The basic is a differential amplifier, and a constant current source is formed by a current mirror circuit of a resistor R9 and N-channel MOSFETs M6 and M7, and the total current value of the N-channel MOSFETs M8 and M9 constituting the differential unit is a constant current. equal. In a general differential amplifier, a current mirror type load is connected to the M8 node rain terminal and the M9 node rain terminal so that the gain of the amplifier can be increased. On the other hand, in the configuration of FIG. 3, there is no load resistance on the M8 node rain side, and the resistor R10 is provided only on the M9 node rain side. The above-described constant current is shunted by two combined resistors of M8 on-resistance (which depends on the reference value Vref) and M9 on-resistance (which depends on the reference value V2) plus R10, and the gain is small. The gate voltage is linearly increased in accordance with the difference voltage between the divided voltage value V2 and the reference value Vref. In the embodiment of FIG. 1, as will be described later, the control voltage Vcc is divided by the first resistance variable means and the second resistance variable means and applied to the gate terminal of Q1, thereby suppressing the temporal change of the gate voltage Vgs of Q1. This suppresses the surge voltage during switching. In this case, if the gain of the first resistance variable means or the second resistance variable means (resistance change rate with respect to the detected value of Vgs or Vds) is too high, the voltages Vds and Vgs of Q1 become oscillating. Therefore, it is desirable that these gains are moderately small, and FIG. 3 is an example.

  Next, the effect of suppressing the surge voltage according to the embodiment of FIGS. 1 and 3 will be described using the operation waveforms of FIG.

FIG. 2 shows the waveforms of the gate-source voltage Vgs (Q1), the gate current Igs (Q1), the drain-source voltage Vds (Q1), and the drain current Ids (Q1) of Q1 in response to the drive command to Q1, and M2. And M3 on / off operation, and M4 on-resistance Ron (M4) and M5 on-resistance Ron (M5) over time. From time t1 to t2, Q1 is in an on state, and from t2 to t7 is an off operation. Although not shown at time t2, M1 is turned off, and M2 and M3 are turned on as shown in FIG. Here, in the ON state before t2, Vgs
(Q1) is charged to a voltage value substantially equal to the control voltage Vcc. When M2 is turned on, a gate voltage substantially equal to Vgs (Q1) is applied between the gate and source of M4. As a result, the on-resistance Ron (M4) of M4 is reduced to a very small value. Assuming that the sum of the on-resistances of the resistors R2, Ron (M4) and M2 is 1/10 or less as described above compared to the sum of the on-resistances of the resistors R3 and M3, the resistors R2, Ron (M4) and M2 The sum of the on-resistances becomes the discharge resistance of the gate voltage, and the charge accumulated between the gate and source of Q1 is rapidly discharged. This is the period from t2 to t3, which corresponds to the aforementioned gate voltage discharge period. At this time, the gate current Igs (Q1) of Q1 becomes the maximum current value during the turn-off operation.

Next, after t3, the gate voltage Vgs (Q1) of Q1 is reduced. As a result, the gate voltage of M4 is also reduced, and the on-resistance Ron (M4) becomes higher depending on the decrease of Vgs (Q1). Although not shown in FIG. 2, the voltage V1 in FIG. 1 is decreased. In addition, Igs (Q1) decreases as Ron (M4) increases. This state is continued during the period from t3 to t4, and the feedback capacitance is charged by Igs (Q1) on the way, and the drain-source voltage Vds (Q1) increases.
This corresponds to the voltage rise period. When Vgs (Q1) becomes smaller than a certain voltage (for example, 1/2 to 1/3 or less of the control voltage Vcc), Ron (M4) increases remarkably, and the resistance R2 and Ron
The current characteristic of M4 is selected so that the sum of the on-resistances of (M4) and M2 increases to 10 times or more than the sum of the on-resistances of resistors R3 and M3. As a result, from the middle of the period t3, the gate-source resistance of Q1 is substantially equal to the sum of the resistances R3 and M3, and the on-resistance of M3 is selected to be sufficiently smaller than the resistance value of R3. Only the resistor R3 should be considered as the gate-source resistance of Q1. Note that the time change (dV / dt) of the drain-source voltage Vds (Q1) decreases as Ron (M4) increases.

When the value V2 obtained by dividing Vds (Q1) by R7 and R8 in the middle of the voltage rise period becomes equal to or higher than the reference value Vref, the output voltage corresponding to the difference voltage of (V2−Vref) by the amplifier 6 is used as the gate voltage of M5. Applied and M5 is turned on. The time when M5 is turned on is assumed to be t4. In FIG. 2, the value of Vref is selected so that Vds (Q1) when the divided voltage value V2 and the reference value Vref are substantially equal is substantially equal to the voltage VB of the main power supply. Here, in this embodiment, first, during the period from t3 to t4, the on-resistance Ron (M4) of M4 increases according to the gate voltage Vgs (Q1) of Q1, and as an effect of this, the gate discharge resistance value of Q1 increases. The charging current (Igs (Q1)) of the feedback capacity of Q1 decreases and charging of the feedback capacity becomes slow. This means that the voltage rise of the drain-source voltage Vds (Q1) also slows down, and prevents the delay in the detection of Vds (Q1) due to the voltage rise too fast as in the above-mentioned known example. It is out. In addition, the effect of the speed-up capacitor C2 increases the divided voltage V2, and this also contributes to shortening the detection delay of Vds (Q1). Further, immediately after M5 is turned on, the series impedance of M5 is reduced momentarily by the speed-up capacitor C1, which also has the effect of shortening the operation delay of the resistance variable means.

During the period from t4 to t6, both the first resistance variable means 2 and the second resistance variable means 3 are operating. The first resistance variable means has a value RT1 between the gate and source of Q1 and a combination of resistors R2 and Ron (M4) and the sum of the on resistances of M2 and the sum of the on resistances of resistors R3 and M3 in parallel. On the other hand, since the second variable resistance means has a value RT2 determined by the sum of the resistors R4 and Ron (M5), the gate voltage of Q1 becomes a value obtained by dividing the control power supply Vcc by RT1 and RT2. Assuming that this value is Vo, Ron (M5) is increased by the function of the amplifier with respect to the increase of Vds (Q1) even if the current change (di / dt) tries to generate a surge voltage during the current falling period from t5 to t6. The operation of further decreasing and increasing Vo works. As Vo increases, the transient impedance of Q1 becomes lower, which tends to suppress current interruption. In this way, the divided voltages of the first resistance variable means and the second resistance variable means are the gate voltage Vgs (Q1) and the drain voltage Vds.
(Q1) is detected, and feedback control is performed so that Vgs (Q1) becomes a stable value Vo. By this effect, the current change (di / dt) is suppressed, and the surge voltage is minimized. Although not shown in FIG. 1, the parasitic inductance of the wiring that supplies current from the main power supply VB to Q1 is Ls, the instantaneous value of the main current that Q1 cuts off is I, and the maximum value of Vgs (Q1) including the surge voltage Is Vc, the time tf required for Q1 to cut off the current I has the relationship Ls · di / dt = Vc−VB (1), and when di / dt is linearly approximated, tf = Ls × I / (Vc−VB) (2). This tf is equal to the time from t5 to t6. During this time, the drain voltage Vds (Q1) and the drain current Ids (Q1) overlap, resulting in turn-off loss, but this value is stored in the parasitic inductance Ls of the wiring. Equal to electromagnetic energy. Since this electromagnetic energy is always generated at the time of turn-off, it can be said that the turn-off loss is minimized.

  In FIG. 2, the turn-on operation is performed after time t7. However, the embodiment of FIG. 1 does not perform any special function when Q1 is turned on. As in the case of the conventional driving device, when M1 is turned on, the gate of Q1 is connected via the resistor R1. Supply current between the sources to increase the gate voltage. At this time, the free-wheeling diode QD2 provided in parallel with Q2 reversely recovers, but the surge voltage generated during reverse recovery of the diode can also be suppressed by the driving device 1 of the present invention. This will be described in detail with reference to FIGS.

FIG. 4 is a diagram illustrating a state when the diode QD2 is reversely recovered. The circuit parts shown in FIG. 4 that are the same as those in FIG. The difference from FIG. 1 is that only three power semiconductor elements Q1, Q2, and Q4 are described for each power semiconductor element of the three-phase inverter, but only the elements necessary for explaining the operation of QD2 are described. The exact configuration is the same as in FIG. In FIG. 4, only the resistor R3 is connected between the gate and source of Q2, but the actual configuration is the same as that of the driving device 1 for Q1 of FIG.
Assuming a reflux state in which Q2 is off and current flows in QD2 in FIG. 4, the gate-source voltage of Q2 is almost zero, so M4 described in FIG. 1 is in a high resistance state. . Further, since the on-resistance of M3 is selected to be sufficiently smaller than the resistance value of R3 as described above, only the resistor R3 should be considered as the gate-source resistance of Q2 when QD2 is in the reflux state. . Note that Ls is a component newly described in FIG. 4, and Ls is a parasitic inductance of a wiring connecting the positive electrode of the gate main power supply VB of Q2 and the Q2 and Q4 node rain terminals. Further, although the load is the motor M in FIG. 1, it is described as an inductive load in FIG.

  FIG. 5 shows an operation explanation and an operation waveform when the diode QD2 performs reverse recovery. First, FIG. 5A shows a case where a conventional driving device is used. The resistance value of the resistor R3 in FIG. 5A is set to 1/10 or less as compared with R3 of the present invention. In the conventional driving device, the gate resistance does not change from the start of turn-off in the period t2 shown in FIG. 2 until the end of the off-state in the period t7, and the off-gate resistance generally aims to pass a large gate current in the period t2 to t3. This is because it is selected. FIG. 5B shows an operation waveform in the conventional drive device, and the return current I (QD2) is displayed with the polarity from the anode to the cathode of QD2 being positive. In FIG. 5B, I (QD2) decreases and eventually becomes less than zero, but a reverse polarity current flows until all the electrons and holes accumulated in QD2 are discharged. This is a phenomenon called reverse recovery. The reverse recovery current starts to decrease after reaching the peak, and a reverse voltage (VQ2 in the figure) with the cathode being positive is applied to QD2. The reverse voltage has a large voltage change (dV / dt) as shown in FIG. This spike voltage is generated by a current change (dI / dt) when the parasitic inductance Ls and the reverse recovery current decrease. In this way, a current VD2 having a large (dV / dt) and a spike voltage superimposed thereon flows a current for charging the feedback capacitor between the Q2 node rain gate and the gate, and this charging current is directed to the source of Q2 via R3. Since the resistance R3 is small in the conventional driving device, the voltage drop generated by the feedback capacitor charging current at R3 is small. In general, the value of the resistor R3 is selected so that this voltage drop is equal to or lower than the gate threshold voltage of Q2. Was.

FIG. 5C shows the operation when the driving device of the present invention is used. The phenomenon until QD2 recovers reversely and voltage VQ2 having a large voltage change (dV / dt) is generated is the same as in the conventional case.
Here, when a current for charging the feedback capacitor of Q2 flows by the voltage VQ2, and this charging current causes a voltage drop in R3, in the present invention, since the resistor R3 is more than 10 times larger than the conventional, the gate-source of Q2 A voltage as shown in FIG. The value of R3 is determined so that the peak value of this voltage is slightly larger than the gate threshold voltage of Q2. As a result, the MOSFET Q2 is turned on for a moment, and a current from the drain to the source as shown in FIG. 5C flows. Since the MOSFET Q2 that is turned on has a gate voltage that is not sufficiently high, its resistance is larger than the period from t1 to t2 in FIG. 2, but is much smaller than that in the conventional off state of FIG. . Since the current of Q2 flows in addition to the reverse recovery current of QD2, the current I (QD2) of FIG. 5D has a longer conduction period than that of FIG. 5B and the current change (dI / dt). Is getting smaller. When (dI / dt) is reduced in this way, the spike voltage as shown in FIG. 5B does not occur, and the electromagnetic energy accumulated in the parasitic inductance Ls is caused by the loss determined by the product of the voltages VQ2 and I (QD2). Is consumed. The present invention generates a dV / dt false firing of the MOSFET Q2, which is avoided in the conventional driving device, and suppresses the spike voltage by using this. The current of the MOSFET Q2 flowing due to the voltage change (dV / dt) at the time of reverse recovery also has a drawback of increasing the switching loss as compared with the case of using a conventional driving device, but if the resistance value of R3 is optimally selected, Q2 is It is also possible to minimize the increase in loss caused by the conduction. Further, if the spike voltage is suppressed as in the present invention, the withstand voltage of the element Q2 can be made smaller than before, so that the on-resistance of Q2 can be reduced. According to the present invention, although the switching loss increases, the on-resistance can be reduced and the steady loss can be reduced by reducing the breakdown voltage of the element. If the reduction of the steady loss is larger than the increase of the switching loss, the overall loss is reduced.

FIG. 6 shows a second embodiment relating to the second variable resistance means 3 shown in FIG. 1 differs from the configuration of FIG. 1 in that the output of the amplifier is applied directly to the gate of M5 in FIG. 1, whereas in FIG. 6, the diode D3 and the resistor R11 in parallel therewith, the anode terminal of D3, and the Vcc It is applied to the gate of M5 through a delay means composed of a capacitor C3 provided between the negative electrodes.
When the gate potential of M5 falls due to the effect of this delay means, the voltage of C3 is discharged through D3 having a small resistance, and the time delay is slight. On the other hand, when the gate potential of M5 increases, the voltage of C3 is charged through R11 having a large resistance, and a time delay occurs due to the time constant of R11 and C3. According to this delay means, even when Vds (Q1) decreases at time t6 in FIG. 2, the current that M5 was suddenly flowing is not interrupted, but is slowly interrupted. This brings about an effect that the gate voltage Vgs (Q1) immediately after time t6 decreases slowly, and Vds
The waveform vibration of (Q1) can be suppressed. The time constant determined by the resistor R11 and the capacitor C3 provided in the delay means is about 5 to about the resonance period determined by the Q1 node rain-source parasitic capacitance (Coss) and the parasitic inductance Ls of the wiring as shown in FIG. If the length is selected to be about 10 times longer, it is possible to prevent Vds (Q1) from vibrating after time t6.

FIG. 7 shows a second embodiment relating to the first variable resistance means 2 shown in FIG. 7 differs from FIG. 1 in that a resistor R2 and an n-channel MOSFET M2 are first connected in parallel between the gate and source of Q1, and a control signal Soff is supplied to a series connection comprising resistors R12 and R13 and a MOSFET M6. . A gate signal is supplied to M2 from the connection point of R12 and R13.
M6 compares the gate-source voltage Vgs (Q1) of Q1 with the reference voltage Vref2, and when the gate voltage Vgs (Q1) is higher than the reference voltage Vref2, M6 is turned off, and when it becomes lower, the comparator 7 turns on M6. Output a signal. That is, when Vgs (Q1) is higher than Vref2, since M6 is off, the voltage of the control signal Soff is applied to M2 through the resistor R12 as it is. In this case, the resistors R2 and R3 are in parallel, but R2 is 1 / compared to R3 as in FIG.
10 or less is selected so that the combined resistance is approximately only R2. Q1 gate voltage Vgs
(Q1) is rapidly discharged by this combined resistance.

Next, when Vgs (Q1) becomes lower than Vref2, since M6 is turned on, a voltage obtained by dividing the control signal Soff by R12 and R13 is applied as the gate voltage of M2. When the gate voltage decreases due to the voltage division of R12 and R13, the on-resistance of M2 increases. If the current characteristic of M2 is selected so that the on-resistance of M2 increases and its value is much larger than that of resistor R3, the combined resistance connected between the gate and source of Q1 is almost equal to R3. Become. As a result, the gate voltage Vgs (Q1) of Q1 is slowly discharged by the increased combined resistance, and the operation is the same as that described with reference to FIGS. Comparing FIG. 1 and FIG. 7, M2 and M4 in the case of FIG. 1 require a large current rating MOSFET because a large gate current flows at the beginning of turn-off. Similarly, M2 in FIG. 7 requires a MOSFET with a large rating. However, since M6 limits the current with R12 and R13, the current rating may be smaller than that of M2. If the current rating of the MOSFET to be used can be reduced, the cost can be reduced. In particular, when the drive device is integrated, the cost is effective.

  FIG. 8 shows a second embodiment relating to the driving apparatus of the present invention. The inverter type power converter shown in FIG. 8 is the same as that shown in FIG. 1, and only the second resistance variable means 3 surrounded by the broken line of the drive device 1 is different. The second variable resistance means 3 in FIG. 8 includes a series connection including a Zener diode ZD2 and a diode D2 between the Q1 node rain terminal and the gate terminal, taking the power MOSFET of Q1 as an example. In the present invention, the Q1 node rain-source voltage Vds (Q1) is divided by the series connection of ZD2 and D2 and the first variable resistance means 2, and the divided voltage is applied as the gate voltage of Q1. Is a feature. Although there has been an example in which a Zener diode is provided between the drain terminal and the gate terminal as in FIG. 8 for overvoltage protection of the power semiconductor element, if this method is used for the purpose of suppressing a surge voltage generated during switching, Since the Zener diode falls and current flows every switching, the loss of the Zener diode becomes a problem. An object of the present invention is to suppress the surge voltage and reduce the loss of the Zener diode by using the Zener diode and the resistance variable means together.

  It should be noted that it is desirable that the breakdown voltage of the Zener diode ZD2 is selected to have a characteristic equal to the voltage VB of the main power supply in terms of reduction of loss and delay time.

FIG. 9 shows operation waveforms when the driving apparatus of FIG. 8 is used, and the operation up to time t4 is the same as that of FIG. When the Q1 node rain-source voltage Vds (Q1) exceeds the breakdown voltage of the Zener diode ZD2 at time t4, a current flows through ZD2, and this current is a first gate discharge resistor composed of R2, M4, and M2, R3, It flows to the second gate discharge resistor consisting of M3.
Here, it is assumed that there is no M4 in the first gate discharge resistor, and only M2 and R2 that are turned on in response to the control signal are assumed. Even if the second gate discharge resistor is provided, since the value of R2 is 1/10 or less as compared with R3 as described above, the synthesized gate discharge resistance is substantially equal to R2 and a small value. This has the same characteristics as the conventional example in which a Zener diode is provided for overvoltage protection. That is, the small resistance R2 is reducing the gate-source voltage Vgs (Q1) of Q1, and the gate current flowing through R2 is large. When ZD2 falls, the current in ZD2 flows through R2, and the current increases to a value approximately equal to the gate current through R2. At this time, the current that R2 can flow is a value obtained by dividing the gate-source voltage Vgs (Q1) of Q1 by R2.
When the current of ZD2 increases to a current value that can flow through R2, the gate voltage Vgs (Q1) does not decrease any more, and the current is cut off gradually. Further, since the current change (dI / dt) is reduced, the surge voltage can be suppressed. In FIG. 8, the current falling period from t5 to t6 corresponds to this, and the voltage obtained by dividing the Q1 node rain-source voltage Vds (Q1) by ZD2 and R2 is applied as the gate-source voltage Vgs (Q1) of Q1. It can be said that. On the other hand, the current that can flow through R2 increases as the value of R2 decreases, and a loss determined by the product of this current and the breakdown voltage occurs in the Zener diode.

In the case of the driving device according to the present invention, as described with reference to FIG. 2, the on-resistance of M4 is small until time t3, but thereafter, M4 is turned on depending on the decrease in the gate voltage Vgs (Q1) of Q1. The resistance increases, and at time t4, the combined value of the gate discharge resistance is R3, which is 10 times larger than R2. For this reason, the current that flows when ZD2 falls is also greatly reduced compared to the case where there is no M4. Accordingly, the surge voltage of Q1 can be suppressed and the loss of the Zener diode can be greatly reduced.

FIG. 10 shows an embodiment for achieving the first resistance variable means by using the principle of the speed-up capacitor. The configuration other than the first resistance variable means surrounded by the chain line 2 is the same as that shown in FIG. The first variable resistance means in this embodiment includes a resistor R2 and M2 that switches by the drive signal Soff in series between the gate and source of Q1, and a speed-up capacitor C4 in parallel with R2. In the period t2 to t3 shown in the operation waveform of FIG.
When the gate voltage of Q1 changes sharply and a large gate current flows, the impedance of the speed-up capacitor C4 becomes smaller than R2 and the gate current flows. When the temporal change of the gate voltage of Q1 becomes small in the next period from t3 to t6, the impedance of C4 becomes high and R2 works as a gate resistance. Therefore, in FIG. 10, the value of the resistor R2 is set to be about 10 times larger than that in the example of FIG. 8, and C2 is used as a resistance means for discharging the gate current during the period t2 to t3 in the initial turn-off, and the Zener diode ZD2 If R2 is used as the gate resistance during the period from t4 to t6 when the current falls, the current of the Zener diode can be reduced and the loss can be reduced by the principle described in FIG. Note that the capacitance of C4 is preferably equal to the gate-source capacitance of Q1.

  In the driving apparatus 1 described in FIGS. 1 to 10, the MOSFET, the resistor, the Zener diode, the amplifier, and the comparator excluding the capacitors C1 to C4 are all components suitable for an integrated circuit (IC), and one or a plurality of them are included. You may comprise with an IC chip. By using an IC, the operation delay of the circuit is greatly shortened, and characteristics more suitable for the purpose of the present invention can be obtained.

  FIG. 11 shows a configuration of a power conversion system that supplies power from a large-capacity battery to an inverter device equipped with a drive device according to the present invention.

The three-phase inverter composed of the power semiconductor elements Q1 to Q6 in FIG. 11 and the motors M and Q1 to Q6 connected as loads to the motors M and Q1 to Q6 are the same drive device 1 and drive device 1 as FIG. 1 or FIG. The control power supply Vcc that supplies power to the control device 5 and the control device 5 that transmits the PWM control signal to the drive device 1 are all the same as those described in FIG. 1 or FIG.
Ls1 is the parasitic inductance of the wiring connecting the smoothing capacitor CF and the three-phase inverter, and Ls2 is the parasitic inductance of the wiring connecting the battery VB and the smoothing capacitor CF. Next, the battery VB can be expressed in terms of an equivalent circuit by an internal resistance RB and an open circuit voltage VBO. The current for charging or discharging the battery VB is measured by the current sensor 8, and the current measurement result is sequentially transmitted to the battery state monitoring device 9. The state monitoring device 9 also measures the voltage of the battery VB, estimates the internal resistance RB and the open circuit voltage VBO from the measured current and voltage information of the battery VB, and transmits them to the control device 5.

  In the present invention, when the battery VB is energized with a large current, the voltage between the positive and negative electrodes appears to decrease or increase from the true voltage (open circuit voltage VBO) due to the influence of the internal resistance RB. It is aimed to be applied as a control method.

As described in the above equations (1) and (2), the parasitic inductance of the wiring existing in the closed circuit including the power semiconductor element from the smoothing capacitor CF (capacitance is Cf) is the power of Ls1, Q1 to Q6. The instantaneous value of the main current output from the semiconductor element is I (discharge current for the battery), the effective value of this current is Iav, the voltage between the positive and negative electrodes of the battery is VB, the open circuit voltage is VBO, and the internal resistance of the battery is RB. If the maximum voltage value of the power semiconductor element when the surge voltage is suppressed by the device is Vc (corresponding to Vds (Q1) in the period t5 to t6 in FIG. 2), and the time during which the power semiconductor element cuts off the current is tf. These parameters have the following relationship:
The surge voltage generated during the current interruption period is Ls1 × dI / dt = Vc−VB (3) When dI / dt at the time of current interruption is linearly approximated,
dI / dt = I / tf (4) The voltage between the positive and negative electrodes of the battery is decreased due to the effect of the effective value Iav of the current passed through the power semiconductor element during the on-state period and the internal resistance,
VB = VBO−RB × Iav (5) The surge voltage of the expression (3) has a current of dI / dt from the time when the current starts to be interrupted (t5 in FIG. 2) until the electromagnetic energy stored in Ls1 is consumed (t6 in FIG. 2). It means that it continues to flow while changing with the gradient. However, this current flows between the smoothing capacitor, the wiring parasitic inductor, and the power semiconductor element, and the current is not supplied from the battery. Therefore, the battery recovers the voltage drop (RB × Iav) due to the internal resistance and current described in equation (5). This recovery process is an exponential voltage change with the internal resistance RB and the capacitance Cf of the smoothing capacitor as time constants. On the other hand, from the viewpoint of suppressing the surge voltage of the power semiconductor element, the time constants of RB and Cf are sufficiently long with respect to the current falling period (t5 to t6), and VB in equation (3) is maintained at a low value. Is preferred. If Vc is selected to be 80 to 90% of the breakdown voltage of the power semiconductor element, dI / dt in the current falling period can be selected larger as VB is lower, and tf in equation (4) becomes shorter. This leads to shortening the delay time, which was a problem in the known example, and ensuring the PWM non-wrap time.
Assuming that Rb is 20 mΩ and Cf is 5000 μF, for example, the time constant is 100 μs. If the current fall time tf is selected to be 10% or less of the above time constant, the battery voltage is sufficiently short to recover the battery voltage. Is approximately equal to the value of As described above, the PWM non-wrap time has an upper limit of 5 μs, which corresponds to 5% for the above example of the time constant, and satisfies the condition of 10% or less.
The delay time can be controlled by setting the clamp value Vc of the voltage during the current falling period using the reference value Vref in FIG. 1 or the breakdown voltage of the Zener diode ZD2 in FIG. The expressions (3) to (5) depend on the amplitude I of the cutoff current, and the maximum value of the main current or the effective value for the maximum main current is considered in setting the Vc.

Further, since the time tf is expressed as tf = L × I / (Vc−Vb + RB × Iav) (6) from the expressions (3) and (4), the control device 5 obtains information from the battery state monitoring device 9. Based on the above, the calculation of the equation (6) can be performed, and the PWM signal can be provided with a non-wrap time longer than tf. According to this control method, even when the amplitude I of the cutoff current changes, the accurate current fall time tf can be grasped and reflected in the non-lap time.

  According to the driving device of the present invention, the gate voltage divided by the first and second resistance variable means, which changes in accordance with the control voltage and the voltage between the input and output terminals, is applied to the power semiconductor element to thereby reduce the current falling period. Can be stably suppressed.

According to the control method of the present invention, when the freewheeling diode reversely recovers, the power semiconductor element in parallel with it can be dV / dt fired in a short time to suppress the surge voltage.
Although the switching loss slightly increases due to the dV / dt firing, the steady loss is greatly reduced by lowering the withstand voltage, and the entire loss is reduced. Furthermore, the voltage at the time of surge suppression can be optimized and the current fall time can be shortened by setting the reference value of the second resistance variable means or the breakdown voltage of the Zener diode in consideration of the influence of the internal resistance. In addition, it is possible to set a non-lap time of PWM control considering this time.

1 is a circuit diagram of a driving apparatus showing a first embodiment of the present invention. Operation waveform diagram. The circuit diagram of the amplifier which optimized the gain. The circuit diagram in which a diode explains reverse recovery. Operation | movement explanatory drawing when a diode carries out reverse recovery. The circuit diagram of the amplifier which provided the delay means. 2nd Example regarding the 1st resistance variable means. The circuit diagram of the drive device which shows 2nd Example of this invention. FIG. A third embodiment relating to the first resistance variable means. The block diagram of the power converter device which shows the control method of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Drive device, 2 ... 1st resistance variable means, 3 ... 2nd resistance variable means, 4 ... Control circuit, 5 ... PWM control apparatus, 6 ... Amplifier, 7 ... Comparator, 8 ... Current sensor, 9 ... Battery state monitoring device, Q1 to Q2 ... power semiconductor element, QD1 to QD6 ... reflux diode, M1 to M9 ...
MOSFET, R1 to R11 ... resistor, C1 to C4 ... capacitor, ZD1, ZD2 ... Zener diode, D1 to D3 ... diode, M ... motor, VB ... power source (or battery), Vcc ... control power source, Vref and Vref2 ... reference value .

Claims (4)

A control voltage is applied to or removed from a semiconductor element having a control gate terminal and first and second terminals related to input and output of the main current and having a diode between the first and second terminals. A method of controlling a semiconductor element that passes or blocks current,
A method of controlling a semiconductor element, wherein a voltage generated between the control gate terminal and the second terminal during reverse recovery of the diode is made larger than a gate threshold voltage of the semiconductor element. The method for controlling a semiconductor device according to claim 1,
The voltage generated between the control gate terminal and the second terminal during reverse recovery of the diode is set such that a peak value is slightly larger than a gate threshold voltage of the semiconductor element. For controlling a semiconductor device. The method for controlling a semiconductor device according to claim 1,
The voltage generated between the control gate terminal and the second terminal during reverse recovery of the diode is set so that current flows instantaneously from the first terminal toward the second terminal. A method for controlling a semiconductor device. A control voltage is applied to or removed from a semiconductor element having a control gate terminal and first and second terminals related to input and output of the main current and having a diode between the first and second terminals. A method of controlling a semiconductor element that passes or blocks current,
In the process of removing the control voltage, a resistance provided between the control gate terminal and the second terminal is increased to a predetermined value, and a displacement current flows from the first terminal to the control gate terminal during reverse recovery of the diode; A method for controlling a semiconductor element, wherein a voltage drop caused by the resistor is set to a value larger than a gate threshold voltage of the semiconductor element.

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