JP6971869B2 - Power factor improvement circuit and control method of power factor improvement circuit - Google Patents

Description

The present invention relates to a power factor improving circuit and a method for controlling the power factor improving circuit.

Patent Document 1 describes a chopper-controlled switching regulator. The switching regulator described in Patent Document 1 generates a lamp voltage that gradually returns to zero at a predetermined rate of change when the power is turned on, and this lamp voltage suppresses the gain of the pulse width of the switching operation. As a result, the switching regulator described in Patent Document 1 suppresses overcurrent due to overshoot immediately after the power is turned on.

However, although the switching regulator described in Patent Document 1 suppresses an overcurrent due to overshoot immediately after the power is turned on, the case where the current flowing through the inductor is cumulatively increased is not considered. Therefore, in the switching regulator described in Patent Document 1, the current flowing through the inductor may be cumulatively increased, which may lead to magnetic saturation of the inductor and destruction of the switch element.

Japanese Unexamined Patent Publication No. 4-156275

An object of the present invention is to provide a power factor improving circuit and a method for controlling a power factor improving circuit, which can suppress a cumulative increase in the current flowing through the inductor.

The power factor improving circuit of one aspect of the present invention is
A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor connected between the first input terminal and the first node, a first switch element connected between the first node and the first output terminal, and One or more arm circuits having at least a second switch element connected between the first node and the second output terminal.
A third switch element connected between the second input terminal and the first output terminal, and a fourth connected between the second input terminal and the second output terminal. Polarity switching arm circuit with at least the switch element of
A control unit that controls the switching operation of the first to fourth switch elements, and
Equipped with
The control unit
When the difference between the DC voltage and the absolute value of the AC voltage becomes smaller than the threshold value, switching operation stop control for stopping the switching operation of the first to fourth switch elements is performed, and the difference. When is equal to or greater than the threshold value, switching operation restart control for restarting the switching operation of the first to fourth switch elements is performed.
It is characterized by that.

The power factor improving circuit of one aspect of the present invention is
A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor whose one end is connected to a first node, a rectifying element connected between the first node and the first output terminal, and the first node and the second output. One or more arm circuits having at least a switch element connected between the terminals and
A full-wave rectifier circuit that outputs a voltage obtained by full-wave rectifying the AC voltage between the other end of the first inductor and the second output terminal.
A control unit that controls the switching operation of the switch element,
Equipped with
The control unit
When the difference between the DC voltage and the absolute value of the voltage full-wave rectified by the full-wave rectifier circuit becomes smaller than the threshold value, switching operation stop control for stopping the switching operation of the switch element is performed. When the difference becomes equal to or greater than the threshold value, the switching operation restart control for restarting the switching operation of the switch element is performed.
It is characterized by that.

The power factor improving circuit of one aspect of the present invention is
A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor connected between the first input terminal and the first node, a first switch element connected between the first node and the first output terminal, and One or more first arm circuits having at least a second switch element connected between the first node and the second output terminal.
A third switch element connected between the second input terminal and the first output terminal, and a fourth connected between the second input terminal and the second output terminal. Polarity switching arm with at least the switch element of
A second inductor connected between the first input terminal and the second node, a fifth switch element connected between the second node and the first output terminal, and a fifth switch element. One or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal.
A control unit that controls the switching operation of the first to sixth switch elements, and
Equipped with
The control unit
When the difference between the DC voltage and the absolute value of the AC voltage becomes smaller than the threshold value, switching operation stop control for stopping the switching operation of the first to sixth switch elements is performed, and the difference. When is equal to or greater than the threshold value, switching operation restart control for restarting the switching operation of the first to sixth switch elements is performed.
It is characterized by that.

In the power factor improvement circuit
The control unit
When the difference becomes smaller than the first threshold value, the switching operation stop control is performed, and when the difference becomes greater than or equal to the second threshold value, the switching operation restart control is performed.
It is characterized by that.

The control method of the power factor improving circuit according to one aspect of the present invention is as follows.
A pair of first input terminals and a second input terminal to which an AC voltage is input, a pair of first output terminals and a second output terminal to output a DC voltage, the first output terminal and the first output terminal. An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, the first node and the first output terminal. A first switch element connected to and one or more arm circuits having at least a second switch element connected between the first node and the second output terminal, and the above. A third switch element connected between the second input terminal and the first output terminal, and a fourth switch element connected between the second input terminal and the second output terminal. It is a control method of a power factor improvement circuit including a polarity switching arm circuit having at least a switch element and a control unit for controlling the switching operation of the first to fourth switch elements.
When the difference between the DC voltage and the absolute value of the AC voltage becomes smaller than the threshold value by the control unit, the switching operation stop control for stopping the switching operation of the first to fourth switch elements. When the difference becomes equal to or greater than the threshold value, the switching operation restart control for restarting the switching operation of the first to fourth switch elements is performed.
It is characterized by that.

The control method of the power factor improving circuit according to one aspect of the present invention is as follows.
A pair of first input terminals and a second input terminal to which an AC voltage is input, a pair of first output terminals and a second output terminal to output a DC voltage, the first output terminal and the first output terminal. An output capacitor connected between the two output terminals, a first inductor with one end connected to the first node, and a rectifier connected between the first node and the first output terminal. The first one includes an element, one or more arm circuits having at least a switch element connected between the first node and the second output terminal, and a voltage obtained by full-wave rectifying the AC voltage. A control method for a power factor improving circuit including a full-wave rectifier circuit that outputs between the other end of the inductor and the second output terminal, and a control unit that controls the switching operation of the switch element.
When the difference between the DC voltage and the absolute value of the voltage rectified by the full-wave rectifier circuit by the control unit becomes smaller than the threshold value, switching to stop the switching operation of the switch element. The operation stop control is performed, and when the difference becomes equal to or larger than the threshold value, the switching operation restart control for restarting the switching operation of the switch element is performed.
It is characterized by that.

The control method of the power factor improving circuit according to one aspect of the present invention is as follows.
A pair of first input terminals and a second input terminal to which an AC voltage is input, a pair of first output terminals and a second output terminal to output a DC voltage, the first output terminal and the first output terminal. An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, the first node and the first output terminal. One or more first arm circuits having at least a first switch element connected to and a second switch element connected between the first node and the second output terminal. And a third switch element connected between the second input terminal and the first output terminal, and connected between the second input terminal and the second output terminal. A polarity switching arm having at least a fourth switch element, a second inductor connected between the first input terminal and the second node, the second node and the first output terminal. A fifth switch element connected in between, and one or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal. A control method for a power factor improving circuit including a control unit for controlling the switching operation of the first to sixth switch elements.
When the difference between the DC voltage and the absolute value of the AC voltage becomes smaller than the threshold value by the control unit, the switching operation stop control for stopping the switching operation of the first to sixth switch elements. When the difference becomes equal to or greater than the threshold value, the switching operation restart control for restarting the switching operation of the first to sixth switch elements is performed.
It is characterized by that.

The power factor improving circuit and the control method of the power factor improving circuit according to one aspect of the present invention have an effect that the cumulative increase of the current flowing through the inductor can be suppressed.

FIG. 1 is a diagram showing a circuit configuration of a power factor improving circuit according to the first embodiment. FIG. 2 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. FIG. 3 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. FIG. 4 is a diagram showing an equivalent circuit of the power factor improving circuit of the first embodiment. FIG. 5 is a diagram showing an example of the waveform of the equivalent circuit of the power factor improving circuit of the first embodiment. FIG. 6 is a diagram showing an equivalent circuit of the power factor improving circuit of the first embodiment. FIG. 7 is a diagram showing an example of the waveform of the equivalent circuit of the power factor improving circuit of the first embodiment. FIG. 8 is a diagram showing a waveform of a comparative example. FIG. 9 is a diagram showing an example of the waveform of the power factor improving circuit according to the first embodiment. FIG. 10 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. FIG. 11 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. FIG. 12 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. FIG. 13 is a diagram showing an example of the waveform of the power factor improving circuit according to the first embodiment. FIG. 14 is a diagram showing a circuit configuration of the power factor improving circuit according to the second embodiment. FIG. 15 is a diagram showing a circuit configuration of the power factor improving circuit according to the third embodiment. FIG. 16 is a diagram showing an example of the waveform of the power factor improving circuit according to the third embodiment.

Hereinafter, embodiments of the power factor improving circuit of the present invention will be described in detail with reference to the drawings. The present invention is not limited to this embodiment.

(First Embodiment)
FIG. 1 is a diagram showing a circuit configuration of a power factor improving circuit according to the first embodiment. Power factor correction circuit 1, AC (e.g., 50 Hz or 60Hz) supplied with the input voltage _{V in} from the power supply 2 and outputs an output voltage _{V out} is higher than the input voltage _{V in} direct current to the load 4, the booster circuit Is. In this embodiment, the effective value of the input voltage _{V in} is assumed to be 200V, the target voltage of the output voltage _{V out} is assumed to be 400V. In other words, the power factor correction circuit 1 is supplied with the input voltage _{V in} effective value 200V, and outputs an output voltage _{V out} of 400V.

A noise filter 3 is provided between the power supply 2 and the power factor improving circuit 1. The noise filter 3 is a filter that mainly suppresses common mode noise. The noise filter 3 includes a first cross-the-line capacitor 31, a common mode filter 32, and a second cross-the-line capacitor 33. In the common mode filter 32, the first winding 32a and the second winding 32b are wound around the core 32c (for example, a ferrite core or an amorphous core) in the same direction.

Both ends of the first cross-the-line capacitor 31 are connected to both ends of the power supply 2, respectively. One end of the first winding 32a of the common mode filter 32 is connected to one end of the first cross-the-line capacitor 31. One end of the second winding 32b of the common mode filter 32 is connected to the other end of the first cross-the-line capacitor 31. One end of the second cross-the-line capacitor 33 is connected to the other end of the first winding 32a of the common mode filter 32. The other end of the second cross-the-line capacitor 33 is connected to the other end of the second winding 32b of the common mode filter 32.

The common mode noise flows in the same direction in the first winding 32a and the second winding 32b. Therefore, the magnetic fluxes generated inside the core 32c also have the same direction and strengthen each other. As a result, the impedance of the common mode filter 32 becomes large. As a result, the noise filter 3 can suppress common mode noise.

Power factor correction circuit 1 includes a first input terminal 11 and the second input terminal 12 of the input voltage V _in is supplied. Power factor correction circuit 1 includes a first voltage detector 13 for detecting an input voltage V _in. The first voltage detector 13 is connected between the first input terminal 11 and the second input terminal 12.

The power factor improving circuit 1 includes a first output terminal 14 and a second output terminal 15 that output an _{output voltage V out.} The power factor improving circuit 1 includes an output capacitor C _{1 for smoothing the output voltage V out} . The output capacitor C ₁ is connected between the first output terminal 14 and the second output terminal 15. Further, the power factor improving circuit 1 includes a second voltage detector 16 that detects the _{output voltage V out.} The second voltage detector 16 is connected between the first output terminal 14 and the second output terminal 15.

A load 4 is connected between the first output terminal 14 and the second output terminal 15. The load 4 is exemplified by, but is not limited to, a DC-DC converter that converts an _{output voltage V out to a different DC voltage.}

Power factor correction circuit 1 includes a first inductor L _1. The first end of the inductor L ₁ is connected to a first input terminal 11. The first end of the inductor L ₁ is connected to the first node N _1.

Power factor correction circuit 1 includes first and second switching elements (for example, N-channel field effect transistor (MOSFET)) the _{Q 1} and _{Q 2.} The first node N _1, the first source of the switch element Q ₁ - through the drain path, and is connected to the first output terminal 14. Further, the first node N ₁ is connected to the second output terminal 15 via the drain-source path of the second switch element Q _2.

The first inductor L ₁ and the first and second switch elements Q ₁ and Q _{2 form} the arm circuit 17.

In the present embodiment, the power factor improving circuit 1 includes one arm circuit 17, but the present embodiment is not limited to this. Power factor correction circuit 1 is connected in parallel, is controlled by the first and second gate pulse signals P ₁ and P _2, it may include two or more arm circuit 17.

The arm circuit 17 has included a first switching element to Q ₁ high side one is not limited to this. The arm circuit 17 may include two or more high-side switch elements in which source-drain paths are connected in parallel _{and controlled by a first gate pulse signal P1.} The arm circuit 17 is includes a second switching element Q ₂ of one of the low side, but is not limited thereto. The arm circuit 17 may include two or more low-side switch elements in which source-drain paths are connected in parallel _{and controlled by a second gate pulse signal P2.} The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Power factor correction circuit 1 includes a third and fourth switching elements _{Q 3} and _{Q 4.} The second input terminal 12, the source of the third switching element Q ₃ - via the drain path is connected to the first output terminal 14. The second input terminal 12, the drain of the fourth switching element Q ₄ - via the source path is connected to the second output terminal 15.

Third and fourth switching elements _{Q 3} and _{Q 4} constitute a polarity switching arm circuit 18.

Polarity switching arm circuit 18 has included one third switching element Q ₃ of the high side, but is not limited thereto. The polarity switching arm circuit 18 may include two or more high-side switch elements in which source-drain paths are connected in parallel _{and controlled by a third gate pulse signal P3.} The polarity switching arm circuit 18 has included a fourth switching element Q ₄ of one of the low side, but is not limited thereto. The polarity switching arm circuit 18 may include two or more low-side switch elements in which source-drain paths are connected in parallel _{and controlled by a fourth gate pulse signal P4.} The number of high-side switch elements and the number of low-side switch elements are preferably the same.

In this embodiment, although the first switching element Q ₁ to the fourth switching element Q ₄ is as it is N-channel type MOSFET, but is not limited thereto. From the first switching element _{Q 1} to the fourth switching element _{Q 4,} silicon power devices, GaN power devices, SiC power devices, IGBT (Insulated Gate Bipolar Transistor) or the like.

The first switch element Q ₁ to the fourth switch element Q _{4 each} have a first parasitic diode (body diode) D ₁ to a fourth parasitic diode D ₄ . The parasitic diode is a pn junction between the back gate of the MOSFET and the source and drain. The first parasitic diode D ₁ to the fourth parasitic diode D ₄ are freewheels for releasing the transient counter electromotive force when the first switch element Q ₁ to the fourth switch element Q _{4 are off.} It can be used as a diode.

The power factor improving circuit 1 includes a control unit 50. The control unit 50 can be realized by using a CPU (Central Processing Unit) and a program.

Control unit 50, depending on the polarity of the input voltage V _in, the gate of the first switching element Q ₁ to the fourth switching element Q ₄ - by controlling the voltage between the source, the first switching element Q controlling the switching operation from _one to the fourth switching element Q _4. Control unit 50, PWM (Pulse Width Modulation) is a signal, a first gate pulse signal from _{P 1} to the fourth gate pulse signal _{P 4,} first the switch element _{Q 1} the fourth switching element _{Q 4} Output to each of the gates up to. Note that the first gate pulse signals P ₁ to the fourth gate pulse signal P _4, the dead time t _{d (see} FIG. 2) is set. The dead time t _d is exemplified, but is not limited to about 1 ns to 10 ns.

Control unit 50, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} and if the difference is smaller than the first threshold value _{V deff1's} first fourth from the switch element _{Q 1} performing a switching operation stop control for stopping the switching operation of the up switch element Q _{4. Further, when the difference between the output voltage V out} and the absolute value | V _in | of the input voltage V _{in becomes equal to} or more than the second threshold value V def2, the control unit 50 first switches from the _{first switch element Q1 to the first.} The switching operation restart control for restarting the switching operation up to the switch element Q4 of _{4 is performed.}

The control unit 50 includes a first threshold storage unit 51, a second threshold storage unit 52, a determination unit 53, and a driving unit 54.

The first threshold value storage unit 51 stores the first threshold value V _def1 . The first threshold value V _def1 may be rewritable via wired communication or wireless communication. The first threshold value V _def1 is exemplified by, but is not limited to, 50V.

The second threshold value storage unit 52 stores the second threshold value V _def2 . The second threshold value V _def2 may be rewritable via wired communication or wireless communication. The second threshold value V _def2 is preferably a value larger than the first threshold value V _def1. The second threshold value V _def2 is exemplified by, but is not limited to, 60V.

Determining unit 53, when starting the power factor correction circuit 1, the first from the switch element to Q ₁ for performing a switching operation from the fourth switching element Q _4, the high-level decision signals S ₁ the driving unit 54 Output to.

Determining unit 53, an output voltage _{V out,} the absolute value of the input voltage _{V in |} computing and the difference | _{V in.} Then, the determination unit 53, the absolute value of the output voltage _{V out} and the input voltage _{V in |} comparing the difference between, and the first threshold value _{V deff1,} the | _{V in.} Determination unit 53 outputs the absolute value of the voltage _{V out} and the input voltage _{V in | V in |} and if the difference is smaller than the first threshold value _{V deff1's} first fourth from the switch element _{Q 1} outputs for stopping the switching operation of the up switch element Q _4, the decision signals S ₁ of low level to the drive unit 54.

The determination unit 53, the absolute value of the output voltage _{V out} and the input voltage _{V in |} comparing the difference between, and the second threshold value _{V Deff2,} the | _{V in.} Determining unit 53, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} difference between the if it becomes the second threshold value _{V Deff2} above, the first switching element to _{Q 1} 4 for restarting the switching operation to switching element Q _4, and outputs the judgment signals S ₁ at a high level to the drive unit 54.

Driving unit 54, the determination signals _{S 1} supplied from the determining unit 53 in the case of high level, so that the output voltage _{V out} is equal to the target voltage (400V), from the first switch element to _{Q 1} 4 controls the up switch element _{Q 4.} Specifically, the drive unit 54 from the first gate pulse signals P ₁ to the fourth gate pulse signal P _4, the gate of the first switching element Q ₁ to the fourth switching element Q _4, Output each.

Specifically, the drive unit 54, the input voltage V _in detected by the first voltage detector 13, the output voltage V _out which is detected by the second voltage detector 16, based on the first and second and second gate pulse signals P ₁ and P ₂ of the frequency (switching frequency), the on-time, the computing. Driving unit 54, the calculated frequency, and on-time, based on, of the first and second gate pulse signals P ₁ and P _2, the first and second gates of the switching elements Q ₁ and Q ₂ , Output each.

Driving unit 54, the determination signals S ₁ supplied from the determining unit 53 in the case of low level, from the first gate pulse signal P ₁ of the low level to the fourth gate pulse signal P _4, the first to the gate of the switching element Q ₁ to the fourth switching element Q _4, respectively output. Thus, from the first switching element Q ₁ to the fourth switching element Q _4, turned off.

The control during the switching operation of the control unit 50 will be described.

The arm circuit 17 has a circuit configuration similar to that of the boost chopper circuit. Therefore, the power factor improving circuit 1 operates in the same manner as the boost chopper circuit.

More specifically, the control unit 50, when the polarity of the input voltage V _in is positive phase (V _in ≧ 0) turns off the third switching element Q ₃ polarity switching arm circuit 18 and the Turn on the switch element Q4 of ₄ .

Then, the control unit 50, the third switching element Q ₃ off to state and turned on the fourth switch element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / Control to switch off.

For example, the control unit 50, when the input voltage _{V in} is positive phase, the second and fourth switching elements _{Q 2} and _{Q 4} turns on the and first and third switching elements _{Q 1} and _{Q 3} from a first state in which the off-controls the second state of turning off the second switching element Q _2.

Next, the control unit 50, from the second state to control the third state in which the on-first switching element Q _1.

Next, the control unit 50, from the third state, and controls the fourth state in which off the first switching element Q _1.

Next, the control unit 50, the fourth state is controlled to a fifth state in which the on-second switching element Q _2.

On the other hand, the control unit 50, when the polarity of the input voltage V _in is reversed phase (V _{in <0)} turns on the third switching element Q ₃ polarity switching arm circuit 18 and the fourth switch to turn off the element _{Q 4.}

Then, the control unit 50, the third switching element Q ₃ at ON and state and turning off the fourth switching element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / Control to switch off.

The polarity of the input voltage V _in when it is reversed phase, specific operation of controlling so that the first and second switching elements Q ₁ and Q ₂ switches the complementarily turned on / off, the above input voltage V _in is the same as the control from the first state when a positive phase to a fifth state.

FIG. 2 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. 2, when the polarity of the input voltage V _in is positive phase, the power factor correction circuit 1 during switching operation control, the second gate pulse signal P is supplied to the second gate of the switching element Q ₂ it is a diagram illustrating an example of ₂ and the first of the first gate pulse signal P ₁ of the waveform supplied to the gate of the switching element Q _1.

Control unit 50, when the input voltage V _in is positive phase, turns off the second and fourth switching elements Q ₂ and Q ₄ turns on the and first and third switching elements Q ₁ and Q ₃ Control to the first state.

Next, the control unit 50, from the first state to control a second state in which turning off the second switching element Q _{2. The time T 0} from the first state to the second state is the on time of the _second switch element Q2.

Next, the control unit 50, after the dead time t _d has elapsed from the second state to control the third state in which the on-first switching element Q _1.

Next, the control unit 50, from the third state, and controls the fourth state in which off the first switching element Q _{1. The time T 1} from the third state to the fourth state is the on time of the _first switch element Q1.

Next, the control unit 50, after the dead time t _d has elapsed from the fourth state is controlled to a fifth state in which the on-second switching element Q _2.

The control unit 50 subsequently executes the same control.

Referring again to FIG. 1, when the input voltage V _in is positive phase, the first switching element Q ₁ is, the direction of the current I _Q1 flowing from the first node N ₁ to the first output terminal 14 flow, interrupting the direction of current flowing from the first output terminal 14 to the first node N _1, which is equivalent to the rectifying elements.

FIG. 3 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. 3, the second gate pulse signal P ₂ to be supplied to the second gate of the switching element Q _2, the drain of the second switching element Q ₂ - source voltage V _Q2, the first inductor L ₁ It is a figure which shows the waveform of the current I _L1 flowing through, the drain current I _{Q2 of a second} switch element Q2, and the _{current I Q1} flowing through a _{first switch element Q1.}

Note that FIG. 3 omits the illustration of the _{dead time t d.}

When the second switch element Q ₂ is in the ON state, a current flows in the path of power supply 2 → first inductor L ₁ → second switch element Q _{2 → power supply 2.} Therefore, _IL1 = _IQ2 .

When the second switch element Q ₂ is in the off state, a current flows through the path of the power supply 2 → the first inductor L ₁ → the first switch element Q _{1 → the first output terminal 14.} Therefore, _IL1 = _IQ1 .

FIG. 4 is a diagram showing an equivalent circuit of the power factor improving circuit of the first embodiment. 4, the input voltage V _in is positive phase and the second switching element Q ₂ is a diagram illustrating a case of ON state, the equivalent circuit of the power factor correction circuit 1.

Relationship between the first voltage _{V L1} and the current _{I L1} of inductor _{L 1} is expressed by the following equation (1). In equation (1), t is time.

In the case shown in FIG. _4, a _V L1 ₌ V _in. Considering the directions of the voltage _VL1 and the current _{IL1 , the current IL1} is expressed by the following equation (2).

Accordingly, the waveform of the current _{I L1} is the gradient becomes a linear _V in / _{L 1.} In other words, the waveform of the current _{I L1} is dependent on the input voltage _{V in,} it does not depend on the output voltage _{V out.}

FIG. 5 is a diagram showing an example of the waveform of the equivalent circuit of the power factor improving circuit of the first embodiment. 5, the input voltage V _in is positive phase and the second switching element Q ₂ is a diagram illustrating a case of ON state, the first waveform of the current I _L1 of inductor L _1. The waveform of the current _{I L1} is the gradient becomes a linear _V in / _{L 1.}

FIG. 6 is a diagram showing an equivalent circuit of the power factor improving circuit of the first embodiment. 6, the input voltage V _in is positive phase and the second switching element Q ₂ is a diagram showing the case in the OFF state, an equivalent circuit of the power factor correction circuit 1.

In the case shown in FIG. _6, a V _{L1 =} V out _{-V in.} Considering the directions of the voltage _VL1 and the current _{IL1 , the current IL1} is expressed by the following equation (3). In the equation (3), I _p is an initial value of the current IL _{1 when the second} switch element Q 2 is turned off.

Accordingly, the waveform of the current _{I L1,} slope _- becomes _{(V out -V in) / L} 1 of the straight line. That is, the waveform of the _{current IL1} depends on the _{input voltage V in} and the output voltage V _out.

FIG. 7 is a diagram showing an example of the waveform of the equivalent circuit of the power factor improving circuit of the first embodiment. 7, the input voltage V _in is positive phase and the second switching element Q ₂ is a diagram showing the case in the OFF state, the first waveform of the current I _L1 of inductor L _1. The waveform of the current _{I L1} is slope _- becomes _{(V out -V in) / L} 1 of the straight line.

Referring again to FIG. 3, when the second switching element _{Q 2} is on, current _I L1 _{(= I Q2)} is the slope increases linearly in _V in / _{L 1.} On the other hand, when the second switching element _{Q 2} is off, current _I L1 _{(= I Q1)} is slope _- reduced to _{(V out -V in) / L} 1 of the straight line.

As shown in FIG. 3, the control unit 50 controls the current critical mode. Current critical mode, a current continuous mode for continuously without interruption of current I _L1, a current discontinuous mode in which current I _L1 is interrupted, a mode of the boundary. However, the control unit 50, the current I _L1 is without lead to 0A, When the second switching element Q ₂ in the predetermined time has elapsed from off to forcibly turn on the second switching element Q _2. This is because if the current _IL1 is continuously waiting to reach 0 A, the boosting operation will be stopped during the waiting period.

[Comparison example]
As shown in equation _(3), if _(V out _{-V in)} is small, that is, when the _{V out} ≒ _{V in} has a smaller slope current _{I L1} is decreased. That is, it takes a long time for _{the current IL1 to decrease.} When (V _out −V _in ) is small, the time when the power factor improving circuit 1 is started is exemplified, but the present invention is not limited to this.

FIG. 8 is a diagram showing a waveform of a comparative example. _{8, V} where _out is a ≒ _{V in,} the second gate pulse signal _{P 2} to be supplied to the second gate of the switching element _{Q 2,} the drain of the second switching element _{Q 2} - source voltage shows a V _Q2, the first current _{I L1} flowing through the inductor _{L 1,} a second drain current _{I Q2} of the switching element _{Q 2,} the first current _{I Q1} flowing through the switching element _{Q 1,} the waveform Is.

Note that FIG. 8 omits the illustration of the _{dead time t d.}

_{In the first state in which the second} switch element Q2 is in the ON state, _IL1 = _IQ2 . The slope of the waveform of the current _I L1 _{(= I Q2) is} a V in / _{L 1.}

In the third state in which the second switch element Q ₂ is in the off state _{after the lapse of time T 2 from the first state, IL1} = _IQ1 . The slope of the waveform of the current _I L1 _{(= I Q1) is} - _{(V out -V in) / L} 1.

If _(V out _{-V in)} is small, ie, in the case of _{V out} ≒ _{V in} it does not decrease the current _{I L1} almost. However, as described above, the control unit 50 forces the _second switch element Q _{2 after a predetermined time T 3} has elapsed from the turning off of the second switch element Q _{2 even if the current IL 1 does not reach 0 A.} Turn on.

The time T ₃ may be calculated from the time T ₄ of the switching period until the next second switching element Q ₂ is turned on after the second switching element Q ₂ is turned on. That is, the time T ₄ may be predetermined and the time T ₃ may be calculated by _{T 3} = T _{4 −} T _2. The time T ₄ is exemplified, but is not limited to several tens of ms (milliseconds) to several hundred ms. As an example, the time T ₄ is exemplified by about 40 ms to 100 ms.

The third state since by the time _{T 3} after, in a first state the second switching element _{Q 2} is turned _on, it is _I L1 ₌ I _Q2. The slope of the waveform of the current _I L1 _{(= I Q2) is} a V in / _{L 1.} Thus, before the current I _L1 is decreased sufficiently in a time T _3, the second switching element Q ₂ is in the on-state during the time T _5, current I _L1 increases further. Similarly thereafter, by the second on-off switching element Q ₂ is repeated, the current I _L1 is increased cumulatively, a first magnetic saturation and inductor L _1, the second breakdown of the switching element Q ₂ May invite.

[Operation of the first embodiment]
The present inventor has an output voltage V _out and an input voltage V _in when the effective value of the input voltage V _in is 200 V and the switching period of the first and second switch elements Q ₁ and Q ₂ is 40 ms. the absolute value | V _{in |} if the difference between at least about 50 V, found that it is possible to reduce the current I _L1 suitably. In other words, if the effective value is 200V and the first and second switching cycle of the switching elements _{Q 1} and _{Q 2} of the input voltage _{V in} is 40 ms, the absolute value of the output voltage _{V out} and the input voltage _{V in} It has been found that if the difference from | V _in | is smaller than about 50 V, the current _IL1 cannot be suitably reduced.

_{Therefore, when the difference between the output voltage V out} and the absolute value | V _in | of the input voltage V _in becomes smaller than the first threshold value V _def1 (= 50V), the control unit 50 sets the first switch. The switching operation stop control for stopping the switching operation from the element Q ₁ to the fourth switch element Q _{4 is performed.} The control unit 50, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} when the difference between the reaches the second threshold value _{V deff2} (= 60V) or more, the first switch element performing a switching operation restart control to restart the switching operation from Q ₁ to the fourth switching element Q _4.

The control unit 50, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} when the difference between the became the first threshold value _V deff1 (= 50V) or more, performs the switching operation restart control It's fine as a matter of fact. In this case, the second threshold storage unit 52 becomes unnecessary. However, in this case, ripples and the input voltage V _in and the output voltage V _out, due like the detection accuracy of the first voltage detector 13 and second voltage detector 16, and the resumption and stop switching operation , May be repeated in small steps. Therefore, the control unit 50, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} when the difference between the reaches the second threshold value _{V deff2} (= 60V) or more, performs the switching operation restart control That is preferable.

FIG. 9 is a diagram showing an example of the waveform of the power factor improving circuit according to the first embodiment. FIG. 9 shows the gate of the _{second switch element Q2 when the difference between the output voltage V out} and the absolute value | V _in | of the input voltage V _in | is equal to or greater than the first threshold value V _{def1 (= 50V).} the second gate pulse signal _{P 2} to be supplied, the drain of the second switching element _{Q 2} - source voltage _{V Q2,} the current _{I L1} flowing in the first inductor _{L 1,} the second switching element _{Q 2} and the drain current _{I Q2} of the first current _{I Q1} flowing through the switching elements _{Q 1,} is a diagram showing the waveform.

Note that FIG. 9 omits the illustration of the _{dead time t d.}

_{In the first state in which the second} switch element Q2 is in the ON state, _IL1 = _IQ2 . The slope of the waveform of the current _I L1 _{(= I Q2) is} a V in / _{L 1.}

In the first state since by the time _{T 6} after, in the third state the second switching element _{Q 2} is in the OFF _state, an _I L1 ₌ I _Q1. The slope of the waveform of the current _I L1 _{(= I Q1) is} - _{(V out -V in) / L} 1.

As shown in FIG. 9, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} when the difference between the is the first threshold value _V deff1 (= 50V) or more, that _(V out _{-V in)} When ≧ 50, the current _IL1 is preferably reduced. In the third state to become in time _{T 7} elapses after the current _{I L1} reaches the 0A. As a result, the control unit 50 can perform the current critical mode. The sum of the time T ₆ and the time T ₇ is the switching period T ₈ (for example, about 40 ms to 100 ms).

FIG. 10 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. 10, in the positive-phase period of the input voltage _{V in,} the peak value of the input voltage _{V in} (e.g., 283V) and when the output voltage _{V out} is substantially equal to an input voltage _{V in,} the output voltage _{V out,} and current _{I L1} flowing first inductor _{L 1,} is a diagram showing the waveform.

Rising start of the period of the input voltage V _in 71 is a switching operation period to perform the switching operation from the first switching element Q ₁ to the fourth switching element Q _4. Period 71, the absolute value of the output voltage _{V out} and the input voltage _{V in |} a period difference is the first threshold value _{V deff1} more and | _{V in.}

Next period of time 71 72 from the first switch element Q ₁ to the fourth switching element Q ₄ does not perform the switching operation is a switching inoperative period. At the beginning of period 72, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} difference _{V 0} which A, first threshold value _{V deff1} smaller. At the end of the period 72, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} difference between the second threshold value _{V Deff2} smaller.

Following the second period of time 72 71 is a switching operation period to resume the switching operation from the first switching element Q ₁ to the fourth switching element Q _4. The second period 71, the absolute value of the output voltage _{V out} and the input voltage _{V in |} a period difference is the second threshold value _{V Deff2} more and | _{V in.} At the start of the second period 71, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} difference _{V 1} of the and is the second threshold value _{V Deff2} more.

FIG. 11 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. Figure 11 is the positive phase period of the input voltage _{V in,} when the difference between the peak value of the input voltage _{V in} and the output voltage _{V out} is the first threshold value _{V deff1} smaller than _(e.g., V out = 300 V), the input the voltage _{V in,} the output voltage _{V out,} the first current _{I L1} flowing through the inductor _{L 1,} is a diagram showing the waveform.

Rising start of the period of the input voltage V _in 71 is a switching operation period to perform the switching operation from the first switching element Q ₁ to the fourth switching element Q _4. Period 71, the absolute value of the output voltage _{V out} and the input voltage _{V in |} a period difference is the first threshold value _{V deff1} more and | _{V in.}

Next period of time 71 72 from the first switch element Q ₁ to the fourth switching element Q ₄ does not perform the switching operation is a switching inoperative period. At the beginning of period 72, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} difference _{V 2} between the first threshold value _{V deff1} smaller. At the end of the period 72, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} difference between the second threshold value _{V Deff2} smaller.

Following the second period of time 72 71 is a switching operation period to resume the switching operation from the first switching element Q ₁ to the fourth switching element Q _4. The second period 71, the absolute value of the output voltage _{V out} and the input voltage _{V in |} a period difference is the second threshold value _{V Deff2} between | _{V in.} At the start of the second period 71, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} difference _{V 3} between is the second threshold value _{V Deff2} more.

In FIG. 11, the period 72, which is the switching non-operation period, is shorter than that in FIG. This is because the output voltage V _out is high.

FIG. 12 is a diagram showing an example of a waveform of the power factor improving circuit according to the first embodiment. 12, the positive-phase period of the input voltage _{V in,} when the difference between the peak value of the input voltage _{V in} and the output voltage _{V out} is the first threshold value _{V deff1} more _(e.g., V out = 400V), the input voltage _{V in,} the output voltage _{V out,} the current _{I L1} flowing in the first inductor _{L 1,} is a diagram showing the waveform.

Overall a is the period of the positive-phase period of the input voltage V _in 71 is a switching operation period to perform the switching operation from the first switching element Q ₁ to the fourth switching element Q _4. Period 71, the absolute value of the output voltage _{V out} and the input voltage _{V in |} a period difference is the first threshold value _{V deff1} more and | _{V in.} During the peak of the input voltage _{V in,} the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} difference _{V 4} and is the first threshold value _{V deff1} more.

In FIG. 12, as compared with FIGS. 10 and 11, the switching non-operating period 72 is eliminated. This is because the output voltage _{V out} is higher, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} difference between is because there is no be less than the first threshold value _{V deff1} ..

FIG. 13 is a diagram showing an example of the waveform of the power factor improving circuit according to the first embodiment. 13, the power factor correction circuit 1 of the startup, the input voltage V _in and a second gate pulse signal P ₂ to be supplied to the second gate of the switching element Q _2, the second switching element Q ₂ It is a figure which shows the waveform of the drain-source voltage V _{Q2 of.}

Since the output voltage V _out according periodicity progresses the input voltage V _in increases, as shown in FIG. 13, and decrease period 72 is a switching non operation period, a period 71 which is a switching operation period is increased. Then, the third cycle of the second half of the input voltage V _in (reverse-phase period of the third period), missing the period 72 is a switching inoperative period.

As described above, the power factor correction circuit 1, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} if the difference between is smaller than the first threshold value _{V deff1} the first switch The switching operation stop control for stopping the switching operation from the element Q ₁ to the fourth switch element Q _{4 is performed.}

Thus, the power factor correction circuit 1, possible for the first inductor L ₁ of the current I _L1 is cumulatively increased, causing the magnetic saturation and the first inductor L _1, the second breakdown of the switching element Q ₂ Sex can be suppressed.

Further, power factor improvement circuit 1, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} if the difference reaches the second threshold value _{V Deff2} above and includes a first switching element _{Q 1} a fourth switching operation restart control to restart the switching operation to switching element Q ₄ from performing.

Thus, the power factor correction circuit 1, the ripple and the input voltage V _in and the output voltage V _out, due like the detection accuracy of the first voltage detector 13 and second voltage detector 16, the switching operation It is possible to suppress the possibility that the stop and restart are repeated in small steps.

(Second embodiment)
FIG. 14 is a diagram showing a circuit configuration of the power factor improving circuit according to the second embodiment. The same components as those in the first embodiment are designated by the same reference numbers, and the description thereof will be omitted.

Power factor improvement circuit 1A, includes a full-wave rectifier circuit 61 for full-wave rectifying the input voltage V _in. The full-wave rectifier circuit 61 is exemplified by, but is not limited to, a diode bridge. Full-wave rectifier circuit 61, a voltage obtained by full-wave rectifying the input voltage V _in, one end of the first inductor L _1, a second output terminal 15, and outputs during the. The first end of the inductor L ₁ is connected to the first node N _1.

The first voltage detector 13 detects the voltage rectified by the full wave rectifier circuit 61.

The power factor improving circuit 1A includes a rectifying element D ₇ . The rectifying element D ₇ allows the _{current from the first node N 1} to the first output terminal 14 to pass through, and cuts off the current from the first output terminal 14 to the first node N _1. The rectifying element D ₇ is exemplified by a diode, but the rectifying element D 7 is not limited to this.

Power factor improvement circuit 1A, includes a second switching element _{Q 2.} The first node N ₁ is connected to the second output terminal 15 via the drain-source path of the second switch element Q _2.

The first inductor L ₁ , the rectifying element D _7, and the second switch element Q ₂ constitute the arm circuit 17A.

The arm circuit 17A has a circuit configuration similar to that of the boost chopper circuit.

In the present embodiment, the power factor improving circuit 1A includes one arm circuit 17A, but the present invention is not limited to this. Power factor improvement circuit 1A is connected in parallel and controlled by a second gate pulse signals P _2, it may include two or more arm circuit 17A.

Further, the arm circuit 17A includes, but is not limited to, _{one rectifying element D 7 on the high side.} The arm circuit 17A may include two or more rectifying elements connected in parallel. The arm circuit 17A has included a second switching element Q ₂ of one of the low side, but is not limited thereto. Arm circuit 17A, the source - drain paths connected in parallel and controlled by a second gate pulse signals P _2, it may include two or more switching elements of the low-side. The number of high-side rectifying elements and the number of low-side switch elements are preferably the same.

The power factor improving circuit 1A includes a control unit 50. The control unit 50 can be realized by using a CPU and a program.

Control unit 50, the second gate of the switching element Q ₂ - by controlling the voltage between the source and controls the second switching operation of the switching element Q _2. The control unit 50 outputs the second gate pulse signal P _2, which is a PWM signal, to the gate of the second switch element Q ₂ , respectively.

The power factor improving circuit 1A operates the switching operation of the _second switch element Q2 when _{the difference between the output voltage V out} and the absolute value of the full-wave rectified voltage _{becomes smaller than the first threshold value V def1.} Switching operation to stop the operation Stop control is performed.

Thus, the power factor correction circuit 1A, similar to the power factor correction circuit 1 of the first embodiment, the first inductor L ₁ of the current I _L1 is increased cumulatively, the first inductor L ₁ the possibility of causing magnetic saturation and the second breakdown of the switching element Q ₂ can be suppressed.

Further, power factor improvement circuit 1A, when the difference between the absolute value of the output voltage V _out and the full-wave rectified voltage reaches the second threshold value V _Deff2 above, the second switching of the switching element Q ₂ Switching to restart the operation The operation restart control is performed.

Thus, the power factor correction circuit 1A, similar to the power factor correction circuit 1 of the first embodiment, the ripple and the input voltage V _in and the output voltage V _out, the first voltage detector 13 and the second Due to the detection accuracy of the voltage detector 16, it is possible to suppress the possibility that the switching operation is stopped and restarted in small steps.

(Third embodiment)
FIG. 15 is a diagram showing a circuit configuration of the power factor improving circuit according to the third embodiment. The same components as those in the first embodiment are designated by the same reference numbers, and the description thereof will be omitted.

Power factor correction circuit 1B further includes compared to power factor correction circuit 1 of the first embodiment, the second inductor L _2, a switching element Q ₅ and Q ₆ of the fifth and sixth, the ..

One end of the second inductor L ₂ is connected to the first input terminal 11. The other end of the second inductor L ₂ is connected to the second node N _2. The second node N ₂ is the fifth source of the switch element Q ₅ - through the drain path, and is connected to the first output terminal 14. The second node N _2, the drain of the switching element Q ₆ of the sixth - through the source path is connected to the second output terminal 15.

The second inductor _{L 2,} and the switching elements _{Q 5} and _{Q 6} of the fifth and sixth constitute the second arm circuit 19.

The first arm circuit 17 may be referred to as a master arm or a slave arm. The second arm circuit 19 may be referred to as a slave arm or a master arm.

In the present embodiment, the power factor improving circuit 1B includes one second arm circuit 19, but is not limited thereto. Power factor correction circuit 1B is connected in parallel, it is controlled by the gate pulse signal P ₅ and P ₆ of the fifth and sixth, may include two or more of the second arm circuit 19. The number of the second arm circuit 19 and the number of the first arm circuit 17 are preferably the same.

The second arm circuit 19 has included switching element Q ₅ of one fifth high side, but is not limited thereto. The second arm circuit 19, the source - drain paths connected in parallel, is controlled by the gate pulse signal P ₅ of the fifth, it may contain two or more switching elements of the high side. The second arm circuit 19 has included switching element Q ₆ of the sixth one of the low side, but is not limited thereto. The second arm circuit 19, the source - drain paths connected in parallel, is controlled by the gate pulse signal P ₆ of the sixth, it may contain two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

The fifth switch element Q ₅ and the sixth switch element Q _{6 each} have a fifth parasitic diode D ₅ and a sixth parasitic diode D ₆ . The fifth parasitic diode D ₅ and the sixth parasitic diode D ₆ are used as freewheel diodes for escaping the transient back electromotive force when the fifth switch element Q ₅ and the sixth switch element Q _{6 are off.} It is available.

Input current _{I in} is input to the first input terminal 11, a current _{I L1} flowing in the first arm circuit 17, the current _{I L2} flowing in the second arm circuit 19 is the sum of.

The power factor improving circuit 1B includes a control unit 50. Control unit 50, depending on the polarity of the input voltage V _in, the gate of the first switching element Q ₁ until the switch element Q ₆ of the sixth - by controlling the voltage between the source, the first switching element Q controlling the switching operation from _one to the switch element Q ₆ of the sixth. Control unit 50 is a PWM signal, from the first gate pulse signals _{P 1} to the gate pulse signal _{P 6} of the sixth, the gate of the first switching element _{Q 1} until the switch element _{Q 6} of the sixth, Output each. Note that the first gate pulse signals P ₁ to the gate pulse signal P ₆ of the sixth, the dead time t _d is set.

_{When the difference between the output voltage V out} and the absolute value | V _in | of the input voltage V _in becomes smaller than the first threshold value V _def1 (= 50V), the control unit 50 receives the first switch element Q. performing a switching operation stop control for stopping the switching operation from _one to the switch element Q ₆ of the sixth. The control unit 50, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} when the difference between the reaches the second threshold value _{V deff2} (= 60V) or more, the first switch element performing a switching operation restart control to restart the switching operation from Q ₁ to switch element Q ₆ of the sixth.

Drive unit 54, when performing a switching operation, the input voltage V _in detected by the first voltage detector 13, the output voltage V _out which is detected by the second voltage detector 16, on the basis, first, second, fifth and sixth gate pulse signal _P 1 _of, P 2, _{P 5} and the frequency of the _{P 6} (switching frequency), the on time _{T on-d} (see FIG. 16), the first _{The phase difference time t diff} (see FIG. 16) between the arm circuit 17 and the second arm circuit 19 is calculated. The drive unit 54 has the first, second, fifth and sixth gate pulse signals P ₁ , P ₂ , based on the calculated frequency, the on-time _Ton-d, and the phase difference time t _diff. the P ₅ and _{P 6,} first, the second, switching element to _Q 1 fifth and _6, Q 2, the gate of _{Q 5} and _{Q 6,} respectively output.

The control during the switching operation of the control unit 50 will be described.

Control unit 50, the polarity of the input voltage V _in the case of the positive phase is on the third switching element Q ₃ off and and the fourth of the switching element Q ₄ of polarity switching arm circuit 18.

Then, the control unit 50, the third switching element Q ₃ off to state and turned on the fourth switch element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / while controlling to switch off, and controls so that the switching element Q ₅ and Q ₆ of the fifth and sixth switches the complementarily turned on / off.

For example, the control unit 50, when the input voltage _{V in} is positive-phase, second, fourth and switching element _Q 2, _{Q 4} and _{Q 6} was turned on while the first sixth, third and fifth from a first state in which turning off the switch element Q _1, Q ₃ and Q ₅ of, for controlling the second switching element Q ₂ in the second state in which turned off and and the first switching element Q _1.

Further, the control unit 50, after controlling the second state, the second state is controlled to the third state of turning off the switch element Q ₆ of the sixth.

Then, the control unit 50, after controlling the third state, the third state is controlled to a fourth state in which turns on the switch element Q ₅ of the fifth.

The control unit 50, after controlling the fourth state, the fourth state is controlled to a fifth state in which off the first switching element Q _1.

Then, the control unit 50, after controlling the fifth state, the fifth state, and controls the sixth state of that on the second switching element Q _2.

Further, the control unit 50 controls from the sixth state to the seventh state in which the _{fifth switch element Q5 is turned off after controlling to the sixth state.}

Then, after controlling to the seventh state, the control unit 50 controls from the seventh state to the eighth state in which the _{sixth switch element Q6 is turned on.}

Further, the control unit 50 controls from the eighth state to the ninth state in which the _{second switch element Q2 is turned off after controlling to the eighth state.}

Then, after controlling to the ninth state, the control unit 50 controls from the ninth state to the tenth state in which the _{first switch element Q1 is turned on.}

By the control described above, when the polarity of the input voltage V _in is positive phase currents I _L1 and I _L2, via a fourth switch element Q _4, it will flow to the second input terminal 12 ..

On the other hand, the control unit 50, when the polarity of the input voltage V _in is reversed phase, turns off the third switching element Q ₃ ON and and fourth switching elements Q ₄ of polarity switching arm circuit 18 ..

Then, the control unit 50, the third switching element Q ₃ at ON and state and turning off the fourth switching element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / while controlling to switch off, and controls so that the switching element Q ₅ and Q ₆ of the fifth and sixth switches the complementarily turned on / off.

This control, when the polarity of the input voltage V _in the reverse phase currents I _L1 and I _L2 is allowed to flow to the second input terminal 12 via a third switching element Q _3.

The polarity of the input voltage V _in when it is reversed phase, while controlling to switch complementarily turned on / off first and second switching elements Q ₁ and Q _2, the fifth and sixth specific operations for controlling to switch complementarily turned on / off the switch element Q ₅ and Q ₆ from a first state when the input voltage V _in the above are positive-phase up to the 10 state Similar to control.

FIG. 16 is a diagram showing an example of the waveform of the power factor improving circuit according to the third embodiment. FIG. 16 is a diagram showing an example of an operating waveform of the power factor improving circuit 1B when the polarity of the input voltage Vin is _{in the positive phase.}

Control unit 50, when the input voltage _{V in} is positive-phase, second, fourth and sixth switching element _Q 2, _{Q 4} and _{Q 6} turned on and the first to the third and fifth switch The elements Q ₁ , Q ₃ and Q ₅ are controlled to the first state in which they are turned off. Next, the control unit 50, at the timing _{t 1,} turns off the second switching element _{Q 2.} Next, the control unit 50 at a timing t ₂ after elapse of the dead time t _d from the timing t _1, and controls the second state in which the on-first switching element Q _1.

Next, the control unit 50 at a timing t _3, from the second state to control the third state of turning off the switch element Q ₆ of the sixth. Next, the control unit 50 at a timing t ₄ after the dead time t _d has elapsed from the timing t _3, and controls the fourth state in which turns on the switch element Q ₅ of the fifth. The period from timing t ₂ to timing t _{4 is the phase difference time t diff} between the first arm circuit 17 and the second arm circuit 19.

Next, the control unit 50, at the timing t _5, the fourth state is controlled to a fifth state in which off the first switching element Q _1. The period from timing t ₂ to timing t ₅ is the on-time _Ton-d . Next, the control unit 50, at the timing t ₆ after the dead time t _d has elapsed from the timing t _5, and controls the sixth state of that on the second switching element Q _2. Next, the control unit 50, at the timing t _7, the sixth state of controls to the seventh state of turning off the switching element Q ₅ of the fifth. The period from timing t ₄ to timing t ₇ is the on-time _Ton-d .

Next, the control unit 50 at a timing t ₈ of the dead time t _d after the timing t _7, the seventh state, to control the state of the 8 turns on the switch element Q ₆ of the sixth. Next, the control unit 50 at a timing t _9, the state of the 8 controls the ninth state of turning off the second switching element Q _2. The period from timing t ₆ to timing t ₉ is the on-time _Ton-d . Next, the control unit 50, the dead time _{t d} has elapsed timing _{t 10} after the timing _{t 9,} the ninth state is controlled to a tenth state of the turn on the first switching element _{Q 1.}

The control unit 50 subsequently executes the same control.

Note that the second gate pulse signals P ₂ phases for controlling the second switching element Q _2, the phase and the sixth switch element Q ₆ gate pulse signal P ₆ of the sixth to control the , The phase difference time is shifted by _{t diff.} As well as, the first gate pulse signal P ₁ of the phase to control the first switching element Q _1, the fifth gate pulse signal P ₅ for controlling the switching element Q ₅ of the fifth phase Is deviated by the phase difference time t _diff.

As described above, the power factor improving circuit 1B is an interleave type power factor improving circuit. In the power factor improvement circuit 1B, the phase of the first inductor L ₁ of the current I _L1 and the second inductor L ₂ of the current I _L2 is shifted, the current of one of the inductors, the current of the other inductor It flows in the direction of canceling. Therefore, it is possible to reduce the second across-the Line ripple current of the capacitor 33 and the output capacitor C _1.

Power factor correction circuit 1B, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} if the difference between is smaller than the first threshold value _{V deff1} from the first switching element _{Q 1} The switching operation stop control for stopping the switching operation up to the _sixth switch element Q6 is performed.

Thus, the power factor correction circuit 1B includes a first inductor _{L 1} of the current _{I L1} and the second inductor _{L 2} of the current _{I L2} increases cumulatively, the first inductor _{L 1} and the second inductor L _It is possible to suppress the possibility of causing _{magnetic saturation of 2} and destruction of the second switch element Q 2 and the fourth switch element Q _4.

Further, power factor improvement circuit 1B, the absolute value of the output voltage _{V out} and the input voltage _{V in | V in |} if the difference reaches the second threshold value _{V Deff2} above and includes a first switching element _{Q 1} a sixth switching operation restart control to restart the switching operation to switching element Q ₆ from performing.

Thus, the power factor correction circuit 1, the ripple and the input voltage V _in and the output voltage V _out, due like the detection accuracy of the first voltage detector 13 and second voltage detector 16, the switching operation It is possible to suppress the possibility that the stop and restart are repeated in small steps.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention as well as the invention described in the claims and the equivalent scope thereof.

1, 1A, 1B Power factor improvement circuit 2 Power supply 3 Noise filter 4 Load 11 1st input terminal 12 2nd input terminal 13 1st voltage detector 14 1st output terminal 15 2nd output terminal 16 2nd Voltage detector 17 arm circuit (first arm circuit)
18 Polarity switching arm circuit 19 Second arm circuit 50 Control unit 51 First threshold storage unit 52 Second threshold storage unit 53 Judgment unit 54 Drive unit 61 Full-wave rectifier circuit D ₇ Rectifier element L ₁ First inductor L ₂ First 2 Inductor Q ₁ 1st switch element Q ₂ 2nd switch element Q ₃ 3rd switch element Q ₄ 4th switch element Q ₅ 5th switch element Q ₆ 6th switch element C ₁ Output capacitor N ₁ 1st node N ₂ 2nd node

Claims (7)

A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor connected between the first input terminal and the first node, a first switch element connected between the first node and the first output terminal, and One or more arm circuits having at least a second switch element connected between the first node and the second output terminal.
A third switch element connected between the second input terminal and the first output terminal, and a fourth connected between the second input terminal and the second output terminal. Polarity switching arm circuit with at least the switch element of
A control unit that controls the switching operation of the first to fourth switch elements, and
Equipped with
The control unit
When the difference between the DC voltage and the absolute value of the AC voltage becomes smaller than the threshold value, switching operation stop control for stopping the switching operation of the first to fourth switch elements is performed, and the difference. When is equal to or greater than the threshold value, switching operation restart control for restarting the switching operation of the first to fourth switch elements is performed.
A power factor improvement circuit characterized by this. A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor whose one end is connected to a first node, a rectifying element connected between the first node and the first output terminal, and the first node and the second output. One or more arm circuits having at least a switch element connected between the terminals and
A full-wave rectifier circuit that outputs a voltage obtained by full-wave rectifying the AC voltage between the other end of the first inductor and the second output terminal.
A control unit that controls the switching operation of the switch element,
Equipped with
The control unit
When the difference between the DC voltage and the absolute value of the voltage full-wave rectified by the full-wave rectifier circuit becomes smaller than the threshold value, switching operation stop control for stopping the switching operation of the switch element is performed. When the difference becomes equal to or greater than the threshold value, the switching operation restart control for restarting the switching operation of the switch element is performed.
A power factor improvement circuit characterized by this. A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor connected between the first input terminal and the first node, a first switch element connected between the first node and the first output terminal, and One or more first arm circuits having at least a second switch element connected between the first node and the second output terminal.
A third switch element connected between the second input terminal and the first output terminal, and a fourth connected between the second input terminal and the second output terminal. Polarity switching arm with at least the switch element of
A second inductor connected between the first input terminal and the second node, a fifth switch element connected between the second node and the first output terminal, and a fifth switch element. One or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal.
A control unit that controls the switching operation of the first to sixth switch elements, and
Equipped with
The control unit
When the difference between the DC voltage and the absolute value of the AC voltage becomes smaller than the threshold value, switching operation stop control for stopping the switching operation of the first to sixth switch elements is performed, and the difference. When is equal to or greater than the threshold value, switching operation restart control for restarting the switching operation of the first to sixth switch elements is performed.
A power factor improvement circuit characterized by this. The control unit
When the difference becomes smaller than the first threshold value, the switching operation stop control is performed, and when the difference becomes greater than or equal to the second threshold value, the switching operation restart control is performed. conduct,
The power factor improving circuit according to any one of claims 1 to 3, wherein the power factor is improved. A pair of first input terminals and a second input terminal to which an AC voltage is input, a pair of first output terminals and a second output terminal to output a DC voltage, the first output terminal and the first output terminal. An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, the first node and the first output terminal. A first switch element connected to and one or more arm circuits having at least a second switch element connected between the first node and the second output terminal, and the above. A third switch element connected between the second input terminal and the first output terminal, and a fourth switch element connected between the second input terminal and the second output terminal. It is a control method of a power factor improvement circuit including a polarity switching arm circuit having at least a switch element and a control unit for controlling the switching operation of the first to fourth switch elements.
When the difference between the DC voltage and the absolute value of the AC voltage becomes smaller than the threshold value by the control unit, the switching operation stop control for stopping the switching operation of the first to fourth switch elements. When the difference becomes equal to or greater than the threshold value, the switching operation restart control for restarting the switching operation of the first to fourth switch elements is performed.
A control method for a power factor improvement circuit, which is characterized by the fact that. A pair of first input terminals and a second input terminal to which an AC voltage is input, a pair of first output terminals and a second output terminal to output a DC voltage, the first output terminal and the first output terminal. An output capacitor connected between the two output terminals, a first inductor with one end connected to the first node, and a rectifier connected between the first node and the first output terminal. The first one includes an element, one or more arm circuits having at least a switch element connected between the first node and the second output terminal, and a voltage obtained by full-wave rectifying the AC voltage. A control method for a power factor improving circuit including a full-wave rectifier circuit that outputs between the other end of the inductor and the second output terminal, and a control unit that controls the switching operation of the switch element.
When the difference between the DC voltage and the absolute value of the voltage rectified by the full-wave rectifier circuit by the control unit becomes smaller than the threshold value, switching to stop the switching operation of the switch element. The operation stop control is performed, and when the difference becomes equal to or larger than the threshold value, the switching operation restart control for restarting the switching operation of the switch element is performed.
A control method for a power factor improvement circuit, which is characterized by the fact that. A pair of first input terminals and a second input terminal to which an AC voltage is input, a pair of first output terminals and a second output terminal to output a DC voltage, the first output terminal and the first output terminal. An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, the first node and the first output terminal. One or more first arm circuits having at least a first switch element connected to and a second switch element connected between the first node and the second output terminal. And a third switch element connected between the second input terminal and the first output terminal, and connected between the second input terminal and the second output terminal. A polarity switching arm having at least a fourth switch element, a second inductor connected between the first input terminal and the second node, the second node and the first output terminal. A fifth switch element connected in between, and one or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal. A control method for a power factor improving circuit including a control unit for controlling the switching operation of the first to sixth switch elements.
When the difference between the DC voltage and the absolute value of the AC voltage becomes smaller than the threshold value by the control unit, the switching operation stop control for stopping the switching operation of the first to sixth switch elements. When the difference becomes equal to or greater than the threshold value, the switching operation restart control for restarting the switching operation of the first to sixth switch elements is performed.
A control method for a power factor improvement circuit, which is characterized by the fact that.

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