JP6920124B2 - Power factor improvement circuit and control method of power factor improvement circuit - Google Patents

Description

The present invention relates to a power factor improving circuit and a method for controlling the power factor improving circuit.

Conventionally, there is an interleave type power factor correction circuit (see, for example, Patent Document 1). This conventional power factor improving circuit includes a master arm circuit (which may be referred to as a first arm circuit), a slave arm circuit (which may be referred to as a second arm circuit), and a polarity switching arm circuit. , Equipped with. In this conventional power factor improving circuit, since the currents of the two inductors are out of phase, the current of one inductor flows in the direction of canceling the current of the other inductor. Therefore, the ripple current of the input capacitor and the output capacitor can be reduced.

However, there are the following circumstances near the zero cross of the input voltage. Since the current of each inductor is small, the merit that the currents of the two inductors cancel each other out is small. Therefore, the merit of reducing the ripple current of the input capacitor and the output capacitor is small.

On the other hand, the amount of voltage boost is large, and it is necessary to switch the switch element in a short cycle. Therefore, there is a demerit that the control load is large.

Further, since the switch element is switched in a short cycle, the absolute amount of the switching loss and the gate drive loss of the switch element is large. In addition, the vicinity of the zero cross of the input voltage is a region where the conversion power is small. Therefore, the ratio of the switching loss of the switch element and the gate drive loss to the converted power is high. Therefore, there is a demerit that the power efficiency is lowered.

Japanese Unexamined Patent Publication No. 2015-23606

An object of the present invention is to provide a power factor improving circuit capable of improving power efficiency and a control method for the power factor improving circuit.

The power factor improving circuit of one aspect of the present invention is
A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor connected between the first input terminal and the first node, a first switch element connected between the first node and the first output terminal, and One or more first arm circuits having at least a second switch element connected between the first node and the second output terminal.
A third switch element connected between the second input terminal and the first output terminal, and a fourth connected between the second input terminal and the second output terminal. Polarity switching arm with at least the switch element of
A second inductor connected between the first input terminal and the second node, a fifth switch element connected between the second node and the first output terminal, and One or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal.
A control unit that controls the switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage.
With
The control unit
The input current input to the first input terminal is compared with the threshold value, and when the input current is larger than the threshold value, both the first arm circuit and the second arm circuit are operated. Double arm control is performed, and when the input current is equal to or less than the threshold value, single arm control for operating only the first arm circuit is performed.
It is characterized by that.

In the power factor improvement circuit
The control unit
The first switch element and the second switch element on time in the single arm control period in which the single arm control is performed are assumed to perform the double arm control in the single arm control period. Twice the on-time of the switch element 1 and the second switch element.
It is characterized by that.

In the power factor improvement circuit
The control unit
The peak value of the input current is calculated based on the instantaneous voltage of the AC voltage and the on-time of the first switch element and the second switch element when the double arm control is performed.
The threshold value is calculated by multiplying the peak value of the input current and a predetermined coefficient.
It is characterized by that.

In the power factor improvement circuit
The coefficient is 0.5.
It is characterized by that.

In the power factor improvement circuit
The control unit
A plurality of the threshold values are calculated by multiplying the peak value of the input current and each of the plurality of predetermined coefficients.
One of the plurality of threshold values is selected according to the value of the DC voltage.
It is characterized by that.

In the power factor improvement circuit
The control unit
When the DC voltage is larger than a predetermined voltage threshold value, the first threshold value among the plurality of the threshold values is selected, and when the DC voltage is equal to or less than the predetermined voltage threshold value, a plurality of the DC voltage values are selected. A second threshold value smaller than the first threshold value is selected from the threshold values.
It is characterized by that.

In the power factor improvement circuit
The control unit
When the polarity of the AC voltage is positive and the single arm control is performed, only the first arm circuit is operated, and the polarity of the AC voltage is opposite and the single arm control is performed. To operate only the second arm circuit,
It is characterized by that.

The method for controlling the power factor improving circuit according to one aspect of the present invention is as follows.
A pair of first and second input terminals to which an AC voltage is input, a pair of first and second output terminals to output a DC voltage, a first output terminal, and the first output terminal. An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, the first node and the first output terminal. A first arm circuit having a first switch element connected to and a second switch element connected between the first node and the second output terminal, and the first arm circuit. A third switch element connected between the second input terminal and the first output terminal, and a fourth switch connected between the second input terminal and the second output terminal. A polarity switching arm having an element, a second inductor connected between the first input terminal and the second node, and a second inductor connected between the second node and the first output terminal. A fifth switch element, a second arm circuit having a sixth switch element connected between the second node and the second output terminal, and depending on the polarity of the AC voltage, A control method for a power factor improving circuit including a control unit for controlling a switching operation from the first switch element to the sixth switch element.
The control unit compares the input current input to the first input terminal with the threshold value, and when the input current is larger than the threshold value, both the first arm circuit and the second arm circuit are operated. When the input current is equal to or less than the threshold value, the double arm control for operating only the first arm circuit is performed.
It is characterized by that.

The power factor improving circuit and the control method of the power factor improving circuit according to one aspect of the present invention have an effect that the power efficiency can be improved.

FIG. 1 is a diagram showing a circuit configuration of a power factor improving circuit according to the first embodiment. FIG. 2 is a diagram showing an example of an operation waveform of the power factor improving circuit according to the first embodiment. FIG. 3 is a diagram showing an example of the operation waveform of the power factor improving circuit of the comparative example. FIG. 4 is a diagram showing an example of an operation waveform of the power factor improving circuit according to the first embodiment. FIG. 5 is a diagram showing a circuit configuration of the power factor improving circuit of the second embodiment.

Hereinafter, embodiments of the power factor improving circuit of the present invention will be described in detail with reference to the drawings. The present invention is not limited to this embodiment.

(First Embodiment)
FIG. 1 is a diagram showing a circuit configuration of a power factor improving circuit according to the first embodiment. The power factor improving circuit 1 improves the power factor by an interleave method. Power factor correction circuit 1, AC (e.g., 50 Hz or 60Hz) supplied with the input voltage _{V in} from the power supply 2 and outputs an output voltage _{V out} is higher than the input voltage _{V in} direct current to the load 4, the booster circuit Is. In this embodiment, the effective value of the input voltage _{V in} is assumed to be 200V, the target voltage of the output voltage _{V out} is assumed to be 400V. In other words, the power factor correction circuit 1 is supplied with the input voltage _{V in} effective value 200V, and outputs an output voltage _{V out} of 400V.

A noise filter 3 is provided between the power supply 2 and the power factor improving circuit 1. The noise filter 3 is a filter that mainly suppresses common mode noise. The noise filter 3 includes a first cross-the-line capacitor 31, a common mode filter 32, and a second cross-the-line capacitor 33. The common mode filter 32 is obtained by winding the first winding 32a and the second winding 32b around a core 32c (for example, a ferrite core or an amorphous core) in the same direction.

Both ends of the first cross-the-line capacitor 31 are connected to both ends of the power supply 2, respectively. One end of the first winding 32a of the common mode filter 32 is connected to one end of the first cross-the-line capacitor 31. One end of the second winding 32b of the common mode filter 32 is connected to the other end of the first cross-the-line capacitor 31. One end of the second cross-the-line capacitor 33 is connected to the other end of the first winding 32a of the common mode filter 32. The other end of the second cross-the-line capacitor 33 is connected to the other end of the second winding 32b of the common mode filter 32.

The common mode noise flows in the same direction through the first winding 32a and the second winding 32b. Therefore, the magnetic fluxes generated inside the core 32c also have the same direction and strengthen each other. As a result, the impedance of the common mode filter 32 becomes large. As a result, the noise filter 3 can suppress common mode noise.

Power factor correction circuit 1 includes a first input terminal 11 and the second input terminal 12 of the input voltage V _in is supplied. Power factor correction circuit 1 includes a first voltage detector 13 for detecting an input voltage V _in. The first voltage detector 13 is connected between the first input terminal 11 and the second input terminal 12.

The power factor improving circuit 1 includes a first output terminal 14 and a second output terminal 15 that output an _{output voltage V out.} The power factor improving circuit 1 includes an output capacitor C _{1 for smoothing the output voltage V out} . The output capacitor C ₁ is connected between the first output terminal 14 and the second output terminal 15. Further, the power factor improving circuit 1 includes a second voltage detector 16 that detects an _{output voltage V out.} The second voltage detector 16 is connected between the first output terminal 14 and the second output terminal 15.

A load 4 is connected between the first output terminal 14 and the second output terminal 15. The load 4 is exemplified by, but is not limited to, a DC-DC converter that converts an _{output voltage V out to a different DC voltage.}

Power factor correction circuit 1 includes a first inductor L _1. The first end of the inductor L ₁ is connected to a first input terminal 11. The first end of the inductor L ₁ is connected to the first node N _1. Further, the power factor improving circuit 1 includes a second inductor L ₂ . One end of the second inductor L ₂ is connected to the first input terminal 11. The other end of the second inductor L ₂ is connected to the second node N _2.

Power factor correction circuit 1 includes first and second switching elements (for example, N-channel field effect transistor (MOSFET)) the _{Q 1} and _{Q 2.} The first node N _1, the first source of the switch element Q ₁ - through the drain path, and is connected to the first output terminal 14. Further, the first node N ₁ is connected to the second output terminal 15 via the drain-source path of the second switch element Q _2.

The first inductor L ₁ and the first and second switch elements Q ₁ and Q ₂ constitute the first arm circuit 17.

The first arm circuit 17 may be referred to as a master arm or a slave arm. Further, in the present embodiment, the power factor improving circuit 1 includes one first arm circuit 17, but the present invention is not limited to this. Power factor correction circuit 1 is connected in parallel, is controlled by the first and second gate pulse signals P ₁ and P _2, it may include two or more of the first arm circuit 17.

Further, the first arm circuit 17 has included a first switching element to Q ₁ high side one is not limited to this. The first arm circuit 17, the source - drain paths connected in parallel, is controlled by the first gate pulse signals P _1, may contain two or more switching elements of the high side. Further, the first arm circuit 17 is includes a second switching element Q ₂ of one of the low side, but is not limited thereto. The first arm circuit 17, the source - drain paths connected in parallel and controlled by a second gate pulse signals P _2, may include two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Power factor correction circuit 1 includes a third and fourth switching elements _{Q 3} and _{Q 4.} The second input terminal 12, the source of the third switching element Q ₃ - via the drain path is connected to the first output terminal 14. The second input terminal 12, the drain of the fourth switching element Q ₄ - via the source path is connected to the second output terminal 15.

Third and fourth switching elements _{Q 3} and _{Q 4} constitute a polarity switching arm circuit 18.

Polarity switching arm circuit 18 has included one third switching element Q ₃ of the high side, but is not limited thereto. Polarity switching arm circuit 18, the source - drain paths connected in parallel, is controlled by the third gate pulse signals P _3, may contain two or more switching elements of the high side. The polarity switching arm circuit 18 has included a fourth switching element Q ₄ of one of the low side, but is not limited thereto. Polarity switching arm circuit 18, the source - drain paths connected in parallel and controlled by a fourth gate pulse signal P _4, may contain two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Power factor correction circuit 1 includes a switching element _{Q 5} and _{Q 6} of the fifth and sixth. The second node N ₂ is connected to the first output terminal 14 via the source-drain path of the fifth switch element Q _5. The second node N _2, the drain of the switching element Q ₆ of the sixth - through the source path is connected to the second output terminal 15.

The second inductor _{L 2,} and the switching elements _{Q 5} and _{Q 6} of the fifth and sixth constitute the second arm circuit 19.

The second arm circuit 19 may be referred to as a slave arm or a master arm. Further, in the present embodiment, the power factor improving circuit 1 includes one second arm circuit 19, but the present invention is not limited to this. Power factor correction circuit 1 is connected in parallel, it is controlled by the gate pulse signal P ₅ and P ₆ of the fifth and sixth, may include two or more of the second arm circuit 19. The number of the second arm circuits 19 and the number of the first arm circuits 17 are preferably the same.

The second arm circuit 19 has included switching element Q ₅ of one fifth high side, but is not limited thereto. The second arm circuit 19, the source - drain paths connected in parallel, is controlled by the gate pulse signal P ₅ of the fifth, it may contain two or more switching elements of the high side. The second arm circuit 19 has included switching element Q ₆ of the sixth one of the low side, but is not limited thereto. The second arm circuit 19, the source - drain paths connected in parallel, is controlled by the gate pulse signal P ₆ of the sixth, it may contain two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Input current _{I in} is input to the first input terminal 11, the current _{I 1} flowing in the first arm circuit 17, a current _{I 2} flowing in the second arm circuit 19 is the sum of.

In this embodiment, although the first switching element Q ₁ until the switch element Q ₆ of the sixth was to be a N-channel MOSFET, but it is not limited thereto. From the first switching element _{Q 1} until the switch element _{Q 6} of the sixth, silicon power devices, GaN power devices, SiC power devices, IGBT (Insulated Gate Bipolar Transistor) or the like.

From the first switching element Q ₁ until the switch element Q ₆ of the sixth, from the first parasitic diode (body diode) D ₁ to the parasitic diode D ₆ of the sixth, respectively Yes. The parasitic diode is a pn junction between the back gate of the MOSFET and the source and drain. The first parasitic diode D ₁ to the sixth parasitic diode D ₆ are freewheels for escaping the transient counter electromotive force when the first switch element Q ₁ to the sixth switch element Q _{6 are off.} It can be used as a diode.

The power factor improving circuit 1 includes a control unit 50. The control unit 50 can be realized by using a CPU (Central Processing Unit) and a program.

Control unit 50, depending on the polarity of the input voltage V _in, the gate of the first switching element Q ₁ until the switch element Q ₆ of the sixth - by controlling the voltage between the source, the first switching element Q controlling the switching operation from _one to the switch element Q ₆ of the sixth. Control unit 50, PWM (Pulse Width Modulation) is a signal, from the first gate pulse signals _{P 1} to the gate pulse signal _{P 6} of the sixth switching element _{Q 6} of the first sixth from the switch element _{Q 1} Output to each of the gates up to. Note that the first gate pulse signals P ₁ to the gate pulse signal P ₆ of the sixth, the dead time t _d is set. The dead time t _d is exemplified, but is not limited to about 1 ns to 10 ns.

The control unit 50 _{compares the input current I in} with the threshold value Thα, and when the input current I _in is larger than the threshold value Thα, controls to operate both the first arm circuit 17 and the second arm circuit 19. I do. On the other hand, when the input current I _in is equal to or less than the threshold value Thα, the control unit 50 controls to operate only the first arm circuit 17 (or only the second arm circuit 19). In the present embodiment, the control for operating both the first arm circuit 17 and the second arm circuit 19 is called double arm control, and only the first arm circuit 17 (or only the second arm circuit 19). The control to operate is called single arm control.

The control unit 50 includes a coefficient storage unit 51, a peak input current calculation unit 52, a threshold value calculation unit 53, a determination unit 54, and a drive unit 55.

The coefficient storage unit 51 stores the coefficient α for calculating the threshold value Thα. The coefficient α may be rewritable via wired communication or wireless communication. The coefficient α is exemplified by, but is not limited to 0.5.

The instantaneous voltage of the input voltage _{V in,} the first, the second, switching element to _Q 1 fifth and _6, Q 2, _{Q 5} and _{Q 6,} on the in one period in the case of performing double-arm control The product of time _Ton-d can be used as an index value representing the _{input current I in.}

Therefore, the peak input current calculation unit 52, the instantaneous voltage of the input voltage _{V in,} and the on-time _{T on-d,} based on, to calculate the peak value _{I in-p} of the input current _{I in.}

The threshold value calculation unit 53 calculates the threshold value Thα by the product of the peak value I _{in −p of the input current I in and the coefficient α.} When the coefficient α is set to 0.5, the threshold value Thα becomes 1/2 of the peak value I _{in −p of the input current I in.}

The coefficient α is preferably set according to the capacity of the second cross-the-line capacitor 33. For example, the larger the capacitance of the second cross-the-line capacitor 33, the smaller the voltage ripple of the second cross-the-line capacitor 33. That is, the larger the capacitance of the second cross-the-line capacitor 33, the smaller the voltage ripple of the second cross-the-line capacitor 33 is suppressed even if the current ripple of _{the input current I in is large.} Therefore, the larger the capacitance of the second cross-the-line capacitor 33, the larger the coefficient α can be set.

Further, the larger the withstand voltage of the second cross-the-line capacitor 33, the larger the voltage ripple of the second cross-the-line capacitor 33 can withstand. That is, the larger the withstand voltage of the second cross-the-line capacitor 33, the larger _{the current ripple of the input current I in} , the larger the second cross-the-line capacitor 33 can withstand the voltage ripple. Therefore, the larger the withstand voltage of the second cross-the-line capacitor 33, the larger the coefficient α can be set.

Therefore, for example, the coefficient α is set based on 0.5 as the capacitance or withstand voltage of the second cross-the-line capacitor 33 increases, and the capacitance or the capacitance of the second cross-the-line capacitor 33 or The smaller the withstand voltage, the smaller it can be set.

Determining unit 54, the instantaneous voltage of the input voltage _{V in,} and the on-time _{T on-d,} based on, to calculate the current of the input current _{I in.} Then, the determination unit 54 _{compares the input current I in} with the threshold value Thα, and when the input current I _in is larger than the threshold value Thα, a low-level determination for causing the drive unit 55 to perform double arm control. and outputs the signals _{S 1} to the drive unit 55. On the other hand, when the input current I _{in is equal to or less than the threshold value Thα, the determination unit 54 outputs a high-level determination signal S 1} to the drive unit 55 for causing the drive unit 55 to perform single arm control.

In this embodiment, the peak input current calculation unit 52 and determination unit 54, based on the first voltage detector 13 input voltage V _in is detected by the on-time and T _on-d, the input current I it was decided to calculate the _in, but is not limited to this. The power factor improving circuit 1 may include a current detector that detects an _{input current I in.} In this embodiment, the peak input current calculation unit 52 and determination unit 54, based on the detected input voltage V _in and the on-time and T _on-d in the first voltage detector 13, the input current I _in The reason for the calculation is as follows.

Driver 55 first, second, in order to calculate the gate pulse signals _{P 1,} P 2, _{P 5} and _{P 6} of the fifth and sixth, the power factor correction circuit 1, the first voltage detector 13 And a second voltage detector 16 needs to be provided. Therefore, the peak input current calculation unit 52 and determination unit 54, based on the detected input voltage V _in and the on-time and T _on-d in the first voltage detector 13, if calculating the input current This is because it is not necessary to add new hardware (current detector).

Drive unit 55, when the determination signals S ₁ supplied from the determining unit 54 is at the low level, performs a double arm control. Drive unit 55, when the determination signal S ₁ is at the high level, performs single arm control.

Drive unit 55 is in each case a double arm control and single arm control, so that the output voltage V _out is equal to the target voltage (400V), from the first switch element Q ₁ until the switch element Q ₆ of the sixth To control.

Drive unit 55, when performing double-arm control, the input voltage V _in detected by the first voltage detector 13, the output voltage V _out which is detected by the second voltage detector 16, on the basis , first, second, fifth and sixth gate pulse signal _P 1 _of, P 2, _{P 5} and the frequency of the _{P 6} (switching frequency), the on time _{T on-d,} the first arm circuit 17 _{The phase difference time t diff} with the second arm circuit 19 is calculated. The drive unit 55 has the first, second, fifth, and sixth gate pulse signals P ₁ , P ₂ , based on the calculated frequency, the on-time _Ton-d, and the phase difference time t _diff. the P ₅ and _{P 6,} first, the second, switching element to _Q 1 fifth and _6, Q 2, the gate of _{Q 5} and _{Q 6,} respectively output.

Drive unit 55, when performing single-arm control, the input voltage V _in detected by the first voltage detector 13, the output voltage V _out which is detected by the second voltage detector 16, on the basis calculates the first and second gate pulse signals _{P 1} and _{P 2} of the frequency (switching frequency), the on time _{T on-s,} a.

Driving unit 55, in a single arm control period for single arm control, the first switching element Q ₁ and the second on-time switching element Q ₂ T _on-s, performs double arm control in a single-arm control period It is assumed that the on-time of the first switch element Q1 and the second switch element Q2 is twice the _on-d. That is, the drive unit 55 has _Ton-s = 2 · _Ton-d . This is because the two arm circuits of the first arm circuit 17 and the second arm circuit 19 are responsible for power conversion when performing double arm control, and the first when performing single arm control. This is because only the arm circuit 17 has to be responsible for power conversion. That is, when performing single arm control, the first arm circuit 17 must perform twice as much power conversion as when performing double arm control. Driving unit 55, the calculated frequency, and the on-time _{T on-s,} based on, of the first and second gate pulse signals _{P 1} and _{P 2,} the first and second switching elements _{Q 1} and Q Output to each of the gates of _2.

The operation of the control unit 50 during double arm control will be described.

Control unit 50, the polarity of the input voltage V _in the case of the positive phase is on the third switching element Q ₃ off and and the fourth of the switching element Q ₄ of polarity switching arm circuit 18.

Then, the control unit 50, the third switching element Q ₃ off to state and turned on the fourth switch element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / while controlling to switch off, and controls so that the switching element Q ₅ and Q ₆ of the fifth and sixth switches the complementarily turned on / off.

For example, the control unit 50, when the input voltage _{V in} is positive-phase, second, fourth and switching element _Q 2, _{Q 4} and _{Q 6} was turned on while the first sixth, third and fifth from a first state in which turning off the switch element Q _1, Q ₃ and Q ₅ of, for controlling the second switching element Q ₂ in the second state in which turned off and and the first switching element Q _1.

Further, the control unit 50, after controlling the second state, the second state is controlled to the third state of turning off the switch element Q ₆ of the sixth.

Then, the control unit 50, after controlling the third state, the third state is controlled to a fourth state in which turns on the switch element Q ₅ of the fifth.

The control unit 50, after controlling the fourth state, the fourth state is controlled to a fifth state in which off the first switching element Q _1.

Then, the control unit 50, after controlling the fifth state, the fifth state, and controls the sixth state of that on the second switching element Q _2.

Further, after controlling to the sixth state, the control unit 50 controls from the sixth state to the seventh state in which the _{fifth switch element Q5 is turned off.}

Then, after controlling to the seventh state, the control unit 50 controls from the seventh state to the eighth state in which the _{sixth switch element Q6 is turned on.}

Further, after controlling to the eighth state, the control unit 50 controls from the eighth state to the ninth state in which the _{second switch element Q2 is turned off.}

Then, after controlling to the ninth state, the control unit 50 controls from the ninth state to the tenth state in which the _{first switch element Q1 is turned on.}

By the control described above, when the polarity of the input voltage V _in is positive phase, the current I ₁ and I ₂ are applied through the fourth switching element Q _4, will flow to the second input terminal 12 ..

On the other hand, the control unit 50, when the polarity of the input voltage V _in is reversed phase, turns off the third switching element Q ₃ ON and and fourth switching elements Q ₄ of polarity switching arm circuit 18 ..

Then, the control unit 50, the third switching element Q ₃ at ON and state and turning off the fourth switching element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / while controlling to switch off, and controls so that the switching element Q ₅ and Q ₆ of the fifth and sixth switches the complementarily turned on / off.

This control, when the polarity of the input voltage V _in is reversed phase, currents I ₁ and I ₂ is allowed to flow to the first input terminal 11 via a third switching element Q _3.

The polarity of the input voltage V _in when it is reversed phase, while controlling to switch complementarily turned on / off first and second switching elements Q ₁ and Q _2, the fifth and sixth specific operations for controlling to switch complementarily turned on / off the switch element Q ₅ and Q ₆ from a first state when the input voltage V _in the above are positive-phase up to the 10 state Similar to control.

FIG. 2 is a diagram showing an example of an operation waveform of the power factor improving circuit according to the first embodiment. FIG. 2 is a diagram showing an example of an operation waveform of the power factor improving circuit 1 during double arm control when the polarity of the input voltage Vin is _{in the positive phase.}

Control unit 50, when the input voltage _{V in} is positive-phase, second, fourth and sixth switching element _Q 2, _{Q 4} and _{Q 6} turned on and the first to the third and fifth switch controlling the elements _Q 1, _{Q 3} and _{Q 5} in a first state in which off. Next, the control unit 50, at the timing _{t 1,} turns off the second switching element _{Q 2.} Next, the control unit 50 at a timing t ₂ after elapse of the dead time t _d from the timing t _1, and controls the second state in which the on-first switching element Q _1.

Next, the control unit 50 at a timing t _3, from the second state to control the third state of turning off the switch element Q ₆ of the sixth. Next, the control unit 50 at a timing t ₄ after the dead time t _d has elapsed from the timing t _3, and controls the fourth state in which turns on the switch element Q ₅ of the fifth. The period from timing t ₂ to timing t _{4 is the phase difference time t diff} between the first arm circuit 17 and the second arm circuit 19.

Next, the control unit 50, at the timing t _5, the fourth state is controlled to a fifth state in which off the first switching element Q _1. The period from timing t ₂ to timing t ₅ is the on-time _Ton-d . Next, the control unit 50, at the timing t ₆ after the dead time t _d has elapsed from the timing t _5, and controls the sixth state of that on the second switching element Q _2. Next, the control unit 50, at the timing t _7, the sixth state of controls to the seventh state of turning off the switching element Q ₅ of the fifth. The period from timing t ₄ to timing t ₇ is the on-time _Ton-d .

Next, the control unit 50 at a timing t ₈ of the dead time t _d after the timing t _7, the seventh state, to control the state of the 8 turns on the switch element Q ₆ of the sixth. Next, the control unit 50 at a timing t _9, the state of the 8 controls the ninth state of turning off the second switching element Q _2. The period from timing t ₆ to timing t ₉ is the on-time _Ton-d . Next, the control unit 50, the dead time _{t d} has elapsed timing _{t 10} after the timing _{t 9,} the ninth state is controlled to a tenth state of the turn on the first switching element _{Q 1.}

The control unit 50 subsequently executes the same control.

Note that the second gate pulse signals P ₂ phases for controlling the second switching element Q _2, the phase and the sixth switch element Q ₆ gate pulse signal P ₆ of the sixth to control the , The phase difference time is shifted by _{t diff.} As well as, the first gate pulse signal P ₁ of the phase to control the first switching element Q _1, the fifth gate pulse signal P ₅ for controlling the switching element Q ₅ of the fifth phase Is deviated by the phase difference time t _diff.

The operation of the control unit 50 during single arm control will be described.

The first arm circuit 17 has a circuit configuration similar to that of the boost chopper circuit. Therefore, the power factor improving circuit 1 operates in the same manner as the boost chopper circuit in the case of single arm control.

More specifically, the control unit 50, when the polarity of the input voltage V _in is positive phase, the third switching element Q ₃ is turned off and the fourth switching element Q ₄ of polarity switching arm circuit 18 Turn on.

Then, the control unit 50, the third switching element Q ₃ off to state and turned on the fourth switch element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / Control to switch off.

For example, the control unit 50, when the input voltage V _in is positive phase, turned on and the first and the second and fourth switching elements Q ₂ and Q _4, the third, fifth and sixth switching elements The control is performed _{from the first state in which Q 1} , Q ₃ , Q ₅ and Q ₆ are turned off to the second state in which the second switch element Q ₂ is turned off and the first switch element Q ₁ is turned on.

Further, the control unit 50, after controlling the second state, the second state is controlled to the third state in which off the first switching element Q _1. Then, the control unit 50, after controlling the third state, the third state is controlled to a fourth state in which the on-second switching element Q _2. The control unit 50, after controlling the fourth state, the fourth state is controlled to a fifth state in which turning off the second switching element Q _2.

By the above control, when _{the polarity of the input voltage Vin is in} the positive phase, the current I ₁ flows to the second input terminal 12 via the _fourth switch element Q 4.

On the other hand, the control unit 50, when the polarity of the input voltage V _in is reversed phase, turns off the third switching element Q ₃ ON and and fourth switching elements Q ₄ of polarity switching arm circuit 18 ..

Then, the control unit 50, the third switching element Q ₃ at ON and state and turning off the fourth switching element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / Control to switch off.

This control, when the polarity of the input voltage V _in the reverse phase, the current I ₁ is allowed to flow to the first input terminal 11 via a third switching element Q _3.

The polarity of the input voltage V _in when it is reversed phase, specific operation of controlling so that the first and second switching elements Q ₁ and Q ₂ switches the complementarily turned on / off, the above input voltage V _in is the same as the control from the first state when a positive phase to a fifth state.

FIG. 3 is a diagram showing an example of the operation waveform of the power factor improving circuit of the comparative example. FIG. 3 is a diagram showing an example of the operating waveform of the power factor improving circuit 1 when the double arm control is performed during the entire period 81 _{in which} the polarity of the input voltage Vin is in the positive phase.

When the polarity of the input voltage V _in to perform double arm control during the period 81 of the positive phase, the envelope of the current I ₂ flowing through the envelope and a second arm circuit 19 of the current I ₁ flowing through the first arm circuit 17 The line becomes sinusoidal.

FIG. 4 is a diagram showing an example of an operation waveform of the power factor improving circuit according to the first embodiment. FIG. 4 is a diagram showing an example of the operation waveform of the power factor improving circuit 1 when the polarity of the input voltage Vin is _{in the positive phase.}

When the coefficient α is set to 0.5, the _{period 72 in} which the input current I _in is larger than 1/2 of the peak value I _{in −p} of the input current I in is the period in which the double arm control is performed. .. _{The periods 71 and 73 in} which the input current I _in is ½ or less of the peak value I _{in −p} of the input current I in are the periods in which the single arm control is performed.

In the period 72, the control unit 50 performs double arm control. Therefore, in the period 72, _{the waveforms of the currents I 1} and I ₂ are the same as those of the comparative example (see FIG. 3).

During periods 71 and 73, the control unit 50 operates only the first arm circuit 17 and does not operate the second arm circuit 19. Therefore, in the periods 71 and 73, the current I ₂ flowing through the second arm circuit 19 is 0. On the other hand, in the periods 71 and 73, the first arm circuit 17 must be responsible for power conversion up to the amount of the second arm circuit 19. Further, in the periods 71 and 73, _Ton-s = 2 · _Ton-d . Therefore, in the periods 71 and 73, the current I ₁ flowing through the first arm circuit 17 is approximately twice as large _{as the current I 1 in} the same period in the comparative example (see FIG. 3).

As described above, the power factor improving circuit 1 performs double arm control in the region where _{the input current I in is larger than the threshold value Th.}

In the region where the input current I _in is larger than the threshold value Th, the currents I ₁ and I ₂ are large, so that there is a great merit that _{the currents I 1} and I _{2 cancel each other out.}

Further, in a region input voltage _{V in} is large, the increased amount of pressure for boosting the input voltage _{V in} to an output voltage _{V out} is small, the first, second, switching element to _Q 1 fifth and _{6, Q} 2, Q ₅ and a long period of Q _6, it is sufficient to ask switched That at low switching frequencies. First, second, if the switching period of the fifth and sixth switch elements to _{Q 1,} Q 2, _{Q 5} and _{Q 6} is long, a small disadvantage of control load of the control unit 50.

The first, the second, the switching period of the fifth and sixth switch elements to _{Q 1,} Q 2, _{Q 5} and _{Q 6} is long, the first, second, switching element to _{Q 1} the fifth and sixth , the absolute amount of switching losses and gate drive losses _Q 2, _{Q 5} and _{Q 6} is small. In addition, the area input voltage V _in is high, the conversion power is large area. Therefore, for the conversion power, first, second, ratio of the switching losses and gate drive losses of the fifth and sixth switch elements to _{Q 1,} Q 2, _{Q 5} and _{Q 6} is low. That is, the demerit of lowering power efficiency is small.

Therefore, the power factor correction circuit 1, the input current I _in is the threshold Th larger area, by performing the double-arm control can reduce the second across-the Line ripple current of the capacitor 33 and the output capacitor C _1, the power It is possible to improve efficiency.

The power factor improving circuit 1 _{performs single arm control in a region where the input current I in} is equal to or less than the threshold value Th.

In the region where the input current I _in is equal to or less than the threshold value Th, that is, _in the vicinity of the zero cross of the _{input voltage Vin, the currents I 1} and I ₂ are small, so that the _{merits of the currents I 1} and I ₂ canceling each other are small.

Further, in the vicinity of the zero crossing of the input voltage _{V in,} since a large step-up amount for boosting the input voltage _{V in} to an output voltage _{V out,} first, second, switching element to _Q 1 fifth and _{6, Q} 2, Q it is necessary to switch the ₅ and Q ₆ in a short cycle. First, the second, the switching period of the fifth and sixth switch elements to _{Q 1,} Q 2, _{Q 5} and _{Q 6} is short, there is a disadvantage that control load of the control unit 50 is large.

The first, the second, the switching period of the fifth and sixth switch elements to _{Q 1,} Q 2, _{Q 5} and _{Q 6} is short, first, second, switching element to _{Q 1} the fifth and sixth , _Q 2, the absolute amount of switching losses and gate drive losses _{Q 5} and _{Q 6} is large. In addition, near the zero crossing of the input voltage V _in is an area conversion power is small. Therefore, for the conversion power, first, second, ratio of the switching losses and gate drive losses of the fifth and sixth switch elements to _{Q 1,} Q 2, _{Q 5} and _{Q 6} is high. That is, the demerit of lowering power efficiency is large.

Therefore, the power factor correction circuit 1, the input current I _in is the threshold Th or less of the area, by performing a single-arm control, to suppress the switching operation of the switching element Q ₅ and Q ₆ of the fifth and sixth, by suppressing the switching loss and the gate drive loss of the fifth and the switch element Q ₅ and Q ₆ of the sixth, it is possible to achieve power efficiency.

When the coefficient α is set to 0.5, the ratio between the period for performing single arm control (sum of period 71 and period 73) and the period for performing double arm control (period 72) is , Approximately 1: 1. As a result, the balance between the merits and demerits of single arm control and the merits and demerits of double arm control becomes suitable.

The control unit 50, when the polarity is positive polarity and a single arm control input voltage V _in is allowed to operate only the first arm circuit 17, the polarity of the input voltage V _in is located at the opposite polarity Moreover, when performing single arm control, only the second arm circuit 19 may be operated. As a result, the power factor improving circuit 1 can suppress the bias between the heat generated by the first arm circuit 17 and the heat generated by the second arm circuit 19.

(Second Embodiment)
In the first embodiment, the target voltage of the _{output voltage V out is set to 400 V.} However, it is conceivable that the target voltage of the output voltage V _{out may change.} For example, the load 4 may request 400V during normal operation, but may request 390V during low voltage (low power consumption) operation (for example, in sleep mode).

In the second embodiment, _{the target voltage of the output voltage V out} is changed to a first target voltage (for example, 400V) and a second target voltage (for example, 390V).

FIG. 5 is a diagram showing a circuit configuration of the power factor improving circuit of the second embodiment. The same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The power factor improving circuit 1A includes a control unit 50A instead of the control unit 50 of the first embodiment. The control unit 50A includes a coefficient storage unit 51A, a peak input current calculation unit 52, a threshold value calculation unit 53A, a determination unit 54A, a drive unit 55A, and an output voltage threshold value storage unit 56.

The coefficient storage unit 51A stores the coefficients α and β for calculating the threshold values Thα and Thβ. The coefficients α and β may be rewritable via wired communication or wireless communication. The coefficient α is exemplified by, but is not limited to 0.5. The coefficient β is exemplified by, but is not limited to 0.4.

When the second target voltage (390V) is lower than the first target voltage (400V), the coefficient β is preferably smaller than the coefficient α. When the second target voltage (for example, 410V) is higher than the first target voltage (400V), the coefficient β is preferably larger than the coefficient α.

The threshold value calculation unit 53A calculates the threshold value Thα by the product of _{the peak value I in −p of the input current and the coefficient α.} Further, the threshold value calculation unit 53A calculates the threshold value Thβ by the product of _{the peak value I in-p of the input current and the coefficient β.}

The output voltage threshold value storage unit 56 stores the threshold value V _{th of the output voltage V out} . The threshold value _Vth may be rewritable via wired communication or wireless communication. The threshold _Vth is a value between the first target voltage (400V) and the second target voltage (390V). For example, the threshold _Vth is exemplified by, but is not limited to, 395V. The threshold value _Vth may be 394V or 396V.

The determination unit 54A compares the output voltage V _out with the threshold value V _th . When the output voltage V _out is larger than the threshold value V _th , the determination unit 54A selects the threshold value Thα among the threshold value Thα and Thβ. When the output voltage V _out is equal to or less than the threshold value V _th , the determination unit 54A selects the threshold value Thβ among the threshold value Thα and Thβ.

Determination unit 54A includes a instantaneous voltage of the input voltage _{V in,} and the on-time _{T on-d,} based on, to calculate the current of the input current _{I in.} Then, the determination unit 54A compares the input current I _in with the selected threshold value among the threshold values Thα and Thβ. Determination unit 54A, when the input current I _in is greater than the selected threshold, the output for causing the double-arm control to the driving unit 55A, a low-level determination signals S ₁ to the drive unit 55A. On the other hand, when the input current I _{in is equal to or less than the selected threshold value, the determination unit 54A outputs a high-level determination signal S 1} to the drive unit 55A for causing the drive unit 55A to perform single arm control.

The drive unit 55A, the signal S ₂ that specifies the target voltage is supplied. If the signal S ₂ is low level, a first target voltage (400V) is specified. If the signal S ₂ is at a high level, a second target voltage (390V) is specified.

_{The drive unit 55A is a first switch so that the output voltage V out} becomes the first target voltage (400 V) or the second target voltage (390 V) in both the double arm control and the single arm control. controlling the from element _{Q 1} until the switch element _{Q 6} of the sixth. Since the specific control content of the drive unit 55A is the same as that of the drive unit 55 of the first embodiment, the description thereof will be omitted.

When the second target voltage (390V) is specified and the output voltage V _out drops and the threshold Thα for the first target voltage (400V) is used, the single arm control period (period of FIG. 4). (See 71 and 73) does not change, but the double arm control period (see period 72 in FIG. 4) becomes shorter, and the merit of double arm control decreases.

Therefore, the power factor improving circuit 1A stores two coefficients α and β, and selects one of the coefficients α and β according _{to the output voltage V out.} Thereby, the power factor improving circuit 1A can adjust the balance between the single arm control period (see periods 71 and 73 in FIG. 4) and the double arm control period (see period 72 in FIG. 4). As a result, the power factor improving circuit 1A can suppress that the merit of the double arm control is reduced.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, as well as in the scope of the invention described in the claims and the equivalent scope thereof.

1, 1A Power factor improvement circuit 2 Power supply 3 Noise filter 4 Load 11 1st input terminal 12 2nd input terminal 13 1st voltage detector 14 1st output terminal 15 2nd output terminal 16 2nd voltage Detector 17 1st arm circuit 18 Polarity switching arm circuit 19 2nd arm circuit 50, 50A Control unit 51, 51A Coefficient storage unit 52 Peak input current calculation unit 53, 53A Threshold calculation unit 54, 54A Judgment unit 55, 55A Drive unit 56 Output voltage threshold storage unit L ₁ First inductor L ₂ Second inductor Q ₁ First switch element Q ₂ Second switch element Q ₃ Third switch element Q ₄ Fourth switch element Q ₅ Fifth switch element Q ₆ Sixth switch element C ₁ Output voltage N ₁ First node N ₂ Second node

Claims (8)

A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor connected between the first input terminal and the first node, a first switch element connected between the first node and the first output terminal, and One or more first arm circuits having at least a second switch element connected between the first node and the second output terminal.
A third switch element connected between the second input terminal and the first output terminal, and a fourth connected between the second input terminal and the second output terminal. Polarity switching arm with at least the switch element of
A second inductor connected between the first input terminal and the second node, a fifth switch element connected between the second node and the first output terminal, and One or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal.
A control unit that controls the switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage.
With
The control unit
The input current input to the first input terminal is compared with the threshold value, and when the input current is larger than the threshold value, both the first arm circuit and the second arm circuit are operated. performs double arm control, when the input current is less than the threshold value, have rows single arm control to operate only the first arm circuit,
The first switch element and the second switch element on time in the single arm control period in which the single arm control is performed are assumed to perform the double arm control in the single arm control period. Twice the on-time of the switch element 1 and the second switch element.
A power factor improvement circuit characterized by this. A pair of first input terminals and second input terminals to which AC voltage is input,
A pair of first output terminals and second output terminals that output DC voltage,
An output capacitor connected between the first output terminal and the second output terminal,
A first inductor connected between the first input terminal and the first node, a first switch element connected between the first node and the first output terminal, and One or more first arm circuits having at least a second switch element connected between the first node and the second output terminal.
A third switch element connected between the second input terminal and the first output terminal, and a fourth connected between the second input terminal and the second output terminal. Polarity switching arm with at least the switch element of
A second inductor connected between the first input terminal and the second node, a fifth switch element connected between the second node and the first output terminal, and One or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal.
A control unit that controls the switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage.
With
The control unit
The input current input to the first input terminal is compared with the threshold value, and when the input current is larger than the threshold value, both the first arm circuit and the second arm circuit are operated. Double arm control is performed, and when the input current is equal to or less than the threshold value, single arm control for operating only the first arm circuit is performed.
The peak value of the input current is calculated based on the instantaneous voltage of the AC voltage and the on-time of the first switch element and the second switch element when the double arm control is performed.
The threshold value is calculated by multiplying the peak value of the input current and a predetermined coefficient.
A power factor improvement circuit characterized by this. The coefficient is 0.5.
The power factor improving circuit according to claim 2 , wherein the power factor is improved. The control unit
A plurality of the threshold values are calculated by multiplying the peak value of the input current and each of the plurality of predetermined coefficients.
One of the plurality of threshold values is selected according to the value of the DC voltage.
The power factor improving circuit according to claim 2 , wherein the power factor is improved. The control unit
When the DC voltage is larger than a predetermined voltage threshold value, the first threshold value among the plurality of the threshold values is selected, and when the DC voltage is equal to or less than the predetermined voltage threshold value, a plurality of the DC voltage values are selected. A second threshold value smaller than the first threshold value is selected from the threshold values.
The power factor improving circuit according to claim 4 , wherein the power factor is improved. The control unit
When the polarity of the AC voltage is positive and the single arm control is performed, only the first arm circuit is operated, and the polarity of the AC voltage is opposite and the single arm control is performed. To operate only the second arm circuit,
The power factor improving circuit according to any one of claims 1 to 5 , wherein the power factor improving circuit is characterized in that. A pair of first and second input terminals to which an AC voltage is input, a pair of first and second output terminals to output a DC voltage, a first output terminal, and the first output terminal. An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, the first node and the first output terminal. One or more first arm circuits having at least a first switch element connected to and a second switch element connected between the first node and the second output terminal. And a third switch element connected between the second input terminal and the first output terminal, and connected between the second input terminal and the second output terminal. A polarity switching arm having at least a fourth switch element, a second inductor connected between the first input terminal and the second node, the second node and the first output terminal. A fifth switch element connected between them, and one or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal. A control method for a power factor improving circuit including a control unit that controls a switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage.
The control unit compares the input current input to the first input terminal with the threshold value, and when the input current is larger than the threshold value, the first arm circuit and the second arm circuit both the make double arm control to operate, when the input current is less than the threshold value, it has rows single arm control to operate only the first arm circuit,
The first switch element and the second switch element on time in the single arm control period in which the single arm control is performed are assumed to perform the double arm control in the single arm control period. Twice the on-time of the switch element 1 and the second switch element.
A method of controlling a power factor improving circuit, which is characterized by the fact that. A pair of first and second input terminals to which an AC voltage is input, a pair of first and second output terminals to output a DC voltage, a first output terminal, and the first output terminal. An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, the first node and the first output terminal. One or more first arm circuits having at least a first switch element connected to and a second switch element connected between the first node and the second output terminal. And a third switch element connected between the second input terminal and the first output terminal, and connected between the second input terminal and the second output terminal. A polarity switching arm having at least a fourth switch element, a second inductor connected between the first input terminal and the second node, the second node and the first output terminal. A fifth switch element connected between them, and one or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal. A control method for a power factor improving circuit including a control unit that controls a switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage.
The control unit compares the input current input to the first input terminal with the threshold value, and when the input current is larger than the threshold value, the first arm circuit and the second arm circuit When the input current is equal to or less than the threshold value, the double arm control for operating both of the above is performed, and the single arm control for operating only the first arm circuit is performed .
The peak value of the input current is calculated based on the instantaneous voltage of the AC voltage and the on-time of the first switch element and the second switch element when the double arm control is performed.
The threshold value is calculated by multiplying the peak value of the input current and a predetermined coefficient.
A method of controlling a power factor improving circuit, which is characterized by the fact that.

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