JP2019022395A - Power-factor improvement circuit and control method of the same - Google Patents

Abstract

To provide a power-factor improvement circuit capable of improving an electric efficiency.SOLUTION: A power-factor improvement circuit comprises: one or more first arm circuits having at least a first inductor, a first switch element, and a second switch element; a polarity switching arm having at least a third switch element and a fourth switch element; one or more second arm circuits having at least a second inductor, a fifth witch element, and a sixth switch element; and a control part that controls a switching operation of the first to sixth switching elements. The control part performs a double arm control which operates both of the first and second arm circuits when the input current is larger than a threshold value, and performs a single arm control which operates only the first arm circuit when the input current is smaller than the threshold value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power factor correction circuit and a control method for the power factor correction circuit.

  Conventionally, there is an interleaved power factor correction circuit (see, for example, Patent Document 1). This conventional power factor correction circuit includes a master arm circuit (may be referred to as a first arm circuit), a slave arm circuit (may be referred to as a second arm circuit), a polarity switching arm circuit, . In this conventional power factor correction circuit, since the currents of the two inductors are out of phase, the current of one inductor flows in a direction that cancels the current of the other inductor. Therefore, the ripple current of the input capacitor and the output capacitor can be reduced.

  However, there are the following circumstances near the zero cross of the input voltage. Since the current of each inductor is small, the merit that the currents of the two inductors cancel each other is small. Therefore, the merit of reducing the ripple current of the input capacitor and the output capacitor is small.

  On the other hand, the voltage boost amount is large, and it is necessary to switch the switch element in a short cycle. Therefore, there is a demerit that the control burden is large.

  Further, since the switching element is switched in a short period, the absolute amount of switching loss and gate driving loss of the switching element is large. In addition, the vicinity of the zero cross of the input voltage is a region where the converted power is small. Therefore, the ratio of the switching loss of the switch element and the gate drive loss to the converted power is high. Therefore, there is a demerit that power efficiency is lowered.

Japanese Patent Laying-Open No. 2015-23606

  An object of the present invention is to provide a power factor correction circuit capable of improving power efficiency and a control method of the power factor correction circuit.

A power factor correction circuit according to one embodiment of the present invention includes:
A pair of first and second input terminals to which an alternating voltage is input;
A pair of first and second output terminals that output a DC voltage;
An output capacitor connected between the first output terminal and the second output terminal;
A first inductor connected between the first input terminal and a first node; a first switch element connected between the first node and the first output terminal; and One or more first arm circuits having at least a second switch element connected between the first node and the second output terminal;
A third switch element connected between the second input terminal and the first output terminal; and a fourth switch element connected between the second input terminal and the second output terminal. A polarity switching arm having at least a switching element;
A second inductor connected between the first input terminal and a second node; a fifth switch element connected between the second node and the first output terminal; and One or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal;
A control unit that controls a switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage;
With
The controller is
An input current input to the first input terminal is compared with a threshold value, and if the input current is larger than the threshold value, both the first arm circuit and the second arm circuit are operated. Double arm control is performed, and when the input current is less than or equal to the threshold value, single arm control for operating only the first arm circuit is performed.
It is characterized by that.

In the power factor correction circuit,
The controller is
When the on-time of the first switch element and the second switch element in the single arm control period in which the single arm control is performed is assumed to be performed in the single arm control period, the second arm control is performed. 2 times the on-time of one switch element and the second switch element,
It is characterized by that.

In the power factor correction circuit,
The controller is
Based on the instantaneous voltage of the AC voltage and the ON time of the first switch element and the second switch element when performing the double arm control, the peak value of the input current is calculated,
The threshold value is calculated by a product of a peak value of the input current and a predetermined coefficient.
It is characterized by that.

In the power factor correction circuit,
The coefficient is 0.5.
It is characterized by that.

In the power factor correction circuit,
The controller is
A plurality of the threshold values are calculated by a product of the peak value of the input current and each of a plurality of predetermined coefficients,
Selecting one of the thresholds according to the value of the DC voltage;
It is characterized by that.

In the power factor correction circuit,
The controller is
When the DC voltage is greater than a predetermined voltage threshold, a first threshold is selected from the plurality of thresholds, and when the DC voltage is less than or equal to a predetermined voltage threshold, a plurality of Selecting a second threshold value smaller than the first threshold value among the threshold values;
It is characterized by that.

In the power factor correction circuit,
The controller is
When the polarity of the AC voltage is positive and the single arm control is performed, only the first arm circuit is operated, and the polarity of the AC voltage is the reverse polarity and the single arm control is performed. To operate only the second arm circuit,
It is characterized by that.

The control method of the power factor correction circuit according to one aspect of the present invention includes:
A pair of first input terminal and second input terminal to which an AC voltage is input, a pair of first output terminal and second output terminal for outputting a DC voltage, the first output terminal, and the first An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, and the first node and the first output terminal. And a first arm circuit having a first switch element connected between the first node and a second switch element connected between the first node and the second output terminal; A third switch element connected between the second input terminal and the first output terminal, and a fourth switch connected between the second input terminal and the second output terminal. A polarity switching arm having an element, and the first input terminal and the second node. A second inductor connected to the second node, a fifth switch element connected between the second node and the first output terminal, and the second node and the second output terminal. A second arm circuit having a sixth switch element connected therebetween, and a control unit for controlling a switching operation from the first switch element to the sixth switch element in accordance with the polarity of the AC voltage; A method for controlling a power factor correction circuit comprising:
The control unit compares the input current input to the first input terminal with a threshold value, and operates both the first arm circuit and the second arm circuit when the input current is larger than the threshold value. Double arm control is performed, and when the input current is less than or equal to the threshold value, single arm control is performed to operate only the first arm circuit.
It is characterized by that.

  The power factor correction circuit and the control method of the power factor correction circuit according to one embodiment of the present invention have an effect that power efficiency can be improved.

FIG. 1 is a diagram illustrating a circuit configuration of the power factor correction circuit according to the first embodiment. FIG. 2 is a diagram illustrating an example of operation waveforms of the power factor correction circuit according to the first embodiment. FIG. 3 is a diagram illustrating an example of operation waveforms of the power factor correction circuit of the comparative example. FIG. 4 is a diagram illustrating an example of operation waveforms of the power factor correction circuit according to the first embodiment. FIG. 5 is a diagram illustrating a circuit configuration of the power factor correction circuit according to the second embodiment.

  Embodiments of a power factor correction circuit according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited by this embodiment.

(First embodiment)
FIG. 1 is a diagram illustrating a circuit configuration of the power factor correction circuit according to the first embodiment. The power factor improvement circuit 1 improves the power factor by an interleave method. Power factor correction circuit 1, AC (e.g., 50 Hz or 60Hz) supplied with the input voltage _{V in} from the power supply 2 and outputs an output voltage _{V out} is higher than the input voltage _{V in} direct current to the load 4, the booster circuit It is. In this embodiment, the effective value of the input voltage _{V in} is assumed to be 200V, the target voltage of the output voltage _{V out} is assumed to be 400V. In other words, the power factor correction circuit 1 is supplied with the input voltage _{V in} effective value 200V, and outputs an output voltage _{V out} of 400V.

  A noise filter 3 is provided between the power source 2 and the power factor correction circuit 1. The noise filter 3 is a filter that mainly suppresses common mode noise. The noise filter 3 includes a first across-the-line capacitor 31, a common mode filter 32, and a second across-the-line capacitor 33. The common mode filter 32 is obtained by winding a first winding 32a and a second winding 32b around a core 32c (for example, a ferrite core or an amorphous core) in the same direction.

  Both ends of the first across-the-line capacitor 31 are connected to both ends of the power source 2, respectively. One end of the first winding 32 a of the common mode filter 32 is connected to one end of the first across the line capacitor 31. One end of the second winding 32 b of the common mode filter 32 is connected to the other end of the first across the line capacitor 31. One end of the second across the line capacitor 33 is connected to the other end of the first winding 32 a of the common mode filter 32. The other end of the second across the line capacitor 33 is connected to the other end of the second winding 32 b of the common mode filter 32.

  The common mode noise flows in the same direction through the first winding 32a and the second winding 32b. Therefore, the magnetic fluxes generated in the core 32c are also in the same direction and strengthen each other. As a result, the impedance of the common mode filter 32 increases. Thereby, the noise filter 3 can suppress common mode noise.

Power factor correction circuit 1 includes a first input terminal 11 and the second input terminal 12 of the input voltage V _in is supplied. Power factor correction circuit 1 includes a first voltage detector 13 for detecting an input voltage V _in. The first voltage detector 13 is connected between the first input terminal 11 and the second input terminal 12.

The power factor correction circuit 1 includes a first output terminal 14 and a second output terminal 15 that output an output voltage _Vout . Power factor correction circuit 1 includes an output capacitor _{C 1} for smoothing the output voltage _{V out.} The output capacitor C ₁ is connected between the first output terminal 14 and the second output terminal 15. The power factor correction circuit 1 also includes a second voltage detector 16 that detects the output voltage _Vout . The second voltage detector 16 is connected between the first output terminal 14 and the second output terminal 15.

A load 4 is connected between the first output terminal 14 and the second output terminal 15. The load 4 is exemplified by a DC-DC converter that converts the output voltage _Vout to a different DC voltage, but is not limited thereto.

Power factor correction circuit 1 includes a first inductor L _1. One end of the first inductor L ₁ is connected to the first input terminal 11. The first end of the inductor L ₁ is connected to the first node N _1. Moreover, power factor correction circuit 1 includes a second inductor L _2. One end of the second inductor L ₂ is connected to the first input terminal 11. The second end of the inductor L ₂ is connected to the second node N _2.

Power factor correction circuit 1 includes first and second switching elements (for example, N-channel field effect transistor (MOSFET)) the _{Q 1} and _{Q 2.} The first node N _1, the first source of the switch element Q ₁ - through the drain path, and is connected to the first output terminal 14. The first node N _1, the second drain of the switching element Q ₂ - via the source path is connected to the second output terminal 15.

The first inductor L ₁ and the first and second switch elements Q ₁ and Q ₂ constitute a first arm circuit 17.

The first arm circuit 17 may be referred to as a master arm or a slave arm. In the present embodiment, the power factor correction circuit 1 includes the first arm circuit 17, but the present invention is not limited to this. The power factor correction circuit 1 may include two or more first arm circuits 17 that are connected in parallel and controlled by the first and second gate pulse signals P ₁ and P ₂ .

Further, the first arm circuit 17 has included a first switching element to Q ₁ high side one is not limited to this. The first arm circuit 17, the source - drain paths connected in parallel, is controlled by the first gate pulse signals P _1, may contain two or more switching elements of the high side. Further, the first arm circuit 17 is includes a second switching element Q ₂ of one of the low side, but is not limited thereto. The first arm circuit 17, the source - drain paths connected in parallel and controlled by a second gate pulse signals P _2, may include two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Power factor correction circuit 1 includes a third and fourth switching elements _{Q 3} and _{Q 4.} The second input terminal 12, the source of the third switching element Q ₃ - via the drain path is connected to the first output terminal 14. The second input terminal 12, the drain of the fourth switching element Q ₄ - via the source path is connected to the second output terminal 15.

The third and fourth switch elements Q ₃ and Q ₄ constitute a polarity switching arm circuit 18.

Polarity switching arm circuit 18 has included one third switching element Q ₃ of the high side, but is not limited thereto. Polarity switching arm circuit 18, the source - drain paths connected in parallel, is controlled by the third gate pulse signals P _3, may contain two or more switching elements of the high side. The polarity switching arm circuit 18 has included a fourth switching element Q ₄ of one of the low side, but is not limited thereto. Polarity switching arm circuit 18, the source - drain paths connected in parallel and controlled by a fourth gate pulse signal P _4, may contain two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Power factor correction circuit 1 includes a switching element _{Q 5} and _{Q 6} of the fifth and sixth. The second node N ₂ is the fifth source of the switch element Q ₅ - through the drain path, and is connected to the first output terminal 14. The second node N ₂ is connected to the second output terminal 15 via the drain-source path of the sixth switch element Q ₆ .

The second inductor L ₂ and the fifth and sixth switch elements Q ₅ and Q ₆ constitute a second arm circuit 19.

The second arm circuit 19 may be referred to as a slave arm or a master arm. In the present embodiment, the power factor correction circuit 1 includes one second arm circuit 19, but the present invention is not limited to this. The power factor correction circuit 1 may include two or more second arm circuits 19 connected in parallel and controlled by the fifth and sixth gate pulse signals P ₅ and P ₆ . The number of the second arm circuits 19 and the number of the first arm circuits 17 are preferably the same.

The second arm circuit 19 has included switching element Q ₅ of one fifth high side, but is not limited thereto. The second arm circuit 19, the source - drain paths connected in parallel, is controlled by the gate pulse signal P ₅ of the fifth, it may contain two or more switching elements of the high side. The second arm circuit 19 has included switching element Q ₆ of the sixth one of the low side, but is not limited thereto. The second arm circuit 19, the source - drain paths connected in parallel, is controlled by the gate pulse signal P ₆ of the sixth, it may contain two or more switching elements of the low-side. The number of high-side switch elements and the number of low-side switch elements are preferably the same.

Input current _{I in} is input to the first input terminal 11, the current _{I 1} flowing in the first arm circuit 17, a current _{I 2} flowing in the second arm circuit 19 is the sum of.

In this embodiment, although the first switching element Q ₁ until the switch element Q ₆ of the sixth was to be a N-channel MOSFET, but is not limited thereto. From the first switching element _{Q 1} until the switch element _{Q 6} of the sixth, silicon power devices, GaN power devices, SiC power devices, IGBT (Insulated Gate Bipolar Transistor) or the like.

From the first switching element Q ₁ until the switch element Q ₆ of the sixth, from the first parasitic diode (body diode) D ₁ to the parasitic diode D ₆ of the sixth, respectively Yes. The parasitic diode is a pn junction between the back gate and the source and drain of the MOSFET. From the first parasitic diode D ₁ to the parasitic diode D ₆ of the sixth, freewheel for missing a transient counter electromotive force at the time of off from the first switching element Q ₁ until the switch element Q ₆ of the sixth It can be used as a diode.

  The power factor correction circuit 1 includes a control unit 50. The control unit 50 can be realized using a CPU (Central Processing Unit) and a program.

Control unit 50, depending on the polarity of the input voltage V _in, the gate of the first switching element Q ₁ until the switch element Q ₆ of the sixth - by controlling the voltage between the source, the first switching element Q controlling the switching operation from _one to the switch element Q ₆ of the sixth. Control unit 50, PWM (Pulse Width Modulation) is a signal, from the first gate pulse signals _{P 1} to the gate pulse signal _{P 6} of the sixth switching element _{Q 6} of the first sixth from the switch element _{Q 1} Output to each of the gates. Note that the first gate pulse signals P ₁ to the gate pulse signal P ₆ of the sixth, the dead time t _d is set. Dead time _{t d} is about 10ns are exemplified by 1 ns, but is not limited thereto.

Control unit 50 compares the input current I _in and the threshold Tharufa, when the input current I _in is greater than the threshold Tharufa may operate both of the first arm circuit 17 and the second arm circuit 19 controls I do. On the other hand, the control unit 50 performs control to operate only the first arm circuit 17 (or only the second arm circuit 19) when the input current I _in is equal to or less than the threshold Thα. In the present embodiment, the control for operating both the first arm circuit 17 and the second arm circuit 19 is referred to as double arm control, and only the first arm circuit 17 (or only the second arm circuit 19). The control to operate is called single arm control.

  The control unit 50 includes a coefficient storage unit 51, a peak input current calculation unit 52, a threshold value calculation unit 53, a determination unit 54, and a drive unit 55.

  The coefficient storage unit 51 stores a coefficient α for calculating the threshold value Thα. The coefficient α may be rewritable via wired communication or wireless communication. The coefficient α is exemplified by 0.5, but is not limited thereto.

The instantaneous voltage of the input voltage _{V in,} the first, the second, switching element to _Q 1 fifth and _6, Q 2, _{Q 5} and _{Q 6,} on the in one period in the case of performing double-arm control The product of the time T _on-d can be used as an index value representing the input current I _in .

Therefore, the peak input current calculation unit 52 calculates the peak value I _in-p of the input current I _in based _on the instantaneous voltage of the input voltage V _in and the on time T _on-d .

The threshold value calculation unit 53 calculates the threshold value Thα by the product of the peak value I _in-p of the input current I _in and the coefficient α. When the coefficient α is set to 0.5, the threshold Thα is ½ of the peak value I _in-p of the input current I _in .

The coefficient α is preferably set according to the capability of the second across the line capacitor 33. For example, the larger the electrostatic capacity of the second across the line capacitor 33, the smaller the voltage ripple of the second across the line capacitor 33. That is, the larger the electrostatic capacity of the second across-the Line capacitor 33 be larger current ripple of the input current I _in is, the voltage ripple of the second across-the Line capacitor 33 is kept small. Accordingly, the larger the capacitance of the second across-the-line capacitor 33, the larger the coefficient α can be set.

Further, the higher the withstand voltage of the second across the line capacitor 33, the more the second across the line capacitor 33 can withstand a large voltage ripple. In other words, the greater the breakdown voltage of the second across-the Line capacitor 33 is large, even larger current ripple of the input current I _in is the second across-the Line capacitor 33, withstand voltage ripple. Therefore, the larger the withstand voltage of the second across-the-line capacitor 33, the larger the coefficient α can be set.

  Therefore, for example, the coefficient α is set to be larger as the capacitance or withstand voltage of the second across the line capacitor 33 is larger, with the base value 0.5, and the capacitance of the second across the line capacitor 33 or It is possible to set the smaller as the withstand voltage is smaller.

The determination unit 54 calculates the current input current I _in based _on the instantaneous voltage of the input voltage V _in and the ON time T _on-d . Then, the determination unit 54 compares the input current I _in with the threshold value Thα, and when the input current I _in is larger than the threshold value Thα, the determination at the low level for causing the drive unit 55 to perform double arm control. and it outputs the signals _{S 1} to the drive unit 55. On the other hand, when the input current I _in is equal to or less than the threshold Thα, the determination unit 54 outputs a high-level determination signal S ₁ for causing the drive unit 55 to perform single arm control.

In this embodiment, the peak input current calculation unit 52 and determination unit 54, based on the first voltage detector 13 input voltage V _in is detected by the on-time and T _on-d, the input current I _{Although in} is calculated, it is not limited to this. Power factor correction circuit 1 may comprise a current detector for detecting an input current I _in. In the present embodiment, the peak input current calculation unit 52 and the determination unit 54 calculate the input current I _in based _on the input voltage V _in detected by the first voltage detector 13 and the on-time T _on-d. The reason for the calculation is as follows.

In order for the drive unit 55 to calculate the first, second, fifth, and sixth gate pulse signals P ₁ , P ₂ , P _5, and P ₆ , the power factor correction circuit 1 includes the first voltage detector 13. And a second voltage detector 16 must be provided. Therefore, the peak input current calculation unit 52 and determination unit 54, based on the detected input voltage V _in and the on-time and T _on-d in the first voltage detector 13, if calculating the input current This is because it is not necessary to add new hardware (current detector).

Drive unit 55, when the determination signals S ₁ supplied from the determining unit 54 is at the low level, performs a double arm control. Drive unit 55, when the determination signal S ₁ is at the high level, it performs single arm control.

Drive unit 55 is in each case a double arm control and single arm control, so that the output voltage V _out is equal to the target voltage (400V), from the first switch element Q ₁ until the switch element Q ₆ of the sixth To control.

Drive unit 55, when performing double-arm control, the input voltage V _in detected by the first voltage detector 13, the output voltage V _out which is detected by the second voltage detector 16, on the basis , First, second, fifth and sixth gate pulse signals P ₁ , P ₂ , P ₅ and P ₆ (switching frequency), on-time T _on-d , first arm circuit 17, The phase difference time t _diff with the second arm circuit 19 is calculated. Based on the calculated frequency, the on time T _on-d, and the phase difference time t _diff , the driving unit 55 performs the first, second, fifth, and sixth gate pulse signals P ₁ , P ₂ , P ₅ and P ₆ are output to the gates of the first, second, fifth and sixth switch elements Q ₁ , Q ₂ , Q ₅ and Q ₆ , respectively.

Drive unit 55, when performing single-arm control, the input voltage V _in detected by the first voltage detector 13, the output voltage V _out which is detected by the second voltage detector 16, on the basis The frequency (switching frequency) of the first and second gate pulse signals P ₁ and P ₂ and the on-time T _on-s are calculated.

Driving unit 55, in a single arm control period for single arm control, the first switching element Q ₁ and the second on-time switching element Q ₂ T _on-s, performs double arm control in a single-arm control period Assuming that the ON time T _on-d of the first switch element Q1 and the second switch element Q2 is doubled. That is, the drive unit 55 sets T _on-s = 2 · T _on-d . This is because when the double arm control is performed, the two arm circuits of the first arm circuit 17 and the second arm circuit 19 perform power conversion. When performing the single arm control, the first arm circuit 17 and the second arm circuit 19 perform the first conversion. This is because only the arm circuit 17 is responsible for power conversion. That is, when single arm control is performed, the first arm circuit 17 has to perform power conversion twice as much as that when double arm control is performed. The drive unit 55 _converts the first and second gate pulse signals P ₁ and P ₂ into the first and second switch elements Q ₁ and Q 2 based _on the calculated frequency and the on time T _{on-s. 2} is output to each gate.

  The operation of the control unit 50 during double arm control will be described.

Control unit 50, the polarity of the input voltage V _in the case of the positive phase is on the third switching element Q ₃ off and and the fourth of the switching element Q ₄ of polarity switching arm circuit 18.

Then, the control unit 50, the third switching element Q ₃ off to state and turned on the fourth switch element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / while controlling to switch off, and controls so that the switching element Q ₅ and Q ₆ of the fifth and sixth switches the complementarily turned on / off.

For example, the control unit 50, when the input voltage _{V in} is positive-phase, second, fourth and switching element _Q 2, _{Q 4} and _{Q 6} was turned on while the first sixth, third and fifth From the first state in which the switch elements Q ₁ , Q _3, and Q ₅ are turned off, the second switch element Q ₂ is turned off and the first switch element Q ₁ is turned on.

Further, the control unit 50, after controlling the second state, the second state is controlled to the third state of turning off the switch element Q ₆ of the sixth.

And after controlling to the 3rd state, control part 50 is controlled from the 3rd state to the 4th state which turned on _5th switch element Q5.

The control unit 50, after controlling the fourth state, the fourth state is controlled to a fifth state in which off the first switching element Q _1.

And after controlling to the 5th state, control part 50 is controlled from the 5th state to the 6th state which turned on _2nd switch element Q2.

Further, after controlling to the sixth state, the control unit 50 controls from the sixth state to the seventh state in which the _fifth switch element Q5 is turned off.

And after controlling to the 7th state, control part 50 is controlled from the 7th state to the 8th state which turned on _6th switch element Q6.

Further, after controlling to the eighth state, the control unit 50 controls from the eighth state to the ninth state in which the _second switch element Q2 is turned off.

Then, after controlling to the ninth state, the control unit 50 controls from the ninth state to the tenth state in which the _first switch element Q1 is turned on.

By the control described above, when the polarity of the input voltage V _in is positive phase, the current I ₁ and I ₂ are applied through the fourth switching element Q _4, will flow to the second input terminal 12 .

On the other hand, the control unit 50, when the polarity of the input voltage V _in is reversed phase, turns off the third switching element Q ₃ ON and and fourth switching elements Q ₄ of polarity switching arm circuit 18 .

Then, the control unit 50, the third switching element Q ₃ at ON and state and turning off the fourth switching element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / while controlling to switch off, and controls so that the switching element Q ₅ and Q ₆ of the fifth and sixth switches the complementarily turned on / off.

This control, when the polarity of the input voltage V _in is reversed phase, currents I ₁ and I ₂ is allowed to flow to the first input terminal 11 via a third switching element Q _3.

The polarity of the input voltage V _in when it is reversed phase, while controlling to switch complementarily turned on / off first and second switching elements Q ₁ and Q _2, the fifth and sixth specific operations for controlling to switch complementarily turned on / off the switch element Q ₅ and Q ₆ from a first state when the input voltage V _in the above are positive-phase up to the 10 state It is the same as the control.

FIG. 2 is a diagram illustrating an example of operation waveforms of the power factor correction circuit according to the first embodiment. 2, when the polarity of the input voltage V _in is positive phase is a diagram illustrating an example of operation waveforms at the time of double-arm control of the power factor correction circuit 1.

Control unit 50, when the input voltage _{V in} is positive-phase, second, fourth and sixth switching element _Q 2, _{Q 4} and _{Q 6} turned on and the first to the third and fifth switch The elements Q ₁ , Q _3, and Q ₅ are controlled to the first state that is turned off. Next, the control unit 50, at the timing _{t 1,} turns off the second switching element _{Q 2.} Next, the control unit 50 at a timing t ₂ after elapse of the dead time t _d from the timing t _1, and controls the second state in which the on-first switching element Q _1.

Next, the control unit 50 at a timing t _3, from the second state to control the third state of turning off the switch element Q ₆ of the sixth. Next, the control unit 50 at a timing t ₄ after the dead time t _d has elapsed from the timing t _3, and controls the fourth state in which turns on the switch element Q ₅ of the fifth. A period from timing t ₂ to timing t ₄ is a phase difference time t _diff between the first arm circuit 17 and the second arm circuit 19.

Next, the control unit 50, at the timing t _5, the fourth state is controlled to a fifth state in which off the first switching element Q _1. Period from the timing _{t 2} to time _{t 5} is the on-time _{T on-d.} Next, the control unit 50, at the timing t ₆ after the dead time t _d has elapsed from the timing t _5, and controls the sixth state of that on the second switching element Q _2. Next, the control unit 50, at the timing t _7, the sixth state of controls to the seventh state of turning off the switching element Q ₅ of the fifth. Period from the timing _{t 4} to time _{t 7} is the on-time _{T on-d.}

Next, the control unit 50 at a timing t ₈ of the dead time t _d after the timing t _7, the seventh state, to control the state of the 8 turns on the switch element Q ₆ of the sixth. Next, the control unit 50 at a timing t _9, the state of the 8 controls the ninth state of turning off the second switching element Q _2. Period from the timing _{t 6} to the time _{t 9} is the on-time _{T on-d.} Next, the control unit 50, the dead time _{t d} has elapsed timing _{t 10} after the timing _{t 9,} the ninth state is controlled to a tenth state of the turn on the first switching element _{Q 1.}

  Thereafter, the control unit 50 performs similar control.

Note that the second gate pulse signals P ₂ phases for controlling the second switching element Q _2, the phase and the sixth switch element Q ₆ gate pulse signal P ₆ of the sixth to control the And the phase difference time t _diff . Similarly, the phase of the first gate pulse signal P ₁ for controlling the _first switch element Q ₁ and the phase of the fifth gate pulse signal P ₅ for controlling the _fifth switch element Q ₅ Is shifted by the phase difference time t _diff .

  An operation during single arm control of the control unit 50 will be described.

  The first arm circuit 17 has a circuit configuration similar to that of the boost chopper circuit. Therefore, the power factor correction circuit 1 performs the same operation as the step-up chopper circuit in the case of single arm control.

More specifically, the control unit 50, when the polarity of the input voltage V _in is positive phase, the third switching element Q ₃ is turned off and the fourth switching element Q ₄ of polarity switching arm circuit 18 Turn on.

Then, the control unit 50, the third switching element Q ₃ off to state and turned on the fourth switch element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / Control to switch off.

For example, the control unit 50, when the input voltage V _in is positive phase, turned on and the first and the second and fourth switching elements Q ₂ and Q _4, the third, fifth and sixth switching elements Control is performed from the first state in which Q ₁ , Q ₃ , Q _5, and Q ₆ are turned off to the second state in which the second switch element Q ₂ is turned off and the first switch element Q ₁ is turned on.

Further, the control unit 50, after controlling the second state, the second state is controlled to the third state in which off the first switching element Q _1. And after controlling to the 3rd state, control part 50 is controlled from the 3rd state to the 4th state which turned on _2nd switch element Q2. The control unit 50, after controlling the fourth state, the fourth state is controlled to a fifth state in which turning off the second switching element Q _2.

By the control described above, when the polarity of the input voltage V _in is positive phase current I ₁ through the fourth switching element Q _4, will flow to the second input terminal 12.

On the other hand, the control unit 50, when the polarity of the input voltage V _in is reversed phase, turns off the third switching element Q ₃ ON and and fourth switching elements Q ₄ of polarity switching arm circuit 18 .

Then, the control unit 50, the third switching element Q ₃ at ON and state and turning off the fourth switching element Q _4, complementarily turned on the first and second switching elements Q ₁ and Q ₂ / Control to switch off.

This control, when the polarity of the input voltage V _in the reverse phase, the current I ₁ is allowed to flow to the first input terminal 11 via a third switching element Q _3.

The polarity of the input voltage V _in when it is reversed phase, specific operation of controlling so that the first and second switching elements Q ₁ and Q ₂ switches the complementarily turned on / off, the above input voltage V _in is the same as the control from the first state when a positive phase to a fifth state.

FIG. 3 is a diagram illustrating an example of operation waveforms of the power factor correction circuit of the comparative example. FIG. 3 is a diagram illustrating an example of an operation waveform of the power factor correction circuit 1 when the double arm control is performed in the entire period 81 _{in which} the polarity of the input voltage Vin is _in the positive phase.

When the double arm control is performed in the period 81 _{in which} the polarity of the input voltage Vin is positive phase, the envelope of the current I ₁ flowing through the first arm circuit 17 and the envelope of the current I ₂ flowing through the second arm circuit 19 are used. The line is sinusoidal.

FIG. 4 is a diagram illustrating an example of operation waveforms of the power factor correction circuit according to the first embodiment. 4, when the polarity of the input voltage V _in is positive phase is a diagram illustrating an example of operation waveforms of the power factor correction circuit 1.

When the coefficient α is set to 0.5, a period 72 _in which the input current I _in is larger than ½ of the peak value I _in-p of the input current I _in is a period during which double arm control is performed. . The periods 71 and 73 _in which the input current I _in is ½ or less of the peak value I _in-p of the input current I _in are periods during which single arm control is performed.

In the period 72, the control unit 50 performs double arm control. Therefore, in the period 72, the waveform of the current _{I 1} and _{I 2,} is the same as Comparative Example (see FIG. 3).

In the periods 71 and 73, the control unit 50 operates only the first arm circuit 17 and does not operate the second arm circuit 19. Therefore, in the period 71 and 73, the current _{I 2} flowing through the second arm circuit 19 is 0. On the other hand, in the periods 71 and 73, the first arm circuit 17 must perform power conversion up to the second arm circuit 19. In the periods 71 and 73, T _on-s = 2 · T _on-d . Therefore, in the period 71 and 73, the current _{I 1} flowing through the first arm circuit 17 will generally twice the current _{I 1} of the same period of the comparative example (see FIG. 3).

As described above, the power factor correction circuit 1 performs double arm control in a region where the input current I _in is larger than the threshold Th.

Since the currents I ₁ and I ₂ are large in the region where the input current I _in is larger than the threshold Th, there is a great merit that the currents I ₁ and I ₂ cancel each other.

Further, in a region input voltage _{V in} is large, the increased amount of pressure for boosting the input voltage _{V in} to an output voltage _{V out} is small, the first, second, switching element to _Q 1 fifth and _{6, Q} 2, Q It is sufficient to switch ₅ and Q ₆ with a long period, that is, with a low switching frequency. When the switching cycle of the first, second, fifth and sixth switch elements Q ₁ , Q ₂ , Q ₅ and Q ₆ is long, the demerit of the control burden of the control unit 50 is small.

Further, if the switching cycle of the first, second, fifth and sixth switch elements Q ₁ , Q ₂ , Q ₅ and Q ₆ is long, the first, second, fifth and sixth switch elements Q ₁ , Q ₂ , Q ₅ and Q ₆ have a small absolute amount of switching loss and gate driving loss. In addition, the area input voltage V _in is high, the conversion power is large area. Therefore, the ratio of the switching loss and gate drive loss of the first, second, fifth and sixth switch elements Q ₁ , Q ₂ , Q ₅ and Q ₆ to the converted power is low. That is, the demerit of power efficiency reduction is small.

Therefore, the power factor correction circuit 1, the input current I _in is the threshold Th larger area, by performing the double-arm control can reduce the second across-the Line ripple current of the capacitor 33 and the output capacitor C _1, the power It is possible to improve efficiency.

The power factor correction circuit 1 performs single arm control in a region where the input current I _in is equal to or less than the threshold Th.

Input current _{I in} is the threshold Th or less of the area, that is, in the vicinity of the zero crossing of the input voltage _{V in,} the current _{I 1} and _{I 2} is small, a small advantage that the current _{I 1} and _{I 2} cancel each other.

Further, in the vicinity of the zero crossing of the input voltage _{V in,} since a large step-up amount for boosting the input voltage _{V in} to an output voltage _{V out,} first, second, switching element to _Q 1 fifth and _{6, Q} 2, Q it is necessary to switch the ₅ and Q ₆ in a short cycle. If the switching cycle of the first, second, fifth and sixth switch elements Q ₁ , Q ₂ , Q ₅ and Q ₆ is short, there is a demerit that the control load of the control unit 50 is large.

When the switching cycle of the first, second, fifth, and sixth switch elements Q ₁ , Q ₂ , Q _5, and Q ₆ is short, the first, second, fifth, and sixth switch elements Q ₁ , Q ₂ , Q ₅ and Q ₆ have a large amount of switching loss and gate drive loss. In addition, near the zero crossing of the input voltage V _in is an area conversion power is small. Therefore, the ratio of the switching loss and gate drive loss of the first, second, fifth and sixth switch elements Q ₁ , Q ₂ , Q ₅ and Q ₆ to the converted power is high. That is, the demerit of power efficiency reduction is great.

Therefore, the power factor correction circuit 1, the input current I _in is the threshold Th or less of the area, by performing a single-arm control, to suppress the switching operation of the switching element Q ₅ and Q ₆ of the fifth and sixth, by suppressing the switching loss and the gate drive loss of the fifth and the switch element Q ₅ and Q ₆ of the sixth, it is possible to achieve power efficiency.

  When the coefficient α is set to 0.5, the ratio between the period for performing single arm control (sum of period 71 and period 73) and the period for performing double arm control (period 72) is as follows. , Approximately 1: 1. Thereby, the balance of the merit and demerit of single arm control and the merit and demerit of double arm control becomes suitable.

The control unit 50, when the polarity is positive polarity and a single arm control input voltage V _in is allowed to operate only the first arm circuit 17, the polarity of the input voltage V _in is located at the opposite polarity When performing single arm control, only the second arm circuit 19 may be operated. Thereby, the power factor correction circuit 1 can suppress the deviation between the heat generation of the first arm circuit 17 and the heat generation of the second arm circuit 19.

(Second Embodiment)
In the first embodiment, the target voltage of the output voltage _Vout is 400V. However, there may be a case where the target voltage of the output voltage _Vout changes. For example, the load 4 may require 400 V during normal operation, but may require 390 V during low voltage (low power consumption) operation (eg, in sleep mode).

In the second embodiment, the target voltage of the output voltage V _out is changed to a first target voltage (for example, 400 V) and a second target voltage (for example, 390 V).

  FIG. 5 is a diagram illustrating a circuit configuration of the power factor correction circuit according to the second embodiment. The same constituent elements as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The power factor correction circuit 1A includes a control unit 50A in place of the control unit 50 of the first embodiment. Control unit 50A includes a coefficient storage unit 51A, a peak input current calculation unit 52, a threshold value calculation unit 53A, a determination unit 54A, a drive unit 55A, and an output voltage threshold value storage unit 56.

  The coefficient storage unit 51A stores coefficients α and β for calculating threshold values Thα and Thβ. The coefficients α and β may be rewritable via wired communication or wireless communication. The coefficient α is exemplified by 0.5, but is not limited thereto. The coefficient β is exemplified by 0.4, but is not limited thereto.

  When the second target voltage (390V) is lower than the first target voltage (400V), the coefficient β is preferably smaller than the coefficient α. When the second target voltage (for example, 410V) is higher than the first target voltage (400V), the coefficient β is preferably larger than the coefficient α.

The threshold value calculation unit 53A calculates the threshold value Thα by the product of the peak value I _in-p of the input current and the coefficient α. Further, the threshold value calculation unit 53A calculates the threshold value Thβ by the product of the peak value I _in-p of the input current and the coefficient β.

The output voltage threshold storage unit 56 stores the threshold V _th of the output voltage V _out . The threshold value V _th may be rewritable via wired communication or wireless communication. The threshold value _Vth is a value between the first target voltage (400V) and the second target voltage (390V). For example, the threshold V _th is 395 V, but is not limited thereto. The threshold value _Vth may be 394V or 396V.

The determination unit 54A compares the output voltage _Vout with the threshold value _Vth . When the output voltage _Vout is greater than the threshold value _Vth , the determination unit 54A selects a threshold value Thα _out of the threshold values Thα and Thβ. When the output voltage _Vout is equal to or lower than the threshold value _Vth , the determination unit 54A selects a threshold value Thβ among the threshold values Thα and Thβ.

Determination unit 54A includes a instantaneous voltage of the input voltage _{V in,} and the on-time _{T on-d,} based on, to calculate the current of the input current _{I in.} Then, the determination unit 54A compares the input current I _in with the selected threshold value among the threshold values Thα and Thβ. Determination unit 54A, when the input current I _in is greater than the selected threshold, the output for causing the double-arm control to the driving unit 55A, a low-level determination signals S ₁ to the drive unit 55A. On the other hand, the determination unit 54A, when the following input current I _in has selected threshold, the output for causing the single arm control the driving unit 55A, a high-level decision signals S ₁ to the drive unit 55A.

The drive unit 55A, the signal S ₂ that specifies the target voltage is supplied. If the signal _{S 2} is at the low level, the first target voltage (400V) is specified. If the signal _{S 2} is at the high level, the second target voltage (390 V) is designated.

The drive unit 55A includes a first switch so that the output voltage _Vout becomes the first target voltage (400V) or the second target voltage (390V) in both cases of double arm control and single arm control. controlling the from element _{Q 1} until the switch element _{Q 6} of the sixth. Since the specific control content of the drive unit 55A is the same as that of the drive unit 55 of the first embodiment, the description thereof is omitted.

When the second target voltage (390V) is specified and the output voltage _Vout decreases, the threshold Thα for the first target voltage (400V) is used, and the single arm control period (period of FIG. 4) is used. 71 and 73) are not changed, but the double arm control period (see period 72 in FIG. 4) is shortened, and the merit of the double arm control is reduced.

Therefore, the power factor correction circuit 1A stores two coefficients α and β, and selects one of the coefficients α and β according to the output voltage V _out . As a result, the power factor correction circuit 1A can adjust the balance between the single arm control period (see periods 71 and 73 in FIG. 4) and the double arm control period (see period 72 in FIG. 4). Thereby, 1 A of power factor improvement circuits can suppress that the merit of double arm control will reduce.

  Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof as well as included in the scope and gist of the invention.

DESCRIPTION OF SYMBOLS 1, 1A Power factor improvement circuit 2 Power supply 3 Noise filter 4 Load 11 1st input terminal 12 2nd input terminal 13 1st voltage detector 14 1st output terminal 15 2nd output terminal 16 2nd voltage Detector 17 First arm circuit 18 Polarity switching arm circuit 19 Second arm circuit 50, 50A Control unit 51, 51A Coefficient storage unit 52 Peak input current calculation unit 53, 53A Threshold calculation unit 54, 54A Determination unit 55, 55A Drive unit 56 Output voltage threshold storage unit L ₁ 1st inductor L ₂ 2nd inductor Q ₁ 1st switch element Q ₂ 2nd switch element Q ₃ 3rd switch element Q ₄ 4th switch element Q ₅ Fifth switch element Q ₆ sixth switch element C ₁ output capacitor N ₁ first node N ₂ second node

Claims (8)

A pair of first and second input terminals to which an alternating voltage is input;
A pair of first and second output terminals that output a DC voltage;
An output capacitor connected between the first output terminal and the second output terminal;
A first inductor connected between the first input terminal and a first node; a first switch element connected between the first node and the first output terminal; and One or more first arm circuits having at least a second switch element connected between the first node and the second output terminal;
A third switch element connected between the second input terminal and the first output terminal; and a fourth switch element connected between the second input terminal and the second output terminal. A polarity switching arm having at least a switching element;
A second inductor connected between the first input terminal and a second node; a fifth switch element connected between the second node and the first output terminal; and One or more second arm circuits having at least a sixth switch element connected between the second node and the second output terminal;
A control unit that controls a switching operation from the first switch element to the sixth switch element according to the polarity of the AC voltage;
With
The controller is
An input current input to the first input terminal is compared with a threshold value, and if the input current is larger than the threshold value, both the first arm circuit and the second arm circuit are operated. Double arm control is performed, and when the input current is less than or equal to the threshold value, single arm control for operating only the first arm circuit is performed.
A power factor correction circuit characterized by that. The controller is
When the on-time of the first switch element and the second switch element in the single arm control period in which the single arm control is performed is assumed to be performed in the single arm control period, the second arm control is performed. 2 times the on-time of one switch element and the second switch element,
The power factor correction circuit according to claim 1, wherein: The controller is
Based on the instantaneous voltage of the AC voltage and the ON time of the first switch element and the second switch element when performing the double arm control, the peak value of the input current is calculated,
The threshold value is calculated by a product of a peak value of the input current and a predetermined coefficient.
The power factor correction circuit according to claim 1, wherein the power factor correction circuit according to claim 1. The coefficient is 0.5.
The power factor correction circuit according to claim 3, wherein: The controller is
A plurality of the threshold values are calculated by a product of the peak value of the input current and each of a plurality of predetermined coefficients,
Selecting one of the thresholds according to the value of the DC voltage;
The power factor correction circuit according to claim 3, wherein: The controller is
When the DC voltage is greater than a predetermined voltage threshold, a first threshold is selected from the plurality of thresholds, and when the DC voltage is less than or equal to a predetermined voltage threshold, a plurality of Selecting a second threshold value smaller than the first threshold value among the threshold values;
The power factor correction circuit according to claim 5, wherein: The controller is
When the polarity of the AC voltage is positive and the single arm control is performed, only the first arm circuit is operated, and the polarity of the AC voltage is the reverse polarity and the single arm control is performed. To operate only the second arm circuit,
The power factor correction circuit according to claim 1, wherein: A pair of first input terminal and second input terminal to which an AC voltage is input, a pair of first output terminal and second output terminal for outputting a DC voltage, the first output terminal, and the first An output capacitor connected between the two output terminals, a first inductor connected between the first input terminal and the first node, and the first node and the first output terminal. And one or more first arm circuits having at least a second switch element connected between the first node and the second output terminal. And a third switch element connected between the second input terminal and the first output terminal, and connected between the second input terminal and the second output terminal. A polarity switching arm having at least a fourth switch element; A second inductor connected between an input terminal and a second node; a fifth switch element connected between the second node and the first output terminal; and One or more second arm circuits having at least a sixth switch element connected between a node and the second output terminal, and the first switch element to the second switch according to the polarity of the AC voltage. A control unit that controls a switching operation up to 6 switch elements, and a control method of a power factor correction circuit comprising:
The control unit compares an input current input to the first input terminal with a threshold value. When the input current is larger than the threshold value, the first arm circuit and the second arm circuit are compared. Double arm control is performed to operate both, and when the input current is less than the threshold value, single arm control is performed to operate only the first arm circuit.
A method for controlling a power factor correction circuit.

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