JP2015023606A - Power-factor correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve interleaving and downsizing of a bridge-less PFC circuit with a small number of components.SOLUTION: A PFC circuit includes: a MOSFET 31 connected between an input terminal 12 and an output terminal 41; a MOSFET 32 connected between the input terminal 12 and an output terminal 42; a first arm circuit; a second arm circuit; and an output capacitor 37 connected between the output terminals 41 and 42. The first arm circuit has an inductor 21 connected between an input terminal 11 and a connection point N11, a MOSFET 33 connected between the connection point N11 and the output terminal 41, and a MOSFET 34 connected between the connection point N11 and the output terminal 42. The second arm circuit has an inductor 22 connected between the input terminal 11 and a connection point N12, a MOSFET 35 connected between the connection point N12 and the output terminal 41, and a MOSFET 36 connected between the connection point N12 and the output terminal 42.

Description

  The present invention relates to a power factor correction (hereinafter referred to as “PFC”) circuit provided in a power supply device or the like, for example, an interleaved PFC circuit.

  For example, a PFC circuit provided in a power supply device includes a bridge diode that rectifies an alternating current (hereinafter referred to as “AC”) voltage, a booster circuit, and a smoothing output capacitor. In order to reduce the loss of the PFC circuit, a bridgeless circuit configuration without a bridge diode has been proposed. The bridgeless PFC circuit has a direct circuit configuration in which a booster circuit is provided for each AC line, and rectification and boosting operations are performed simultaneously. Interleaving is effective to achieve a lower loss. The interleaved PFC circuit includes a plurality of booster circuits whose phases are shifted from each other and a common output capacitor.

  FIG. 4 is a circuit diagram showing a configuration of a conventional interleaved bridgeless PFC circuit described in Non-Patent Document 1.

  This PFC circuit has a pair of input terminals 1-1 and 1-2 to which an AC input voltage Vin (for example, 50/60 Hz) is applied. A boosting inductor 2-1 is connected between one input terminal 1-1 and the connection point N1, and a boosting inductor 2- is also connected between the input terminal 1-1 and the connection point N3. 2 is connected. A boosting inductor 2-3 is connected between the other input terminal 1-2 and the connection point N2, and a boosting inductor 2- is also connected between the input terminal 1-2 and the connection point N4. 4 is connected.

  The connection point N1 is one of the output terminals 6-1 and 6-2 that outputs a direct current (hereinafter referred to as “DC”) output voltage Vout via the forward diode 3-1. Further, the connection point N1 is connected to the other output terminal 6-2 via the MOSFET 4-1. The node N2 is connected to one output terminal 6-1 via a forward diode 3-2, and the node N2 is further connected to the other output terminal 6-2 via a MOSFET 4-2. It is connected. The connection point N3 is connected to one output terminal 6-1 via a forward diode 3-3, and the connection point N3 is connected to the other output terminal 6-2 via a MOSFET 4-3. It is connected. The connection point N4 is connected to one output terminal 6-1 via a forward diode 3-4, and the connection point N4 is connected to the other output terminal 6-2 via a MOSFET 4-4. It is connected. A parasitic diode 4a called a body diode is connected between the drain and source of each of the MOSFETs 4-1 to 4-4.

  A smoothing output capacitor 5 and a load 7 are connected in parallel between the pair of output terminals 6-1 and 6-2.

  The inductors 2-1 and 2-3, the diodes 3-1 and 3-2, and the MOSFETs 4-1 and 4-2 constitute a first booster circuit. Further, the inductors 2-2 and 2-4, the diodes 3-3 and 3-4, and the MOSFETs 4-3 and 4-4 constitute a second booster circuit. The first booster circuit and the second booster circuit perform interleave operations with different phases.

  In the PFC circuit having such a configuration, for example, when the input terminal 1-1 is a positive voltage, the MOSFETs 4-1 and 4-3 perform switching for the boosting operation and turn on the MOSFETs 4-2 and 4-4. By continuing, the conduction loss can be reduced by the low on-resistance in the MOSFETs 4-2 and 4-4 without passing through the parasitic diodes 4a of the MOSFETs 4-2 and 4-4. Each time the AC input voltage Vin alternates, the MOSFETs 4-1 and 4-3 and the MOSFETs 4-2 and 4-4 repeat switching and ON-on. As a result, the boosted DC output voltage Vout is output from the output terminals 6-1 and 6-2 via the output capacitor 5.

Sanken Technical Report, vol. 41 (2009) Sanken Electric Co., Ltd., Chiba, Kyono “Development of High Efficiency Power Supply for Servers”, p. 31-34

  However, the conventional PFC circuit of FIG. 4 has four arms including the inductors 2-1 to 2-4 and has a complicated circuit configuration. For this reason, since the number of parts is large, there is also a problem in terms of downsizing the power supply device.

  The PFC circuit of the present invention includes a pair of first and second input terminals to which an AC voltage is input, a pair of first and second output terminals to which a DC voltage is output, and the second input terminal. And a first switch element and a first diode connected in parallel between the first output terminals; a second switch element and a second diode connected in parallel between the second input terminal and the second output terminal; , A first arm circuit, a second arm circuit, and an output capacitor connected between the first output terminal and the second output terminal.

  The first arm circuit includes a first inductor connected between the first input terminal and the first connection point, a third switch element connected in parallel between the first connection point and the first output terminal, and A third diode; and a fourth switch element and a fourth diode connected in parallel between the first connection point and the second output terminal. The second arm circuit includes a second inductor connected between the first input terminal and the second connection point, a fifth switch element connected in parallel between the second connection point and the first output terminal, and A fifth diode; and a sixth switch element and a sixth diode connected in parallel between the second connection point and the second output terminal.

The PFC circuit of the present invention has the following effects (a) to (c).
(A) Compared with the conventional PFC circuit, the bridgeless PFC circuit can be interleaved with fewer parts, and further, the power supply device and the like can be downsized.

  (B) The upper and lower third and fourth switch elements of the first arm circuit are actively turned on / off, and the upper and lower fifth and sixth switch elements of the second arm circuit are also actively turned on / off. If so, high efficiency can be achieved.

  (C) If the first and second switch elements are also turned on every positive and negative half cycle of the AC input voltage, the efficiency is further increased.

FIG. 1 is a circuit diagram showing a configuration of a PFC circuit in Embodiment 1 of the present invention. FIG. 2 is an operation waveform diagram showing the operation of each part in the FET circuit of FIG. FIG. 3A is a circuit diagram showing a current flow when the input voltage Vin of FIG. 1 is a positive half cycle. 3-2 is a circuit diagram showing a current flow when the force voltage Vin of FIG. 1 is a negative half cycle. FIG. 4 is a circuit diagram showing a configuration of a conventional PFC circuit.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of Example 1)
FIG. 1 is a circuit diagram showing a configuration of an interleaved bridgeless PFC circuit according to a first embodiment of the present invention.

  This interleaved bridgeless PFC circuit is provided in a power supply device or the like, and is a step-up circuit for outputting a DC output voltage Vout that is higher than the AC input voltage Vin (for example, 50/60 Hz). And has a pair of one input terminal 11 and a second input terminal 12 to which the input voltage Vin is applied. A first connection point N 11 is connected to the first input terminal 11 via a first inductor 21, and a second connection point N 12 is connected via a second inductor 22.

  The second input terminal 12 includes a first output terminal 41 and a second output terminal 42 that output a DC output voltage Vout through the source / drain of a first switch element (for example, an N-channel MOSFET) 31. The first output terminal 41 is connected. Further, the second input terminal 12 is connected to the second output terminal 42 via the drain / source of the second switch element (for example, N-channel MOSFET) 32.

  The first connection point N11 is connected to the first output terminal 41 via the source / drain of the third switch element (for example, N channel type MOSFET) 33, and the fourth switch element (for example, N channel type MOSFET). ) 34 is connected to the second output terminal 42 via the drain / source.

  The second connection point N12 is connected to the first output terminal 41 via the source / drain of the fifth switch element (for example, N channel type MOSFET) 35 and the sixth switch element (for example, N channel type MOSFET). ) Is connected to the second output terminal 42 through the drain / source of 36.

  Among the six MOSFETs 31 to 36, a first diode (for example, a parasitic diode) 31 a is connected in parallel in the reverse direction between the drain and source in the forward direction of the MOSFET 31. Similarly, a second diode (for example, a parasitic diode) 32a is connected in parallel in the reverse direction between the drain and source in the forward direction of the MOSFET 32, and the third diode is also connected between the drain and source in the forward direction of the MOSFET 33. (For example, a parasitic diode) 33a is connected in parallel in the reverse direction, and a fourth diode (for example, a parasitic diode) 34a is connected in parallel in the reverse direction between the drain and source in the forward direction of the MOSFET 34. A fifth diode (for example, a parasitic diode) 35a is also connected in parallel in the reverse direction between the drain and source, and a sixth diode (for example, a parasitic diode) is also connected between the drain and source in the forward direction of the MOSFET 36. 36a are connected in parallel in the opposite direction.

  The inductor 21 and the MOSFETs 33 and 34 constitute a first arm circuit. The inductor 22 and the MOSFETs 35 and 36 constitute a second arm circuit.

  A smoothing output capacitor 37 and a load 43 are connected in parallel between the first output terminal 41 and the second output terminal 42.

  When the switch drive signals S31 and S32 output from the control unit 50 are respectively applied to the gates, the MOSFETs 31 and 32 are complementarily turned on / off with the switch drive signals S31 and S32 being out of phase by 180 °. Transistor. The other MOSFETs 33 to 36 are transistors that are turned on / off at a predetermined timing when switch drive signals S33 to S36 output from the control unit 50 are respectively applied to the gates.

  The configuration of the control unit 50 includes, for example, a current continuous mode control method for operating the PFC circuit in the current continuous mode and a current critical mode control method for operating the PFC circuit in the current critical mode.

  In the control unit 50 of the continuous current mode control method, the MOSFETs 33 to 36 are turned on before the current flowing through the inductors 21 and 22 does not become zero, and the MOSFETs 33 to 36 are controlled so that the current flowing through the inductors 21 and 22 does not become zero. To do. That is, the current flowing through the inductors 21 and 22 is continuous. In general, the current waveform is controlled so that the current becomes a sine wave at a fixed frequency.

  The control unit 50 of the continuous current mode control method is a control method that uses the sine wave of the input voltage Vin as the sine wave reference voltage Vth1, for example, the divided voltage obtained by dividing the output voltage Vout and the reference voltage Vref. First differential amplification means for amplifying the difference and outputting a first differential amplification result, and multiplying the first differential amplification result and the sine wave reference voltage Vth1 to output a current detection reference voltage Vth2 And a second differential for amplifying a difference between a current detection value obtained by detecting a current flowing through the inductors 21 and 22 in the form of a voltage and a reference value Vth2 of the current detection and outputting a second differential amplification result. Amplifying means, the second differential amplification result and the triangular wave reference voltage are compared, and pulse width modulation (hereinafter referred to as “PWM”. Comparison means for generating a signal; the PWM signal is driven and the switch drive signal S31- S36 Drive means for outputting, and is composed of.

  On the other hand, in the control unit 50 of the current critical mode control method, the MOSFETs 33 to 36 are turned on after the current flowing through the inductors 21 and 22 (that is, the triangular wave current) becomes zero. If the output voltage Vout changes, the output voltage Vout is detected and the pulse width of the switch drive signals S31 to S36 is changed. When the output voltage Vout is too high, the pulse width is narrowed, and when it is too low, it is widened. For example, the control unit 50 amplifies the difference between the divided voltage obtained by dividing the output voltage Vout and the reference voltage Vref and outputs a differential amplification result having a pulse width, and inductors 21 and 22. Trigger signal generation means for generating a trigger signal delayed by a predetermined time by detecting zero of the current flowing through the pulse, pulse generation means for generating a pulse by inputting the trigger signal and the differential amplification result, and the pulse Driving means for driving and outputting switch drive signals S31 to S36.

(Operation of Example 1)
FIG. 2 is an operation waveform diagram showing the operation of each part in the FET circuit of FIG.

  FIG. 2 shows operation waveforms of the first arm circuit including the inductor 21 and the MOSFETs 33 and 34 when the control unit 50 is in the current critical mode control system. Note that the second arm circuit including the inductor 22 and the MOSFETs 35 and 36 basically operates in the same manner as the first arm circuit, and has an operation waveform shifted by 180 ° with respect to the first arm circuit.

  2, V31gs is the gate-source voltage of the MOSFET 31, V32gs is the gate-source voltage of the MOSFET 32, V33gs is the gate-source voltage of the MOSFET 33, V34gs is the gate-source voltage of the MOSFET 34, and I21 is The triangular wave current flowing through the inductor 21, V34ds is the drain-source voltage of the MOSFET 34, and V34gs is the gate-source voltage of the MOSFET 34.

  FIGS. 3-1 (1) and (2) are circuit diagrams showing the flow of current when the input voltage Vin (50/60 Hz) is a positive half cycle in FIG.

  3-1 (1) and (2), when the input voltage Vin is a positive half cycle, as shown in FIG. 2, the MOSFETs 31 and 33 are turned off by the switch drive signals S31 and S33, and the switch drive is performed. Under the ON state of the MOSFET 32 by the signal S32, the MOSFET 34 is actively turned on / off by the switch drive signal S34.

  When the MOSFET 34 is in the ON state, as indicated by an arrow in FIG. 3A (1), the input voltage Vin → the first input terminal 11 → the inductor 21 → the first connection point N11 → the drain-source between the MOSFETs 34 → the MOSFET 32 → The current I21 flows through the path from the second input terminal 12 to the input voltage Vin. At this time, the value of the current I21 increases as shown in FIG.

  When the MOSFET 34 is in the OFF state, as indicated by an arrow in FIG. 3A (2), the input voltage Vin → the first input terminal 11 → the inductor 21 → the first connection point N11 → the parasitic diode 33a of the MOSFET 33 in the OFF state → The current I21 flows through the path of the output capacitor 37 → the MOSFET 32 → the second input terminal 12 → the input voltage Vin, and the output capacitor 37 is charged. At this time, the value of the current I21 decreases as shown in FIG.

  FIGS. 3-2 (1) and (2) are circuit diagrams showing the flow of current when the input voltage Vin (50/60 Hz) is a negative half cycle in FIG.

  In FIGS. 3-2 (1) and (2), when the input voltage Vin is a negative half cycle, the operation is the reverse of the positive operation. That is, as shown in FIG. 2, the MOSFETs 32 and 34 are turned off by the switch drive signals S32 and S34, and the MOSFET 33 is actively turned on / off by the switch drive signal S33 while the MOSFET 31 is turned on by the switch drive signal S31. Turn off.

  When the MOSFET 33 is in the ON state, as indicated by an arrow in FIG. 3-2 (1), the input voltage Vin → the second input terminal 12 → the source-drain of the MOSFET 31 → the MOSFET 33 → the first connection point N11 → the inductor 21 → A current I21 flows through the path from the first input terminal 11 to the input voltage Vin. At this time, the value of the current I21 increases as shown in FIG.

  When the MOSFET 33 is in an off state, as indicated by an arrow in FIG. 3-2 (2), the input voltage Vin → the second input terminal 12 → the source-drain between the MOSFET 31 → the output capacitor 37 → the parasitic diode of the MOSFET 34 in the off state The current I21 flows through the path 34a → first connection point N11 → inductor 21 → first input terminal 11 → input voltage Vin, and the output capacitor 37 is charged. At this time, the value of the current I21 decreases as shown in FIG.

  As shown in FIG. 2, the DC output voltage Vout smoothed by the output capacitor 37 is output from between the first and second output terminals 41 and 42 and supplied to the load 43.

  The above operation is an operation when the control unit 50 is in the current critical mode control method, but is substantially the same even when the control unit 50 is in the current continuous mode control method.

(Effect of Example 1)
The PFC circuit according to the first embodiment has the following effects (a) to (f).

  (A) Compared to the conventional PFC circuit of FIG. 4, the bridgeless PFC circuit can be interleaved with fewer parts, and further, the power supply device and the like can be downsized.

  (B) The upper and lower MOSFETs 33 and 34 of the first arm circuit are actively turned on / off, and the upper and lower MOSFETs 35 and 36 of the second arm circuit are also actively turned on / off. Can be planned.

  (C) Since the MOSFETs 31 and 32 are also turned on every positive and negative half cycles of the input voltage Vin, the efficiency is further increased.

  (D) As shown in FIG. 3-1 (2), during the operation of the positive half cycle of the input voltage Vin, the MOSFET 33 in the first arm circuit is in the OFF state, so that current flows through the parasitic diode 33a. At this time, the MOSFET 33 may be turned on by the switch drive signal S33. Similarly, the MOSFET 35 in the second arm circuit may be turned on. This further reduces the loss.

  (E) As shown in FIGS. 3-1 (1) and (2), in the positive half cycle of the input voltage Vin, the current flowing through the MOSFET 32 is in one direction. Therefore, even if the MOSFET 32 is in the OFF state, a current can be passed by the parasitic diode 32a. Similarly, as shown in FIGS. 3-2 (1) and (2), in the negative half cycle of the input voltage Vin, the current flowing through the MOSFET 31 is in one direction. Therefore, even if the MOSFET 31 is in the OFF state, a current can be passed through the parasitic diode 31a. That is, the MOSFETs 31 and 32 can be kept off during one positive and negative cycle of the input voltage Vin, whereby the configuration and function of the control unit 50 can be simplified.

  (F) The operation waveform in FIG. 2 is an operation waveform when the control unit 50 is in the current critical mode control method, but has substantially the same effect even when the control unit 50 is in the current continuous mode control method. be able to.

(Modification)
The present invention is not limited to the first embodiment, and various usage forms and modifications are possible. For example, the following forms (1) to (3) are used as the usage form and the modified examples.

  (1) In the first embodiment, N-channel MOSFETs 31 to 36 are used as switching elements. However, P-channel MOSFETs, insulated gate bipolar transistors (hereinafter referred to as “IGBT”), and the like are used. Other switch elements can also be used. However, for example, when an IGBT is used, since there is no parasitic diode, it is necessary to connect an external diode in parallel to the IGBT and in the reverse direction to the forward direction of the IGBT. Become.

  (2) The control unit 50 can be configured by various individual circuits, a microcomputer, or the like.

  (3) The PFC circuit of the first embodiment can be used for various devices including a power supply device.

11, 12 First and second input terminals 21, 22 First and second inductors 31, 32, 33, 34, 35, 36 MOSFET
31a, 32a, 33a, 34a, 35a, 36a Parasitic diode 37 Output capacitor 41, 42 First and second output terminals 43 Load 50 Control unit N11, N12 First and second connection points Vin input voltage Vout output voltage

Claims (5)

A pair of first and second input terminals to which an alternating voltage is input;
A pair of first and second output terminals from which a DC voltage is output;
A first switch element and a first diode connected in parallel between the second input terminal and the first output terminal;
A second switch element and a second diode connected in parallel between the second input terminal and the second output terminal;
A first inductor connected between the first input terminal and the first connection point; a third switch element and a third diode connected in parallel between the first connection point and the first output terminal; A first arm circuit having a fourth switch element and a fourth diode connected in parallel between one connection point and the second output terminal;
A second inductor connected between the first input terminal and the second connection point; a fifth switch element and a fifth diode connected in parallel between the second connection point and the first output terminal; A second arm circuit having a sixth switch element and a sixth diode connected in parallel between two connection points and the second output terminal;
An output capacitor connected between the first output terminal and the second output terminal;
A power factor correction circuit comprising: The first diode is connected in parallel in the reverse direction to the forward direction of the first switch element,
The second diode is connected in parallel in the reverse direction with respect to the forward direction of the second switch element,
The third diode is connected in parallel in the reverse direction to the forward direction of the third switch element,
The fourth diode is connected in parallel in the reverse direction to the forward direction of the fourth switch element,
The fifth diode is connected in parallel in the reverse direction to the forward direction of the fifth switch element,
The sixth diode is connected in parallel in the reverse direction to the forward direction of the sixth switch element,
The power factor correction circuit according to claim 1, wherein: The third switch element is turned on / off by a switch drive signal while the first switch element is on.
The fourth switch element is turned on / off by a switch driving signal while the second switch element is turned on / off complementarily with respect to the first switch element.
The fifth switch element is turned on / off by a switch drive signal during the on state of the first switch element whose phase is shifted by 180 ° from the on state of the first switch element.
The sixth switch element is turned on / off by a switch drive signal during the on state of the second switch element whose phase is shifted by 180 ° from the on state of the second switch element.
The power factor correction circuit according to claim 2, wherein: The 1 switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element, and the sixth switch element are each configured by a MOSFET,
The first diode, the second diode, the third diode, the fourth diode, the fifth diode, and the sixth diode are each configured by a parasitic diode of the MOSFET. The power factor correction circuit according to any one of 1 to 3.   The one switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element, and the sixth switch element are each configured by an insulated gate bipolar transistor. The power factor correction circuit according to any one of claims 1 to 3.

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