JP4793484B2 - Resonant converter device - Google Patents

Description

  The present invention relates to a resonant converter device having a power factor correction function for which a highly efficient power converter is required.

  As a typical circuit of the resonance type power converter for reducing the switching loss, there are a method in which the DC link voltage is separated and resonance is performed, and a method in which the resonance is performed without disconnecting the DC link voltage.

  FIG. 11 is a diagram showing an example of a conventional resonant converter device that cuts off a DC link voltage. This resonant converter device includes switches Q1 to Q4, MOSFETs C1 to C4, reactors L1 and L2, capacitors C5 and C7, DC link voltage disconnecting switch Q6, resonance switch Q5, and resonance switch composed of MOSFETs constituting a full bridge. Reactor L3 and capacitor C6 for maintaining the resonance voltage are included.

  As a conventional related art, for example, an AC-DC converter described in Patent Document 1 is known.

JP-A-10-84684

  The conventional resonant converter device shown in FIG. 11 performs soft switching of the switches Q1 to Q4 by the resonant operation of the reactor L3 and the capacitors C1 to C4 connected in parallel to the switches Q1 to Q4, thereby reducing the switching loss. can do. However, loss occurs in the resonant circuit.

  In the circuit configuration shown in FIG. 11, it is necessary to disconnect the DC link voltage in order to perform the resonance operation, and the disconnecting switch Q6 must be connected to the DC line. For this reason, since a current always flows through the switch Q6, a large conduction loss occurs.

  Further, since the period of the resonance current is one sine wave period, the effective current is increased, and furthermore, the voltage cannot be increased for a certain period in the resonance operation.

  It is an object of the present invention to provide a highly efficient resonant converter device.

  In order to solve the above problems, the present invention is connected to a positive side and a negative side of a DC link, and is connected to a first series circuit composed of a first capacitor and a second capacitor, and to both ends of the first series circuit. A second series circuit comprising a first switch and a second switch; a third capacitor connected in parallel to the first switch; a fourth capacitor connected in parallel to the second switch; A third series circuit composed of a third switch and a fourth switch, connected to both ends of the one series circuit, a commercial power system, a connection point between the first switch and the second switch, and the third switch and the An LC circuit that is connected to a connection point with the fourth switch and includes a reactor and a capacitor, a connection point between the first capacitor and the second capacitor, and a connection point between the first switch and the second switch. A fourth series circuit including a bidirectional switch and a resonance reactor, PWM control of the first switch and the second switch, and the third switch and the fourth switch. By alternately turning on for a period of 180 degrees, and turning on the bidirectional switch while the first switch and the second switch are turned off, the resonance operation of the third capacitor, the fourth capacitor, and the resonance reactor is performed. And a control circuit for performing zero voltage switching.

  According to the present invention, since the control circuit alternately turns on the third switch and the fourth switch for a period of 180 degrees, loss due to high frequency switching does not occur. In addition, since the third switch and the fourth switch are turned on when a current flows through the diode, the use of an FET can reduce loss due to the synchronous rectification effect. Further, the control circuit turns on the bidirectional switch while the first switch and the second switch are off, and performs zero voltage switching by the resonance operation of the third capacitor, the fourth capacitor, and the resonance reactor. There is no turn-on loss. As a result, a highly efficient resonant converter device can be provided.

It is a circuit diagram which shows the resonance type converter apparatus of Example 1 of this invention. FIG. 3 is a diagram illustrating details of a control circuit provided in the resonant converter device according to the first embodiment. It is a conceptual diagram which converts the command value of the control circuit provided in the resonance type converter apparatus of Example 1. FIG. FIG. 3 is a schematic diagram of a resonant operation of the resonant converter device according to the first embodiment. FIG. 3 is a path diagram of resonance current of the resonant converter device according to the first embodiment. It is a figure which shows the system current waveform and resonance reactor current waveform of 1 commercial cycle of the resonant converter apparatus of Example 1. FIG. It is a figure which shows the detail of the control circuit provided in the resonance type converter apparatus of Example 2. FIG. It is a figure which shows a mode that a gate signal is produced | generated based on the falling carrier wave and the time of the zero crossing of a sine wave voltage in the control circuit of Example 2. FIG. It is a figure which shows the detail of the control circuit provided in the resonance type converter apparatus of Example 3. FIG. It is a figure which shows a mode that a gate signal is produced | generated based on the rising carrier wave and the zero crossing time of a sine wave voltage in the control circuit of Example 3. It is a figure which shows an example of the resonance type converter apparatus of the type which isolate | separates the conventional DC link voltage.

  Hereinafter, embodiments of a resonant converter device of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a resonant converter device according to a first embodiment of the present invention. In the resonant converter device shown in FIG. 1, a series circuit (first circuit) of a capacitor C5 (first capacitor) and a capacitor C6 (second capacitor) having the same capacity as the capacitor C5 is provided on the positive electrode side and the negative electrode side of the DC link. Series circuit) is connected, and a voltage ½ of the DC voltage VDC (DC link voltage VDC) is generated at a connection point B between the capacitors C5 and C6.

  The switches Q1 to Q6 are formed of a semiconductor switching element such as a MOSFET provided with a reflux diode. The switch Q1 (first switch) and the switch Q2 (second switch) are connected in series to form a full-bridge U arm, and both ends of the series circuit (second series circuit) are both ends of the first series circuit. It is connected to the. The switch Q3 (third switch) and the switch Q4 (fourth switch) are connected in series to form a full-bridge V-arm, and both ends of the series circuit (third series circuit) are both ends of the first series circuit. It is connected to the.

  A capacitor C1 (third capacitor) is connected between the drain and source of the switch Q1, and a capacitor C2 (fourth capacitor) is connected between the drain and source of the switch Q2. The switches Q1 to Q4 and the capacitors C1 and C2 constitute a single phase converter circuit.

  One end of the reactor L1 is connected to a connection point A between the switches Q1 and Q2, one end of the reactor L2 is connected to a connection point C between the switches Q3 and Q4, and a capacitor is connected to the other ends of the reactors L1 and L2. C7 is connected. A system (commercial power system) Vac is connected in parallel with the capacitor C7, and a power factor 1 current flows from the system Vac to the resonant converter device.

  The reactors L1 and L2 and the capacitor C7 constitute an LC circuit 15. The switch Q5 and the switch Q6 constitute a bidirectional switch (also referred to as an AC switch). The drain of the switch Q5 and the drain of the switch Q6 are connected, or the source of the switch Q5 and the source of the switch Q6 are connected to form a bidirectional switch. Reactor L3 (resonance reactor) is connected in series to switches Q5 and Q6.

  A series circuit (fourth series circuit) of the switches Q5 and Q6 and the reactor L3 is connected to a connection point B between the capacitors C5 and C6 and a connection point A between the switches Q1 and Q2. The control circuit 13 controls the current flowing from the system Vac connected to the capacitor C7 to a sine wave current having a power factor of 1 by switching the switches Q1 to Q4 with a gate signal.

  Next, a gate signal generation pattern (switching pattern) of a sinusoidal current having a power factor of 1 applied to the resonant converter device of the first embodiment will be described. First, a generally used generation method by sinusoidal modulation will be described.

  The voltage Vun and the voltage Vvn in FIG. 3B are potentials as viewed from a virtual midpoint n (not shown) of the capacitor C7. A subscript u of the voltage V indicates a U arm constituted by the switches Q1 and Q2, and a subscript v of the voltage V indicates a V arm constituted by the switches Q3 and Q4. The voltage Vuv can be expressed as Vuv = Vun−Vvn.

  The voltage Vvn has an operation amount that is 180 degrees out of phase with the voltage Vun. As a result, the gate signal waveforms generated by comparing the voltage Vun and the carrier (carrier wave signal) are the switches Q1, Q4, Q2, and Q2. Q3 is equivalent. When the carrier is considered as a sawtooth waveform, the relationship between the U arm operation amount Vr, the V arm operation amount Vs, and the carrier is as shown in FIG. At this time, the voltage across the capacitor C7, that is, the line voltage Vuv has twice the amplitude of the voltage Vun.

Next, a gate signal generation method applied to the resonant converter device shown in FIG. 1 will be described. When the system voltage is a positive voltage, the V-arm switch Q4 continues to be on while the system voltage is a positive voltage. When the operation amount at that time is Sv ^* , it can be expressed as Sv ^* =-1. Further, when the operation amount of the U arm is Su ^* , when −1 is added to the sine wave command Vr necessary for the line voltage, it can be expressed as Su ^* = Vr−1. Since the difference in the operation amount between the U arm and the V arm is reflected in the line voltage, Su ^* −Sv ^* = Vr. If Vr is a sine wave, the output is also a sine wave. Similarly, when the system voltage is a negative voltage, the V-arm switch Q3 is kept on during the period when the system voltage is a negative voltage. When the operation amount at that time is Sv ^* , it can be expressed as Sv ^* = 1. At this time, if 1 is added to the sine wave command Vr necessary for generating the line voltage, Su ^* = Vr + 1.

  When the above reference is generated, PWM comparison as shown in FIG. As a result, it is possible to generate a line voltage that is the same as a generation method using sinusoidal modulation that is generally used. The control circuit 13 continues to turn on the switch Q4 of the V arm while the system voltage is positive, and continues to turn on the switch Q3 while the system voltage is negative. Since the switching of the gate signals of the switches Q3 and Q4 is performed at the zero crossing of the system voltage or current, when switching is performed, almost zero current switching (soft switching) is performed, and no loss occurs.

  Further, since the switches Q3 and Q4 are switched at the system frequency and do not perform high-frequency switching at all, the switching loss is equal to or greater than that of the resonant converter device even if any external parts are not attached to the switches Q3 and Q4. There is a reduction effect.

  Next, the loss reduction between the switches Q1 and Q2 of the U arm will be described with reference to FIG. The control circuit 13 simultaneously turns on the switches Q5 and Q6 constituting the bidirectional switch during the dead time period of the switches Q1 and Q2 (a period in which both the switches Q1 and Q2 are off).

  When the system voltage is a positive voltage, the current path when the switches Q1 and Q2 are OFF is the system Vac → L1 → Q1 → C5 and C6 → Q4 → L2 → system Vac. Since a current flows through the freewheeling diode of the switch Q1, the drain-source voltage of the switch Q1 becomes zero. For this reason, when the switch Q2 is turned on, the DC voltage VDC is applied between the drain and source of the switch Q2, and a switching loss occurs.

  Therefore, in order to prevent a switching loss from occurring in the switch Q2, the drain-source voltage of the switch Q2 is set to zero during the dead time period immediately before the switching of the switch Q2.

  The switches Q5 and Q6 are simultaneously turned on during the dead time period of the switches Q1 and Q2 (time t1). At this time, since no current flows through the reactor L3, the switches Q5 and Q6 perform zero current switching.

  When the potential on the negative electrode side of the DC voltage VDC in FIG. 1 is used as a reference, the voltage at point B is VDC / 2, and the voltage at point A is VDC. Therefore, the voltage VAB applied to the reactor L3 is VDC / 2. The current flowing through reactor L3 increases with a slope of (VDC / 2) / L3.

  When the current in reactor L3 reaches the magnitude of the current in reactor L1, resonance occurs between reactor L3 and capacitors C1 and C2 (time t2). At this time, the charge of the capacitor C2 connected in parallel to the switch Q2 is released, and the charge flows into the capacitor C1 connected in parallel to the switch Q1.

  The resonance period at this time is π√ (L3 × 2 × C1). When the resonance is completed (time t3), the potential at the point A is zero. Therefore, by turning on the switch Q2 at that time, zero voltage switching (soft switching) of the switch Q2 can be realized.

  After the switch Q2 is turned on, the potential at the point A is zero, so the resonance current decreases with a slope of (VDC / 2) / L3. By turning off the switches Q5 and Q6 when the current of the reactor L3 reaches zero (time t4), the loss of the switches Q5 and Q6 can also be reduced.

  The path of the current when the switch Q2 is on is the system Vac → L1 → Q2 → Q4 → L2 → system Vac.

  In this state, when the switch Q2 is turned off, the charge of the capacitor C1 is discharged, and the charge of the capacitor C2 increases. At this time, since only the capacitor C2 is connected in parallel to the switch Q2, no switching loss occurs. Therefore, soft switching can be realized both in turn-on and turn-off of the switch Q2, switching loss is eliminated, and high efficiency can be realized.

  Next, the intermediate potential (point B potential) between the capacitor C5 and the capacitor C6 will be described. In order to perform an ideal resonance operation, this intermediate potential must be balanced with a voltage that is ½ of the DC voltage VDC.

  FIG. 5A and FIG. 5B are diagrams showing the flow of resonance current when the resonance operation is performed. For example, in FIG. 5A, when the voltage of the capacitor C5 is high and the voltage of the capacitor C6 is low, the charging current of the capacitor C5 is small and the discharging current of the capacitor C6 is also small.

  On the other hand, when the voltage of the capacitor C5 is low and the voltage of the capacitor C6 is high, the discharge current of the capacitor C6 is large and the charging current of the capacitor C5 is also large.

  In FIG. 5B, when the potential of the capacitor C5 is high and the potential of the capacitor C6 is low, the discharge current of the capacitor C5 is large and the charging current of the capacitor C6 is also large.

  On the other hand, when the voltage of the capacitor C5 is low and the voltage of the capacitor C6 is high, the discharge current of the capacitor C5 is small and the charging current of the capacitor C6 is also small.

  That is, a capacitor having a smaller capacitor voltage has a smaller discharge current and a larger charging current, and a capacitor having a higher capacitor voltage has a larger discharge current and a smaller charging current. For this reason, the voltage of the capacitor C1 and the voltage of the capacitor C2 approach each other as time passes, and after both balance, as shown in FIG. 6, the resonance current of the reactor L3 (resonance current waveform in FIG. 6). However, the half-cycle discharge current and the charge current of the commercial power system become the same amount and continue to balance.

  In this way, the point B of the capacitor C5 and the capacitor C6 configured to create a voltage that is 1/2 of the DC voltage VDC is controlled so that the outflow and the inflow are switched every half cycle of the commercial power system. The voltage balances in one cycle of the commercial power system. For this reason, an attached circuit or the like for balancing the intermediate potential is not required.

(Details of control circuit)
Next, details of the control circuit 13 shown in FIG. 2 will be described. The control circuit 13 has terminals T1 to T12, the terminal T1 is connected to the positive side of the DC link, the terminal T2 is connected to the connection point B between the capacitors C5 and C6, and the terminal T3 is the negative side of the DC link. It is connected to the. Terminal T4 is connected to the gate of switch Q1, terminal T5 is connected to the gate of switch Q2, terminal T6 is connected to the gate of switch Q3, and terminal T7 is connected to the gate of switch Q4. Terminal T8 is connected to a current sensor 16 that detects a current flowing through reactor L1 (an input current of the single-phase converter circuit). Terminal T9 is connected to the connection point between reactor L1 and capacitor C7, and terminal T10 is connected to the connection point between reactor L2 and capacitor C7. Terminal T11 is connected to the gate of switch Q5, and terminal T12 is connected to the gate of switch Q6.

  First, calculation of the resonance period will be described. Current sensor 16 detects a current flowing through reactor L1 and outputs the detected current to terminal T8. The arithmetic unit 24 multiplies the current detection value I input via the terminal T8 and the inductance value of the reactor L3 (denoted by L3), and outputs a multiplication output L3 × I to the divider 25.

The voltage detector 21 detects the voltage at the terminal T 2 and the terminal T 3, that is, the voltage V = VDC / 2 that is ½ of the DC voltage VDC, and outputs it to the divider 25. The divider 25 divides the multiplication output L3 × I from the calculation unit 24 by the voltage V from the voltage detector 21 to obtain the division output T ₁ = L3 × I / V, that is, the time T ₁ , and the adder 26 Output to.

The adder 26 adds the time (first period) T ₁ and the time (second period) T ₂ = π√ (L3 × 2C1) from the divider 25, and the adder 26 a adds the amplitude of the carrier signal to 2 Then, 2 [1-{(T ₁ + T ₂ ) / T}] is calculated, and the calculation result is output to the comparator 27a as a resonance switch command A as shown in FIG. The time T ₁ of the from the divider 25 is 2 / T times, it is output to the comparator 27b as the resonance switch command B as shown in FIG.

  The phase shift unit 29 phase-shifts the rising carrier signal (period T) from the rising carrier unit 30a by, for example, several μs and outputs the result to the comparators 27a and 27b. The frequency of the carrier signal is much higher than the system frequency, for example, 20 kHz. The phase shift unit 29 may be omitted.

  Here, at time t1 shown in FIG. 4, the value of the rising carrier signal from the rising carrier portion 30a phase-shifted by the phase shift unit 29 reaches the value of the resonance switch command A. For this reason, since the comparator 27a outputs the H level to the OR circuit 28, the switch Q5 and the switch Q6 are turned on. At this time, the switch Q1 and the switch Q2 are in an off state.

Then, the current flowing through reactor L3 rises with a slope of (VDC / 2) / L3 until it becomes the same amount as the current flowing through reactors L1 and L2. Time _{T 1} of the this time (time until t1~ time t2), the L3 × I / (VDC / 2 ) = L3 × I / V. After the current of the reactor L3 reaches the current flowing through the reactors L1 and L2, the resonance operation is performed. When the capacities of the capacitors C1 and C2 are represented by C1, the period is T ₂ = π√ (L3 × 2C1), that is, It is the time from time t2 to time t3.

  Here, 2C1 is set because the capacitor C1 and the capacitor C2 have the same capacity, and the capacitor C1 and the capacitor C2 are connected in parallel in terms of alternating current. Further, π represents a half cycle.

  The resonance between the reactor L3 and the capacitors C1 and C2 causes the drain-source voltage of the switch Q2 to become zero, so that the switch Q2 is turned on. Thereafter, the current of reactor L3 decreases with a slope of (VDC / 2) / L3 and becomes zero at time t4. At this time, the value of the rising carrier signal reaches the value of the resonance switch command B. For this reason, since both the comparators 27a and 27b output the L level to the OR circuit 28, the switches Q5 and Q6 are turned off.

  Next, the sine wave command generation circuit related to sine wave current control includes a voltage detector 31, a DC link voltage reference value, an adder 51, a PI unit 52, a multiplier 33, an adder 34, and a PI unit 35. The PWM generation circuit (first PWM generation circuit) includes a converter 37, a comparator 38a, an inverter 40a, and a dead time unit 41a. The on signal generation circuit (first on signal generation circuit) includes a converter 37, a comparator 38b, an inverter 40b, and a dead time unit 41b.

  The adder 51 obtains a deviation between the DC link voltage VDC between the terminals T1 and T3 detected by the voltage detector 21 and the DC link voltage reference value, and proportionally integrates this deviation output by the PI unit 52. Output to the multiplier 33.

  The voltage detector 31 detects the sine wave voltage (system voltage) of the system Vac from the voltage across the capacitor C7 via the terminals T9 and T10. Multiplier 33 multiplies the sine wave voltage from voltage detector 31 by the PI output from PI unit 52. The adder 34 obtains a deviation between the multiplication output (sine wave current command value) from the multiplier 33 and the sine wave current detected by the current sensor 16 and outputs the deviation to the PI unit 35. The PI unit 35 proportionally integrates the deviation output from the adder 34 and outputs the output to the conversion unit 37 as a sine wave command Vr.

  The zero cross switching discriminating unit 32 discriminates the zero cross between the sine wave voltage from the voltage detector 31 and the sine wave current detected by the current sensor 16, and the sine wave voltage and sine wave current are positive or negative with respect to the zero cross. A switching signal indicating this is output to the switching devices 23, 36 and 39.

The switch 36 selects the contact piece 36a when the sine wave voltage from the voltage detector 31 or the sine wave current detected by the current sensor 16 is positive, and the conversion unit 37 receives the sine wave from the PI unit 35. The command Vr is converted into an operation amount (first operation amount) Su ^ж = Vr−1 and an operation amount (third operation amount) Sv ^ж = −1. The switch 36 selects the contact piece 36b when the sine wave voltage from the voltage detector 31 or the sine wave current detected by the current sensor 16 is negative, and the conversion unit 37 receives the sine wave from the PI unit 35. The command Vr is converted into an operation amount (second operation amount) Su ^ж = Vr + 1 and an operation amount (fourth operation amount) Sv ^ж = 1.

  When the sine wave voltage from the voltage detector 31 or the sine wave current detected by the current sensor 16 is positive, the switch 39 selects the contact SW2 and outputs the falling carrier signal from the falling carrier part 30b. When the sine wave voltage output from the voltage detector 31 or the sine wave current detected by the current sensor 16 is negative, the contact SW1 is selected and the rising carrier signal (period T) from the rising carrier part 30a is selected. Output.

  The rising carrier section 30a outputs a rising carrier signal composed of a sawtooth wave as shown in the latter half of the period of FIG. 3C to the inverting input terminals of the comparators 38a and 38b via the contact piece SW1 of the switch 39. The falling carrier part 30b outputs a falling carrier signal composed of a sawtooth wave as shown in the first half cycle of FIG. 3C to the inverting input terminals of the comparators 38a and 38b via the contact SW2 of the switch 39. To do.

  When the sine wave voltage or sine wave current of the system Vac is positive, that is, when the contact piece 36a is selected and the contact piece SW2 is selected, the comparator 38a is shown in the first half cycle of FIG. As described above, when the first manipulated variable (Vr-1) is equal to or greater than the value of the falling carrier signal, the H level is output to the gate of the switch Q1 via the dead time unit 41a and turned on, and the H level is switched to the inverter 40a. And the L level is output to the gate of the switch Q2 via the dead time portion 41a and turned off. Further, the comparator 38a outputs the L level to the gate of the switch Q1 via the dead time portion 41a and turns it off when the first manipulated variable (Vr-1) is less than the value of the falling carrier signal, and the L level Is inverted by the inverter 40a and the H level is output to the gate of the switch Q2 via the dead time portion 41a to be turned on.

  Further, when the sine wave voltage or sine wave current of the system Vac is positive, that is, when the contact piece 36a is selected and the contact piece SW2 is selected, the comparator 38b is in the first half cycle of FIG. As shown in FIG. 3, since the third manipulated variable (−1) is less than or equal to the value of the rising carrier signal, the H level is output to the gate of the switch Q4 via the dead time portion 41b and turned on, and the H level is set to the inverter 40b. And the L level is output to the gate of the switch Q3 via the dead time portion 41b and turned off.

  When the sine wave voltage or sine wave current of the system Vac is negative, that is, when the contact piece 36b is selected and the contact piece SW1 is selected, the comparator 38a is shown in the second half cycle of FIG. Thus, when the second manipulated variable (Vr + 1) is equal to or greater than the value of the rising carrier signal, the H level is output to the gate of the switch Q1 via the dead time portion 41a and turned on, and the H level is inverted by the inverter 40a. The L level is output to the gate of the switch Q2 via the dead time portion 41a and turned on. When the second manipulated variable (Vr + 1) is less than the value of the rising carrier signal, the comparator 38a outputs the L level to the gate of the switch Q1 via the dead time unit 41a to turn it off, and the L level is inverted by the inverter 40a. Then, the H level is output to the gate of the switch Q2 via the dead time portion 41a and turned on.

  When the sine wave voltage or sine wave current of the system Vac is negative, that is, when the contact piece 36b is selected and the contact piece SW1 is selected, the comparator 38b is shown in the latter half cycle of FIG. Thus, when the fourth manipulated variable (+1) is equal to or greater than the value of the falling carrier signal, the H level is output to the gate of the switch Q3 via the dead time unit 41a and turned on, and the H level is inverted by the inverter 40b. Then, the L level is output to the gate of the switch Q4 via the dead time portion 41b and turned off.

  For this reason, the switch Q1 and the switch Q2 are alternately turned on / off by the PWM signal. The switches Q3 and Q4 are turned on / off alternately by 180 degrees in the system cycle by an on signal.

  By switching the command value conversion and the carrier wave signal by zero crossing, a sine wave output can be realized while performing soft switching.

  Thus, according to the resonant converter device of the first embodiment, the control circuit 13 alternately turns on the switch Q3 and the switch Q4 for a period of 180 degrees, so that no loss due to high frequency switching occurs. In addition, the control circuit 13 turns on the switches Q5 and Q6 constituting the bidirectional switch while the switch Q1 and the switch Q2 are off, and performs zero voltage switching by the resonance operation of the capacitor C1, the capacitor C2, and the reactor L3. As a result, no turn-on loss occurs. As a result, high efficiency can be realized.

  In addition, the control circuit 13 continues to turn on the switch Q4 during a period when the system voltage is positive, and continues to turn on the switch Q3 during a period when the system voltage is negative, so that the switching pattern of the switches Q3 and Q4 is changed. Based on this, since the switching patterns of the switch Q1 and the switch Q2 are generated so that the sine wave current flows through the system Vac, a sine wave current with a power factor of 1 can be passed through the system Vac.

  The comparators 27a and 27b are connected between the current flowing through the reactor L1, the inductance value of the reactor L3, the connection point B between the capacitors C5 and C6, and the connection point A between the first switch Q1 and the second switch Q2. The switches Q5 and Q6 are turned on based on the first period T1 based on the voltage of the first and second periods T2 based on the inductance value of the reactor L3 and the capacitance values of the capacitors C1 and C2, and the rising carrier signal (period T). Since / off is controlled, the switches Q5 and Q6 are turned on while the switch Q1 and the switch Q2 are off, and zero voltage switching can be performed by the resonant operation of the capacitor C1, the capacitor C2, and the reactor L3.

  Moreover, since no switch is provided on the DC line, the loss of the apparatus is reduced. Since a switch having a lower withstand voltage than a switch constituting a DC line or a full bridge can be used for the resonance circuit, when MOSFETs are used for the switches Q5 and Q6, the sum of the on-resistances of the switches Q5 and Q6 is a high withstand voltage switch. Therefore, the conduction loss can be reduced.

  In addition, the V-arm of the single-phase full-bridge configuration can reduce loss by control, and the remaining U-arm can realize a circuit using loss reduction means such as zero current switching and zero voltage switching with the minimum number of parts. .

  FIG. 7 is a diagram illustrating details of a control circuit provided in the resonant converter device according to the second embodiment. In the generation of the gate signal to the switches Q1 to Q4 by the control circuit 13 of the first embodiment, as shown in FIGS. 2 and 8A, the rising and falling carrier signals and the sine wave command Vr are converted to the system voltage. It was necessary to switch at zero crossing. That is, the rising carrier signal, the first manipulated variable (Vr-1) and the third manipulated variable (-1) are used during the period when the system voltage is positive, and the falling is used when the system voltage is negative. The carrier wave signal, the second manipulated variable (Vr + 1), and the fourth manipulated variable (+1) were used.

  Thereby, the gate signal Q1g to the switch Q1 shown in FIG. 8A is generated. A signal obtained by inverting the gate signal Q1g is a gate signal Q2g to the switch Q2 (not shown). Further, the gate signal Q4g to the switch Q4 is on (level 1) during the period when the system voltage is positive, and the gate signal Q3g to the switch Q3 is on (level) during the period when the system voltage is negative. Is 1).

On the other hand, in the second embodiment, as shown in FIG. 8B, the sine wave current flowing in the reactor L1 and the falling carrier signal and the sine wave voltage as the system voltage regardless of whether the system voltage is positive or negative. Is converted into a positive polarity absolute value voltage and the fifth manipulated variable (| Vr based on the positive polarity absolute value command (positive full wave rectified voltage) | Vr ₊ | and | Vr ₊ | ₊ | -1), that is, Su ^* and the third manipulated variable (-1), that is, Sv ^* are used.

  At the time of zero crossing of the system voltage, the terminals a and b of the changeover switches 45a and 45c corresponding to the upper switches Q1 and Q3 of each arm of the U arm and V arm are changed, and the changeover switch 45b corresponding to the lower switch is changed. By switching between the terminal a and the terminal b of 45d, the same gate signal as the gate signals Q1g to Q4g shown in FIG. 8A is generated. The changeover switches 45a to 45d will be described later.

Hereinafter, the gate signals Q1g to Q4g are based on the fifth manipulated variable (| Vr ₊ | -1) and the third manipulated variable (-1) based on the positive polarity absolute value command | Vr ₊ | shown in FIG. A configuration and operation to be generated will be described.

  The control circuit 13a of the second embodiment shown in FIG. 7 is different from the configuration of the control circuit 13 of the first embodiment shown in FIG. 2 in that the positive polarity absolute value conversion units (ABS units) 42 and 43, the zero cross switching determination unit 32a, The falling carrier part 30b and the switch 45 are different.

The ABS unit 42 converts the sine wave voltage detected by the voltage detector 31 into a positive absolute value voltage. The ABS unit 43 converts the sine wave current detected by the current sensor 16 into a positive absolute value current. The multiplier 33 multiplies the positive absolute value voltage from the ABS unit 42 and the output from the PI unit 52. The adder 34 obtains a deviation between the multiplication output from the multiplier 33 (positive polarity absolute value current command) and the positive polarity absolute value current from the ABS unit 43 and outputs the deviation to the PI unit 35. The PI unit 35 proportionally integrates the deviation output from the adder 34 and outputs the output as a positive polarity absolute value command | Vr ₊ |.

  The zero cross switching discriminating unit 32a discriminates the zero cross between the sine wave voltage from the voltage detector 31 and the sine wave current detected by the current sensor 16, and the sine wave voltage and sine wave current are positive or negative with respect to the zero cross. A switching signal indicating this is output to the switch 45. The falling carrier part 30b outputs a falling carrier signal composed of a sawtooth wave as shown in FIG. 8B to the inverting input terminals of the comparators 38a and 38b.

The comparator 38a sets the H level to the dead time portion when the fifth manipulated variable (| Vr ₊ | -1) based on the positive polarity absolute value command | Vr ₊ | It outputs to the output D via 41a, and outputs L level to the output E via the inverter 40a and the dead time part 41a. The comparator 38a sets the L level to the dead time portion when the fifth manipulated variable (| Vr ₊ | -1) based on the positive polarity absolute value command | Vr ₊ | It outputs to the output D via 41a, and outputs H level to the output E via the inverter 40a and the dead time part 41a. That is, as can be seen from FIG. 8B, PWM signals are output from the outputs D and E.

  Since the falling carrier signal is equal to or greater than the value of the third manipulated variable (−1), the comparator 38b outputs the L level to the output F through the dead time unit 41b, and outputs the H level to the inverter 40b and the dead time unit 41b. To output G.

  The switch 45 has switch 45a-45d. The terminals c of the changeover switches 45a to 45d are connected to the gates of the switches Q1 to Q4, and the terminals a and b are selected by a switching signal from the zero cross switching determination unit 32a.

  The changeover switch 45a selects the terminal a and gates the PWM signal from the output D of the dead time unit 41a during the period (time t0 to t1) in which the sine wave voltage is positive based on the switching signal from the zero cross switching discrimination unit 32a. The signal Q1g is output to the switch Q1, and during the period when the sine wave voltage is negative (time t1 to t2) based on the switching signal, a signal obtained by inverting the PWM signal from the output E of the dead time unit 41a is selected. The gate signal Q1g is output to the switch Q1. The gate signal waveform at this time is indicated by Q1g in FIG.

  The change-over switch 45b selects the terminal b during a period when the sine wave voltage is positive, and outputs a signal obtained by inverting the PWM signal from the output E of the dead time unit 41a to the switch Q2, and during a period when the sine wave voltage is negative. The terminal a is selected, and a PWM signal is output from the output D of the dead time unit 41a to the switch Q2.

  The changeover switch 45c selects the terminal a and outputs the L level (off signal) from the output F of the dead time unit 41b to the switch Q3 as the gate signal Q3g during the period in which the sine wave voltage is positive. In the negative period, the terminal b is selected and the H level (ON signal) is output from the output G of the dead time unit 41b to the switch Q3 as the gate signal Q3g.

  The changeover switch 45d selects the terminal b during the period when the sine wave voltage is positive, and outputs the H level from the output G of the dead time unit 41b to the switch Q4 as the gate signal Q4g, and during the period when the sine wave voltage is negative. The terminal a is selected, and the L level is output from the output F of the dead time unit 41b to the switch Q4 as the gate signal Q4g.

Thus, according to the control circuit 13a of the second embodiment, the falling carrier signal, the positive polarity absolute value command | Vr ₊ |, the fifth manipulated variable (| Vr ₊ | −1), and the third manipulated variable (−1 ) To switch the terminals a and b of the change-over switches 45a and 45c corresponding to the upper switches Q1 and Q3 of the U arm and V arm at the time of zero crossing of the system voltage, and switch them to the lower switches Q2 and Q4. Since the terminals a and b of the corresponding changeover switches 45b and 45d are switched, the same gate signals as the gate signals Q1g to Q4g shown in FIG. 8A can be generated. Further, only the falling carrier part 30b is required.

In the first embodiment, the first manipulated variable (Vr−1), the third manipulated variable (−1), the second manipulated variable (Vr + 1), and the fourth manipulated variable (+1) are obtained by the zero cross of the sine wave voltage. However, in the second embodiment, only the fifth manipulated variable (| Vr ₊ | -1) and the third manipulated variable (-1) are used, so that switching of the manipulated variable is unnecessary and the configuration is simple. become. Therefore, the resonant converter device can be reduced in size.

FIG. 9 is a diagram illustrating details of a control circuit provided in the resonant converter device according to the third embodiment. In the third embodiment, as shown in FIG. 10, the rising carrier signal, the sine wave voltage as the system voltage, and the sine wave current flowing through the reactor L1 are converted into a negative absolute voltage regardless of whether the system voltage is positive or negative. The negative polarity absolute value command (negative full wave rectified voltage) | Vr ₋ |, the sixth manipulated variable (| Vr ₋ | +1), and the fourth manipulated variable (+1) generated by the PI unit 35 are used. It was. Further, at the time of zero crossing of the system voltage, the terminals a and b of the changeover switches 45a and 45c corresponding to the upper switches Q1 and Q3 of the U arm and V arm are switched, and the switching corresponding to the lower switches Q2 and Q4. By switching the terminals a and b of the switches 45b and 45d, the same gate signals as the gate signals Q1g to Q4g shown in FIG. 8A are generated.

Hereinafter, the configuration and operation for generating the gate signals Q1g to Q4g based on the sixth manipulated variable (| Vr ₋ | +1) and the fourth manipulated variable (+1) based on the negative polarity absolute value command | Vr ₋ | shown in FIG. Will be explained.

The control circuit 13b of the third embodiment shown in FIG. 9, the configuration of the control circuit of the second embodiment shown in FIG. 7, the rising carrier portion 30a and the sixth operation amount (| Vr _- | +1) and the fourth operation amount (+1) is different from the connection between the divider 25 and the comparators 27a and 27b.

  The rising carrier section 30a outputs a rising carrier signal composed of a sawtooth wave as shown in FIG. 10 to the inverting input terminals of the comparators 38a and 38b.

When the sixth manipulated variable (| Vr ₋ | +1) based on the negative polarity absolute value command | Vr ₋ | from the PI unit 35 is equal to or higher than the value of the rising carrier signal, the comparator 38 a sets the H level to the dead time unit 41 a. To the output D, and the L level is output to the output E through the inverter 40a and the dead time unit 41a. When the sixth manipulated variable (| Vr ₋ | +1) based on the negative polarity absolute value command | Vr ₋ | from the PI unit 35 is less than the value of the rising carrier signal, the comparator 38 a sets the L level to the dead time unit 41 a. To the output D, and the H level is output to the output E through the inverter 40a and the dead time unit 41a. That is, as can be seen from FIG. 10, a PWM signal is output from the outputs D and E.

  Since the rising carrier signal is less than or equal to the value of the fourth manipulated variable (+1), the comparator 38b outputs the H level to the output F through the dead time unit 41b and the L level through the inverter 40b and the dead time unit 41b. To output G.

  The changeover switch 45a selects the terminal b and gates the PWM signal from the output E of the dead time part 41a during the period (time t0 to t1) in which the sine wave voltage is positive based on the switching signal from the zero cross switching judgment part 32a. The signal Q1g is output to the switch Q1, and during the period when the sine wave voltage is negative (time t1 to t2) based on the switching signal, a signal obtained by selecting the terminal a and inverting the PWM signal from the output D of the dead time unit 41a The gate signal Q1g is output to the switch Q1. The gate signal waveform at this time is indicated by Q1g in FIG.

  The changeover switch 45b selects the terminal a during the period when the sine wave voltage is positive, and outputs a signal obtained by inverting the PWM signal from the output D of the dead time unit 41a to the switch Q2, and during the period when the sine wave voltage is negative. The terminal b is selected, and a PWM signal is output from the output E of the dead time unit 41a to the switch Q2.

  The changeover switch 45c selects the terminal b during the period when the sine wave voltage is positive, and outputs the L level from the output G of the dead time unit 41b to the switch Q3 as the gate signal Q3g, and during the period when the sine wave voltage is negative. The terminal a is selected, and the H level is output from the output F of the dead time unit 41b to the switch Q3 as the gate signal Q3g.

  The changeover switch 45d selects the terminal a during the period when the sine wave voltage is positive, and outputs the H level from the output F of the dead time unit 41b to the switch Q4 as the gate signal Q4g, and during the period when the sine wave voltage is negative. The terminal b is selected and the L level from the output G of the dead time unit 41b is output to the switch Q4 as the gate signal Q4g.

In the case of the rising carrier signal, the connection between the output of the divider 25 and the inputs of the comparators 27a and 27b is different from that of the falling carrier signal (Example 2). That is, in the case of the rising carrier signal, as shown in FIG. 9, an adder 26 is provided between the output of the divider 25 and 2 / T on the input side of the comparator 27b. One cycle T ₁ and the second cycle T ₂ = π√ (L3 × 2C1) are added and output.

As described above, according to the control circuit 13b of the third embodiment, the rising carrier signal, the negative absolute value command | Vr ₋ |, the sixth operation amount (| Vr ₋ | +1), and the fourth operation amount (+1) are obtained. Used, when the system voltage is zero-crossed, the terminals a and b of the changeover switches 45a and 45c corresponding to the upper switches Q1 and Q3 of the U arm and V arm are switched, and the switching corresponding to the lower switches Q2 and Q4. Since the terminals a and b of the switches 45b and 45d are switched, the same gate signals as the gate signals Q1g to Q4g shown in FIG. 10 can be generated. Further, only the rising carrier part 30a is required.

In Example 3, the sixth operation amount (| Vr _- | +1), since use of only the fourth operation amount (+1), with the switching of the operation amount is not required, the configuration is simplified. Therefore, the resonant converter device can be reduced in size.

  In the first to third embodiments, MOSFETs are used as the switches Q1 to Q6. Instead, IGBTs (insulated gate bipolar transistors), transistors, and diodes connected in parallel thereto may be used.

  In the second and third embodiments, the ABS units 42 and 42a are provided on the input side of the multiplier 33 and the ABS units 43 and 43a are provided on the input side of the adder 34. Instead, the ABS unit is replaced with the PI. You may provide in the output side of the part 35. FIG.

  The present invention is applicable to a converter that converts alternating current into direct current.

C1 to C7 Capacitors L1 to L3 Reactors Q1 to Q6 Switch 13 Control circuit 15 LC circuit 16 Current sensor 21, 31 Voltage detector 23, 36, 39 Switch 25 Divider 26, 34, 51 Adders 27a, 27b, 38a, 38b Comparator
28 OR circuit 29 Phase shift unit 30a Rising carrier wave unit 30b Falling carrier wave unit 32 Zero crossing switching discriminating unit 33 Multiplier 35, 52 PI unit 37 Conversion unit
40a, 40b Inverter 41a, 41b Dead time section
50 DC voltage controller

Claims (9)

A first series circuit comprising a first capacitor and a second capacitor connected to the positive side and the negative side of the DC link;
A second series circuit comprising a first switch and a second switch connected to both ends of the first series circuit;
A third capacitor connected in parallel to the first switch;
A fourth capacitor connected in parallel to the second switch;
A third series circuit comprising a third switch and a fourth switch connected to both ends of the first series circuit;
An LC circuit connected to a commercial power system, a connection point between the first switch and the second switch, and a connection point between the third switch and the fourth switch, and including a reactor and a capacitor;
A fourth series circuit connected between a connection point of the first capacitor and the second capacitor and a connection point of the first switch and the second switch, and comprising a bidirectional switch and a resonance reactor; ,
PWM control is performed on the first switch and the second switch, and the third switch and the fourth switch are alternately turned on for a period of 180 degrees, and the first switch and the second switch are turned off. A control circuit that turns on the bidirectional switch and performs zero voltage switching by a resonance operation of the third capacitor, the fourth capacitor, and the resonance reactor;
A resonance type converter device comprising:   The control circuit continues to turn on the fourth switch when the sine wave voltage of the commercial power system is positive, and continues to turn on the third switch when the sine wave voltage of the commercial power system is negative. Based on the switching pattern of the third switch and the fourth switch, the switching of the first switch and the second switch so as to input a sine wave current having the same phase as the phase of the sine wave voltage of the commercial power system. 2. The resonant converter device according to claim 1, wherein a pattern is generated. The control circuit includes a voltage detector that detects a sine wave voltage of the commercial power system;
A zero-cross switching determination unit that determines a zero-cross of the sine wave voltage detected by the voltage detector and outputs a switching signal indicating whether the sine wave voltage is positive or negative with respect to the zero-cross,
A sine wave command generation circuit that outputs a sine wave command Vr for generating a sine wave current having the same phase as the phase of the sine wave voltage of the commercial power system;
A carrier wave section for generating a rising carrier wave signal and a falling carrier wave signal composed of a sawtooth wave;
Based on the switching signal, the first PWM signal is generated by comparing the first manipulated variable (Vr-1) based on the sine wave command Vr and the falling carrier signal during a period in which the sine wave voltage is positive. A signal output to the first switch and an inverted version of the first PWM signal is output to the second switch, and a second operation based on the sine wave command Vr is performed in a period in which the sine wave voltage is negative based on the switching signal. A first PWM generation circuit that generates a second PWM signal by comparing the amount (Vr + 1) and the rising carrier signal, outputs the second PWM signal to the first switch, and outputs a signal obtained by inverting the second PWM signal to the second switch When,
The resonant converter device according to claim 2, comprising: The control circuit generates a first ON signal by comparing a third manipulated variable (−1) and the falling carrier signal during a period in which the sine wave voltage is positive based on the switching signal, and generates the first ON signal. A signal that is output to four switches and that is obtained by inverting the first on signal is output to the third switch, and the fourth manipulated variable (+1) and the rising carrier wave are output during the period in which the sine wave voltage is negative based on the switching signal. A first on signal generation circuit that generates a second on signal by comparing the signal and outputs the second on signal to the third switch and outputs a signal obtained by inverting the second on signal to the fourth switch;
The resonant converter device according to claim 3, wherein: The control circuit includes a voltage detector that detects a sine wave voltage of the commercial power system;
A positive polarity absolute value converter that converts the sine wave voltage detected by the voltage detector into a positive polarity absolute value voltage;
A zero-cross switching determination unit that determines a zero-cross of the sine wave voltage detected by the voltage detector and outputs a switching signal indicating whether the sine wave voltage is positive or negative with respect to the zero-cross,
A positive polarity absolute value command generation circuit for outputting a positive polarity absolute value command | Vr ₊ | for generating an absolute value current having the same phase as the phase of the positive polarity absolute value voltage from the positive polarity absolute value conversion unit;
A falling carrier portion that generates a falling carrier signal consisting of a sawtooth wave;
A third PWM signal is generated by comparing a fifth operating amount (| Vr ₊ | −1) based on the positive polarity absolute value command | Vr ₊ | with the falling carrier signal, and the third PWM signal is inverted. A second PWM generation circuit for generating a signal;
Based on the switching signal, in a period in which the sine wave voltage is positive, the third PWM signal is output to the first switch, and a signal obtained by inverting the third PWM signal is output to the second switch. A switch that outputs the third PWM signal to the second switch and outputs the inverted signal of the third PWM signal to the first switch in a negative sine wave voltage period;
The resonant converter device according to claim 2, comprising: The control circuit generates a third on signal by comparing a third manipulated variable (−1) and the falling carrier signal, and generates a signal obtained by inverting the third on signal. Have a circuit,
The switch outputs a signal obtained by inverting the third on signal to the third switch and outputs the third on signal to the fourth switch during a period when the sine wave voltage is positive based on the switching signal. The third ON signal is output to the third switch and the inverted signal of the third ON signal is output to the fourth switch during the negative period of the sine wave voltage based on the switching signal. The resonant converter device according to claim 5. The control circuit includes a voltage detector that detects a sine wave voltage of the commercial power system;
A negative polarity absolute value converter that converts the sine wave voltage detected by the voltage detector into a negative polarity absolute value voltage;
A zero-cross switching determination unit that determines a zero-cross of the sine wave voltage detected by the voltage detector and outputs a switching signal indicating whether the sine wave voltage is positive or negative with respect to the zero-cross,
A negative polarity absolute value command generation circuit for outputting a negative polarity absolute value command | Vr ₋ | for generating an absolute value current having the same phase as the phase of the negative polarity absolute value voltage from the negative polarity absolute value conversion unit;
A rising carrier part for generating a rising carrier signal consisting of a sawtooth wave;
PWM inversion in which a fourth PWM signal is generated by inverting the fourth PWM signal by comparing the rising carrier signal with a sixth manipulated variable (| Vr ₋ | +1) based on the negative polarity absolute value command | Vr ₋ | A third PWM generation circuit for generating a signal;
Based on the switching signal, in a period in which the sine wave voltage is positive, the fourth PWM signal is output to the second switch, and a signal obtained by inverting the fourth PWM signal is output to the first switch. A switch that outputs the fourth PWM signal to the first switch and outputs the inverted signal of the fourth PWM signal to the second switch in a negative sine wave voltage period;
The resonant converter device according to claim 2, comprising: The control circuit generates a fourth on signal by comparing a fourth manipulated variable (+1) and the rising carrier signal, and generates a third on signal generation circuit that generates a signal obtained by inverting the fourth on signal. Have
The switch outputs a signal obtained by inverting the fourth on signal to the third switch and outputs the fourth on signal to the fourth switch during a period when the sine wave voltage is positive based on the switching signal. And, when the sine wave voltage is negative based on the switching signal, the fourth on signal is output to the third switch and the inverted signal of the fourth on signal is output to the fourth switch. The resonant converter device according to claim 7.   The control circuit includes a current flowing through a reactor of the LC circuit, an inductance value of the resonance reactor, a connection point between the first capacitor and the second capacitor, and a connection between the first switch and the second switch. A first period based on a voltage between points, a second period based on an inductance value of the resonance reactor and capacitance values of the third capacitor and the fourth capacitor, and the rising carrier signal or the falling carrier wave 9. The resonant converter device according to claim 3, further comprising a bidirectional switch control circuit that controls on / off of the bidirectional switch based on a signal.

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