JP6366558B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply device that converts an input voltage into a desired DC voltage and supplies power to a load, and more particularly to a switching power supply device that includes a snubber circuit.

  Conventionally, as disclosed in Patent Document 1, a switching power supply device that controls an output voltage by turning on and off a main switching element (main oscillation element), which includes a synchronous rectifying element, an output diode (addition diode), and There was a switching power supply device in which a snubber circuit (rectification auxiliary circuit) composed of a series circuit of an auxiliary capacitor and an auxiliary switching element (auxiliary switching element) was connected in parallel. For example, an N-channel MOS FET is used as the auxiliary switching element. According to this switching power supply device, cross loss, switching noise, etc. (electromagnetic wave noise, voltage surge, ringing, etc.) caused by the recovery operation of the output diode by turning on / off the auxiliary switching element at a predetermined timing The effect of reducing the switching noise generated when the main switching element turns off, the ZVS (zero volt switching) when the main switching element turns on, and the cross loss and switching noise of the main switching element The effect that it can reduce etc. is acquired.

JP 2009-273230 A

  The snubber circuit included in the switching power supply device of Patent Document 1 appropriately controls the on / off sequence of the auxiliary switching element with respect to the on / off timing of the main switching element, and precisely controls the delicate operation delay. It is important to do. However, Patent Document 1 does not disclose a specific circuit configuration for the drive circuit of the auxiliary switching element.

  There are various configurations of the power conversion circuit, and the auxiliary switching element and the main switching element are often separated into a high side and a low side. In this case, since each switching element is driven by two signals that are insulated from each other, it is common to use a drive transformer for signal isolation, a two-output driver IC for high-side and low-side drive, or the like. is there. Therefore, this type of snubber circuit has a problem that it is difficult to configure it simply and inexpensively.

  An object of the present invention is to provide a switching power supply device that has a snubber circuit with a simple configuration and can accurately drive an auxiliary switching element of the snubber circuit in an appropriate sequence.

The present invention relates to a main switching element connected in series to an input power supply to intermittently input voltage, and excited by the input power supply while the main switching element is on and the excitation energy stored during the on period is stored in the main switching element An output inductor that discharges to the output during the off period, and an output diode that conducts during the off period of the main switching element and serves as a current path when the excitation energy is discharged to the output, and is connected to the output A switching power supply device comprising: a power conversion circuit that supplies power to the loaded load; and a control circuit that controls an on time and an off time of the main switching element,
The power conversion circuit is provided with a snubber circuit. The snubber circuit has an auxiliary capacitor having one end connected to the anode of the output diode, a source connected to the other end of the auxiliary capacitor, and a cathode of the output diode. Auxiliary switching element comprising an N-channel MOS type FET connected to the drain, and a DC bias circuit for biasing in a positive direction with a predetermined DC voltage between the gate of the auxiliary switching element and the anode of the output diode. The control circuit performs a critical mode control in which the main switch element is quickly reversed from off to on after the excitation energy of the output inductor is released through the output diode.
After the main switching element is turned off, the auxiliary switching element has its gate-source voltage increased due to a decrease in the voltage of the auxiliary capacitor, and the gate-source voltage exceeds the ON threshold. Inverted from off to on, and then, before the main switching element is turned on, the voltage of the auxiliary capacitor rises to reduce its own gate-source voltage, and the gate-source voltage reaches the on threshold. This is a switching power supply that reverses from on to off at a lower timing.

  Between the output of the DC bias circuit and the gate of the auxiliary switching element, a parallel circuit of an extraction diode and a gate resistor having a cathode arranged on the DC bias circuit side is inserted, and the gate resistor is connected to the auxiliary resistor. It is preferable that the timing at which the auxiliary switching element is inverted from OFF to ON is delayed by limiting the current flowing into the gate of the switching element.

  The DC bias circuit includes a charging resistor having one end connected to the drain of the auxiliary switching element, a smoothing capacitor connected between the other end of the charging resistor and the anode of the output diode, and other than the charging resistor. A Zener diode having a cathode connected to the end and an anode connected to the anode of the output diode, the predetermined DC voltage defined by the Zener voltage of the Zener diode being connected to the charging resistor and the smoothing capacitor It can be configured to output from a point. In this case, it is preferable that a discharge blocking diode for blocking a discharge current from the smoothing capacitor is inserted at a position in series with the charging resistor.

  Alternatively, the DC bias circuit includes a coupling capacitor having one end connected to the drain of the auxiliary switching element, and a Zener having a cathode connected to the other end of the coupling capacitor and an anode connected to the anode of the output diode. A diode, a backflow prevention diode having an anode connected to the cathode of the Zener diode, and a smoothing capacitor connected between the cathode of the backflow prevention diode and the anode of the output diode, the Zener voltage of the Zener diode The predetermined DC voltage defined by the above can be output from a connection point between the backflow prevention diode and the smoothing capacitor.

The present invention also provides a main switching element connected in series to an input power supply and intermittently receiving an input voltage; and the main switching element is excited by the input power supply while the main switching element is on and the excitation energy stored during the on period is stored in the main power supply. An output inductor that emits to the output during a period when the switching element is off, and an output diode that is conductive during the period when the main switching element is off and serves as a current path when the excitation energy is released to the output. A switching power supply comprising: a power conversion circuit that supplies power to a load connected to the power supply; and a control circuit that controls an on time and an off time of the main switching element,
The power conversion circuit is provided with a snubber circuit. The snubber circuit has an auxiliary capacitor having one end connected to the cathode of the output diode, a source connected to the other end of the auxiliary capacitor, and an anode of the output diode. Auxiliary switching element composed of a P-channel MOS FET with a drain connected thereto, and a DC bias circuit for negatively biasing between the gate of the auxiliary switching element and the cathode of the output diode with a predetermined DC voltage The control circuit performs a critical mode control in which the main switch element is quickly reversed from off to on after the excitation energy of the output inductor is released through the output diode.
After the main switching element is turned off, the auxiliary switching element has its gate-source voltage increased due to a decrease in the voltage of the auxiliary capacitor, and the gate-source voltage exceeds the ON threshold. Inverted from off to on, and then, before the main switching element is turned on, the voltage of the auxiliary capacitor rises to reduce its own gate-source voltage, and the gate-source voltage reaches the on threshold. This is a switching power supply that reverses from on to off at a lower timing.

  Between the output of the DC bias circuit and the gate of the auxiliary switching element, a parallel circuit of an extraction diode and a gate resistor, the anode of which is arranged on the DC bias circuit side, is inserted, and the gate resistance is the auxiliary resistor. It is preferable that the timing at which the auxiliary switching element inverts from off to on is delayed by limiting the current flowing out from the gate of the switching element.

  The DC bias circuit includes a charging resistor having one end connected to the drain of the auxiliary switching element, a smoothing capacitor connected between the other end of the charging resistor and the cathode of the output diode, and other than the charging resistor. A Zener diode having an anode connected to the end and a cathode connected to the cathode of the output diode, and connecting the predetermined DC voltage defined by the Zener voltage of the Zener diode to the charging resistor and the smoothing capacitor. It can be configured to output from a point. In this case, it is preferable that a discharge blocking diode for blocking a discharge current from the smoothing capacitor is inserted at a position in series with the charging resistor.

  Alternatively, the DC bias circuit includes a coupling capacitor having one end connected to the drain of the auxiliary switching element, and a Zener having an anode connected to the other end of the coupling capacitor and a cathode connected to the cathode of the output diode. A diode, a backflow prevention diode having a cathode connected to the anode of the Zener diode, and a smoothing capacitor connected between the anode of the backflow prevention diode and the cathode of the output diode, the Zener voltage of the Zener diode The predetermined DC voltage defined by the above can be output from a connection point between the backflow prevention diode and the smoothing capacitor.

  The control circuit is configured to invert the main switching element from off to on at a timing when the voltage across the main switching element is reduced to a predetermined voltage after the excitation energy of the output inductor is released through the output diode. It is preferable to make it. Further, an additional capacitor may be connected between the drain and source of the auxiliary switching element.

  The power conversion circuit supplies power from the input power source to the load while the main switching element is on, and excites the output inductor by the input power source, and outputs the output when the main switching element is off. The excitation energy stored in the inductor is discharged to the output to supply power to the load. Alternatively, the power conversion circuit excites the output inductor by the input power supply without supplying power from the input power supply to the output while the main switching element is on, and the main switching element is off. The excitation energy stored in the output inductor is discharged to an output to supply power to the load.

  Since the switching power supply device of the present invention operates in a so-called critical mode, cross loss, switching noise, etc. (electromagnetic wave noise, voltage surge, ringing, etc.) due to the recovery operation of the output diode hardly occur. In addition, since a unique snubber circuit is provided, switching noise and the like when the main switching element is turned off can be reduced. Further, ZVS of the main switching element can be easily realized, and cross loss, switching noise, and the like when the main switching element is turned on can be greatly reduced. Furthermore, ZVS of the auxiliary switching element can be easily realized, and cross loss, switching noise, and the like when the auxiliary switching element is turned on can be suppressed to be small.

  Since the snubber circuit has a very simple configuration, an increase in the mounting space and cost of the snubber circuit can be minimized. Further, the noise filter and the power semiconductor radiator can be made small by the effects of low noise and low loss described above, so that the entire power supply device can be greatly reduced in size and cost.

  In addition, since this snubber circuit can be used without problems even when the ground potential of the auxiliary switching element and the main switching element is different, a non-insulated converter such as a step-up chopper, a step-down chopper, an isolated converter such as a flyback converter, etc. The present invention can be applied to power conversion circuits having various configurations.

1 is a circuit diagram showing a first embodiment of a switching power supply device of the present invention. FIG. 2 is a circuit diagram (a) showing an internal configuration of the DC bias circuit of FIG. 1 and a diagram (b) showing signs of voltages and currents of respective parts. It is a time chart which shows operation | movement of the switching power supply device of 1st embodiment. 4 is an equivalent circuit (a) showing an operation state in a period t1 in FIG. 3, and an equivalent circuit (b) showing an operation state in a period t2. 4 is an equivalent circuit (a) showing an operation state in a period t3 in FIG. 3, and an equivalent circuit (b) showing an operation state in a period t4. 4 is an equivalent circuit (a) showing an operation state in a period t5 in FIG. 3, and an equivalent circuit (b) showing an operation state in a period t6. 4 is an equivalent circuit (a) showing an operation state in a period t7 in FIG. 3, and an equivalent circuit (b) showing an operation state in a period t8. FIG. 4 is an equivalent circuit illustrating an operation state in a period t9 in FIG. FIG. 5 is a circuit diagram showing a modification of the snubber circuit of FIG. 2. FIG. 5 is a circuit diagram (a) showing a first modification of the internal configuration of the DC bias circuit of FIG. 2 and a circuit diagram (b) showing a second modification. FIG. 7 is a circuit diagram (a) showing a third modification of the internal configuration of the DC bias circuit of FIG. 2 and a circuit diagram (b) showing a fourth modification. It is a circuit diagram which shows 2nd embodiment of the switching power supply device of this invention. It is a circuit diagram which shows 3rd embodiment of the switching power supply device of this invention. It is a circuit diagram which shows 4th embodiment of the switching power supply device of this invention. It is a circuit diagram which shows 5th embodiment of the switching power supply device of this invention. It is the circuit diagram (a) which shows 6th embodiment of the switching power supply device of this invention, and the circuit diagram (b) which shows the internal structure of a DC bias circuit. It is a circuit diagram which shows the modification of the snubber circuit of FIG.16 (b). FIG. 17A is a circuit diagram illustrating a first modification of the internal configuration of the DC bias circuit in FIG. 16B, and FIG. 17B is a circuit diagram illustrating a second modification. FIG. 17 is a circuit diagram showing a third modification of the internal configuration of the DC bias circuit of FIG. It is a circuit diagram which shows the structure of the other switching power supply device.

  Hereinafter, a switching power supply device according to a first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the switching power supply device 10 according to the first embodiment includes a boost chopper type power conversion circuit 14 having a snubber circuit 12 and a control circuit 16 that controls the operation of the power conversion circuit 14. ing.

  The power conversion circuit 14 includes a main switching element 20 that is connected in series to the input power source 18 and intermittently connects the input voltage Vi. The main switching element 20 is, for example, an N-channel MOS FET, and has a source connected to the negative side of the input power supply 18 and a drain connected to the positive side of the input power supply 18 via the output inductor 22. Since it is a MOS type FET, it is turned on when the gate-source voltage is at a high level and turned off when it is at a low level. An anode of the output diode 24 is connected to a connection point between the output inductor 22 and the main switching element 20, and an output capacitor 26 is connected between the cathode of the output diode 24 and the source of the main switching element 20. Both ends of the output capacitor 26 are outputs of the power conversion circuit 14, and the power conversion circuit 14 supplies an output voltage Vo and an output current Io to a load 28 connected to the output.

  The control circuit 16 is a circuit that generates a driving pulse for the main switching element 20, and determines, for example, a high level time (on time) and a low level time (off time) so that the output voltage Vo approaches a target value, The generated drive pulse is output between the gate and source of the main switching element 20.

  The output inductor 22 is excited by the input power source 18 when the main switching element 20 is on, and the main switching element 20 releases the excitation energy stored during the on period to the output during the off period. The output diode 24 becomes conductive while the main switching element 20 is off, and serves as a current path when excitation energy is released to the output. The control circuit 16 controls the critical mode in which the main switch element 20 is quickly reversed from off to on after all the excitation energy of the output inductor 22 is released through the output diode 24. Here, the “period in which the main switching element 20 is on” refers to a period in which a parasitic diode 20b described later is in conduction and a period in which the FET 20a is on (periods t8, t9, t1 in FIG. 3). .

  The snubber circuit 12 includes an auxiliary capacitor 30, an auxiliary switching element 32, and a DC bias circuit 34. The auxiliary capacitor 30 has one end connected to the anode of the output diode 24. The auxiliary switching element 32 is an N-channel MOS FET, and has a source connected to the other end of the auxiliary capacitor 30 and a drain connected to the cathode of the output diode 24. The DC bias circuit 34 is a circuit that biases the gate of the auxiliary switching element 32 and the anode of the output diode 24 in the positive direction with a predetermined DC voltage.

  As shown in FIG. 2A, the internal configuration of the DC bias circuit 34 includes a charging resistor 36 having one end connected to the drain of the auxiliary switching element 32, the other end of the charging resistor 36, and the anode of the output diode 24. A smoothing capacitor 38 connected between them and a Zener diode 40 (Zener voltage Vz40) having a cathode connected to the other end of the charging resistor 36 and an anode connected to the anode of the output diode 24 are constituted. The DC bias circuit 34 performs an operation of substantially averaging the pulse voltage across the output diode 24 with the charging resistor 36 and the smoothing capacitor 38, and applies a substantially DC voltage V38 defined by the Zener voltage Vz 40 across the smoothing capacitor 38. The voltage V38 is biased between the gate of the auxiliary switching element 32 and the anode of the output diode 24.

  Next, the operation of the switching power supply device 10 will be described based on the time chart of FIG. The current I22, voltage Vds20, and current Id20 shown in FIG. 3 are respectively applied to the current flowing through the output inductor 22, the voltage generated between the drain and source of the main switching element 20, and the drain of the main switching element 20 as shown in FIG. It is a flowing current. The voltage V38, voltage V30, voltage Vgs32, voltage Vds32, and current Id32 shown in FIG. 3 are respectively the voltage across the smoothing capacitor 38, the voltage across the auxiliary capacitor 30, the voltage across the auxiliary switching element 32, as shown in FIG. The voltage generated between the gate and the source, the voltage generated between the drain and the source of the auxiliary switching element 32, and the current flowing through the drain of the auxiliary switching element 32.

  FIG. 3 shows one cycle of the switching operation divided into periods t1 to t9, and schematically shows the waveforms in each period. Here, in order to make the waveforms easier to see, the time axes of periods t2, t3, and t4 are slightly changed. Enlarged and drawn. In FIG. 3, the total time of the periods t2, t3, and t4 is drawn at about ½ of the period t1, but the actual time is about 1/10 of the period t1.

  Hereinafter, each operation in the periods t1 to t9 will be described in order using the equivalent circuits in FIGS. In the equivalent circuit, the auxiliary switching element 32, which is an N-channel MOS FET, includes an FET 32a (on / off state is indicated by a switch), a drain-source parasitic diode 32b, and a drain-source parasitic. The capacitor 32c is shown separately. The current Id32 is a waveform obtained by synthesizing currents flowing through the FET 32a, the parasitic diode 32b, and the parasitic capacitor 32c. Similarly, the main switching element 20 which is an N-channel MOS FET includes an FET 20a (on / off state is indicated by a switch), a drain-source parasitic diode 20b, and a drain-source parasitic capacitor 20c. It is shown separately. The current Id20 is a waveform obtained by synthesizing currents flowing through the FET 20a, the parasitic diode 20b, and the parasitic capacitor 20c.

  For ease of explanation, the voltage drop when a forward current flows through the diode element in each part is ignored because it is sufficiently small. The gate threshold voltage at which the auxiliary switching element 32 is switched on / off is Vth32. Further, it is assumed that the capacity of the auxiliary capacitor 30 is sufficiently larger than the parasitic capacitors 20 c and 32 c and sufficiently smaller than the output capacitor 26.

  In the period t1, the FET 20a of the main switching element 20 is turned on as shown in FIGS. The current I22 of the output inductor 22 increases to the right. The current I22 flows through the path of the input power source 18, the output inductor 22, and the FET 20a, and the output inductor 22 is excited. Since the FET 20a is turned on and the voltage Vds20 is almost zero, the output diode 24 is turned off by applying the reverse voltage Vo to both ends. The smoothing capacitor 38 of the DC bias circuit 34 is charged by the charging resistor 36, and the voltage V38 is the Zener voltage Vz40. The value of the voltage V30 of the auxiliary capacitor 30 is V30p. The voltage value V30p is a peak value of the voltage V30, and is determined by an operation in a period t7 described later. During the period t1, the relationship of “Vgs32 = V38−V30 = Vz40−V30p <Vth32” is established, and the FET 32a of the auxiliary switching element 32 is off. The output current Io flowing through the load 28 is supplied from the output capacitor 26. The period t1 ends when the FET 20a of the main switching element 20 turns off under the control of the control circuit 16.

  In the period t2, as shown in FIGS. 3 and 4B, the output inductor 22 performs an operation of continuously flowing the current I22 at the end of the period t1, and the current I22 is output from the output inductor 22, The current is diverted to the path of the capacitor 20c and the input power supply 18 and the path of the output inductor 22, the auxiliary capacitor 30, the parasitic capacitor 32c, the output capacitor 26, and the input power supply 18. The current flowing in the former path is a positive current appearing in the waveform of the current Id20, whereby the parasitic capacitor 20c is charged and the voltage Vds20 rises sharply. The current flowing in the latter path is a negative current appearing in the waveform of the current Id32, whereby the parasitic capacitor 32c is discharged and the voltage Vds32 is sharply reduced, and the auxiliary capacitor 30 is also slightly discharged and the voltage V30 is gradually reduced. descend.

  As the voltage Vds20 of the main switching element 20 increases, the current for charging the smoothing capacitor 38 through the charging resistor 36 gradually decreases, and the DC bias circuit 34 has the ability to hold the voltage V38 of the smoothing capacitor 38 at the Zener voltage Vz40. Becomes weaker. Further, since a parasitic capacitor (not shown) exists between the gate and the source of the auxiliary switching element 32, the smoothing capacitor 38 is discharged when the voltage V30 of the auxiliary capacitor 30 decreases. Therefore, the voltage V38 cannot hold the Zener voltage Vz40, and slightly decreases in the middle. However, during the period t2, the relationship “Vgs32 = V38−V30 <Vth32” is established, and the FET 32a of the auxiliary switching element 32 is off. The period t2 ends when the voltage Vds32 drops to zero volts and the parasitic diode 32b of the auxiliary switching element 32 starts to conduct. At this time, the voltage Vds20 increases to a value obtained by subtracting the voltage V30 of the auxiliary capacitor 30 from the output voltage Vo.

  In the period t3, as shown in FIG. 3 and FIG. 5A, the output inductor 22 performs an operation to continuously flow the current I22 at the end of the period t2, and the current I22 The current is diverted to the path of the capacitor 20c and the input power supply 18 and the path of the output inductor 22, the auxiliary capacitor 30, the parasitic diode 32b, the output capacitor 26, and the input power supply 18. Although the current flowing in the latter path is a negative current appearing in the waveform of the current Id32 as in the period t2, it flows in the parasitic diode 32b having a low impedance instead of the parasitic capacitor 32c. Flows in this path, the discharge of the auxiliary capacitor 30 is accelerated, and the rate of decrease of the voltage V30 is increased. The current flowing in the former path is a positive current appearing in the waveform of the current Id20 as in the period t2, and the amount of current is smaller than that in the period t2, but the parasitic capacitor 20c is gradually charged and the voltage Vds20 is gradually reduced. To rise.

  In addition, when the period t3 is entered, a current flows in the charging resistor 36 in the direction in which the smoothing capacitor 38 is discharged. Further, since a parasitic capacitance exists between the gate and the source of the auxiliary switching element 32, the smoothing capacitor 38 is also discharged as the voltage V30 of the auxiliary capacitor 30 is reduced, and the voltage V38 is slightly reduced. The period t3 ends when “Vgs32 = V38−V30 ≧ Vth32” due to a significant decrease in the voltage V30, and the FET 32a of the auxiliary switching element 32 turns on.

  The period t4 operates as shown in FIGS. 3 and 5B. The difference from the period t3 is that the current flowing in the parasitic diode 32b of the auxiliary switching element 32 flows to the FET 32a. Since both the parasitic diode 32b and the FET 32a are elements having low impedance, There will be no major changes.

  What is characteristic here is that the FET 32a reverses from off to on when the voltage Vds32 is approximately zero volts, and the effect of suppressing the cross loss of the auxiliary switching element 32 by so-called ZVS is obtained. Further, when the snubber circuit 12 is not provided, a large surge voltage is generated in the voltage Vds20. Since the auxiliary capacitor 30 absorbs the energy of the surge voltage during the periods t3 and t4, almost no surge voltage is generated in the voltage Vds20. The period t4 ends when the voltage Vds20 of the main switching element reaches the output voltage Vo and the output diode 24 starts to conduct. At this time, the voltage V30 has dropped to almost zero volts, but the voltage V38 is held at a predetermined voltage.

  The period t5 is a period in which the output inductor 22 releases the excitation energy toward the output, and as shown in FIGS. 3 and 6A, the current I22 that discharges the excitation energy decreases to the output inductor 22. , The output diode 24, the output capacitor 26 and the load 28, and the input power supply 18. Therefore, the output current Io flowing through the load 28 is supplied from the output inductor 22 and the output capacitor 26. A small current continues to flow through the charging resistor 36 in the direction of discharging the smoothing capacitor 38, but the voltage V38 does not decrease so much and is held at a predetermined value. The period t5 ends when the current I22 of the output inductor 22 reaches zero ampere and the output diode 24 becomes non-conductive.

  In the period t6, as shown in FIGS. 3 and 6B, the path of the output inductor 22, the input power supply 18, the output capacitor 26, the FET 32a, the auxiliary capacitor 30, the output inductor 22, the input power supply 18, and the parasitic capacitor 20c are connected. Current flows through the path that passes. The negative current appearing in the waveform of the current I22 of the output inductor 22 is a combination of the currents divided in the former path and the latter path.

  The current flowing through the former path is a positive current appearing in the waveform of the current Id32, and the auxiliary capacitor 30 is charged by this current, and the voltage V30 rises. The current flowing through the latter path is a negative current appearing in the waveform of the current Id20, and is a current that discharges the parasitic capacitor 20c. Since the capacitance of the parasitic capacitor 20c is sufficiently smaller than that of the auxiliary capacitor 30, the amount of current is It is very small and the voltage Vds20 gradually decreases slightly. Further, as the voltage Vds20 decreases, a current in the direction of charging the smoothing capacitor 38 flows through the charging resistor 36, and the voltage V38 slightly increases.

  What is characteristic here is that a reverse voltage is applied to the output diode 24 when the forward current of the output diode 24 becomes zero amperes by so-called critical mode control, and the voltage Vds20 is gradually reduced, so that the output The reverse voltage of the diode 24 does not increase rapidly. By these characteristic operations, the recovery operation of the output diode 24 hardly occurs, so that switching noise and cross loss due to the recovery operation are greatly reduced. The period t6 ends when “Vgs32 = V38−V30 ≦ Vth32” due to a significant increase in the voltage V30, and the FET 32a of the auxiliary switching element 32 turns off.

  In the period t7, as shown in FIGS. 3 and 7A, the output inductor 22 performs an operation of continuously flowing the current I22 at the end of the period t6. The current is diverted to the path of the power supply 18, the output capacitor 26, the parasitic capacitor 32c, and the auxiliary capacitor 30, and the path of the output inductor 22, the input power supply 18, and the parasitic capacitor 20c. The current flowing in the former path is a negative current appearing in the waveform of the current Id32 as in the period t6. However, since the current flows in the parasitic capacitor 32c having a high impedance instead of the FET 32a, the latter of the currents I22. The amount of current flowing through the path increases, the charging of the auxiliary capacitor 30 becomes gradual, and the rise of the voltage V30 becomes gradual. The current flowing in the latter path is a positive current appearing in the waveform of the current Id20, as in the period t6, and the amount of current is larger than that in the period t6, the parasitic capacitor 20c is charged, and the voltage Vds20 decreases sharply. .

  When the voltage Vds20 decreases, a sufficient current flows through the smoothing capacitor 38 and the Zener diode 40 through the charging resistor 36, and the voltage V38 is held at the Zener voltage Vz40. Period t7 ends when voltage Vds20 drops to zero volts and parasitic diode 20b of main switching element 20 begins to conduct. The parasitic diode 20b starts to conduct at the timing when all of the excitation energy stored in the output inductor 22 is released during the period (period t8, t9, t1) when the main switching element 20 is on. Further, the voltage V30 of the auxiliary capacitor 30 has increased to V30p, and the relationship of “Vgs32 = V38−V30 = Vz40−V30p <Vth32” is established.

  During the period t8, the main switching element 20 is turned on by the conduction of the parasitic diode 20b, and the current I22 passes through the output inductor 22, the input power supply 18, and the parasitic diode 20b as shown in FIGS. 3 and 7B. Flowing through the path, the output inductor 22 is excited. Since this path has very low impedance, the current I22 is not shunted to the path of the output inductor 22, the input power supply 18, the output capacitor 26, the parasitic capacitor 32c, and the auxiliary capacitor 30 in the period t7, and the voltage V30 of the auxiliary capacitor 20 Is held at V30p at the end of period t7. The voltage V38 of the smoothing capacitor 38 is held at the Zener voltage Vz40 as in the period t7. The period t8 ends when the FET 20a of the main switching element 20 turns on under the control of the control circuit 16.

  The period t9 operates as shown in FIGS. The difference from the period t8 is that the current that has been flowing through the parasitic diode 20b flows into the FET 20a. However, since both the parasitic diode 20b and the FET 20a have low impedance, there is no significant change in the waveform of each part. . Further, when the period t9 and the period t1 are compared, there is a difference in whether the waveforms of the currents I22 and Id20 are negative or positive, but the substantial operation in the period t9 is the same as that in the period t1.

  What is characteristic here is that the FET 20a reverses from off to on when the voltage Vds20 is almost zero volts, and the effect of suppressing the cross loss of the main switching element 20 by so-called ZVS is obtained. The period t9 ends at the timing when the currents I22 and Id20 are switched from negative to positive, and then the operations in the above-described periods t1 to t9 are repeated.

  In the series of operations described above, the period t6 is a period from when the auxiliary capacitor 30 is charged until the voltage V30 rises to “V30 ≧ V38−Vth32”. For example, the capacity of the auxiliary capacitor 30 is increased. By doing so, the time period t6 can be lengthened. Increasing the time period t6 is advantageous in that the switching frequency can be prevented from becoming too high when the output current Io is small, and an increase in the cross loss of the semiconductor can be suppressed. However, if the time period t6 is made too long, the negative current (regenerative current to the input) appearing in the waveform of the current I22 becomes large, and there is a possibility that the loss regardless of the power supply to the load 28 increases. So be careful. Therefore, the capacity of the auxiliary capacitor 30 is set so that the peak value of the negative current appearing in the waveform of the current I22 is about 1/10 to 1/3 of the peak value of the positive current (current that becomes the output power). It is preferable to do this.

  In order to ZVS the FET 32a of the auxiliary switching element 32 at the start of the period t4, after the period t1 ends, the voltage V30 of the auxiliary capacitor 30 decreases until “V30 ≦ V38−Vth32”. It is necessary to provide time (time of period t2, t3). The time periods t2 and t3 can be lengthened, for example, by increasing the increase width of the voltage V30 in the period t7. As shown in FIG. 7A, the period t7 is a period in which the current I22 of the output inductor 22 is divided into two paths, and the increase amount of the voltage V30 is large in the amount of current in the path for charging the auxiliary capacitor 30. It depends on how few. Since the shunt ratio of the current I22 is almost determined by the ratio of the impedances of the two paths, that is, the capacitance ratio of the parasitic capacitor 32c of the auxiliary switching element 32 and the parasitic capacitor 20c of the main switching element 20, the increase in the voltage V30 in the period t7 is When it is desired to increase the size, it is preferable to select the auxiliary switching element 32 having a large capacitance of the parasitic capacitor 32c. When the auxiliary switching element 32 cannot be changed, an additional capacitor may be connected in parallel with the parasitic capacitor 32c to adjust the capacitance ratio.

  Further, in FIG. 3, the parasitic diode 20b of the main switching element 20 becomes conductive and the voltage Vds20 becomes substantially zero volts (period t8), and then the FET 20a is turned on (period t9). ZVS is realized. However, the timing at which the FET 20a is turned on may be before the parasitic diode 20b is turned on. If the voltage Vds20 is set to be turned on at a timing when the voltage Vds20 becomes lower than a certain level, the cross loss of the main switching element 20 is reduced. be able to. Similarly, in FIG. 3, the parasitic diode 32b of the auxiliary switching element 32 becomes conductive, the voltage Vds32 becomes substantially zero volts (period t3), and then the FET 32a is turned on (period t4). ZVS is realized. However, the timing at which the FET 32a is turned on may be before the parasitic diode 32b is turned on. If the voltage Vds32 is turned on at a timing when the voltage Vds32 becomes lower than a certain level, the cross loss of the auxiliary switching element 32 is suppressed to a small level. be able to.

  Further, in the auxiliary switching element 32, when the forward voltage of the parasitic diode 32b is large, a current flows during the period t3 and conduction loss occurs, and heat generation increases when a small package component is used. For example, the parasitic diode 32b The auxiliary switching element 32 may be formed by connecting an additional diode having a small forward voltage in a parallel position with the MOS FET and an additional diode.

  As described above, since the switching power supply device 10 operates in a so-called critical mode, cross loss, switching noise, etc. (electromagnetic wave noise, voltage surge, ringing, etc.) due to the recovery operation of the output diode 24 hardly occur. Further, since the unique snubber circuit 12 is provided, switching noise and the like when the main switching element 20 is turned off can be suppressed to a small level. In addition, since the main switching element 20 and the auxiliary switching element 32 are ZVS, almost no cross loss or switching noise occurs when the switching elements 20 and 32 are turned on.

  Further, since the configuration of the snubber circuit 12 is very simple, an increase in the mounting space and cost of the snubber circuit 12 can be minimized. Further, the noise filter and the power semiconductor radiator can be made small by the effects of low noise and low loss described above, so that the entire apparatus can be greatly reduced in size and cost.

  Next, a modification of the snubber circuit 12 of the switching power supply device 10 will be described with reference to FIG. Here, the same components as those in the above embodiment are denoted by the same reference numerals and description thereof is omitted. In addition to the configuration of the snubber circuit 12 shown in FIG. 2A, the snubber circuit 42 of this modified example has a cathode between the output of the DC bias circuit 34 and the gate of the auxiliary switching element 32, and the cathode side of the DC bias circuit 34. A parallel circuit of an extraction diode 44 and a gate resistor 46 arranged in the circuit is inserted. The gate resistor 46 functions to limit the current flowing into the gate of the auxiliary switching element 32 (current that charges the gate-source parasitic capacitor 32d) and delay the timing at which the FET 32a is inverted from off to on. The extraction diode 44 prevents the current flowing out from the gate of the auxiliary switching element 32 (current that discharges the parasitic capacitor 32d) from being limited by the gate resistor 46, so that the timing at which the FET 32a is inverted from on to off is not delayed. To work. By providing the gate resistor 46, it becomes easy to set the FET 32a to turn on after the parasitic diode 32b is turned on, and the ZVS of the auxiliary switching element 32 can be more reliably realized (period t3 in FIG. 3). , T4).

  Next, a modification of the DC bias circuit 34 of the switching power supply device 10 will be described with reference to FIGS. Here, the same components as those in the above embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 10A, the DC bias circuit 48 of the first modified example has a smoothing capacitor 38 in a position in series with the charging resistor 36 in addition to the configuration of the DC bias circuit 34 shown in FIG. A discharge blocking diode 50 is inserted to block the discharge current from. By providing the discharge prevention diode 50, the decrease width of the voltage V38 in the period from t3 to t7 can be reduced, and the timing for turning on / off the FET 32a of the auxiliary switching element 32 can be easily set.

  As shown in FIG. 10B, the direct current bias circuit 52 of the second modification has a coupling capacitor 54 having one end connected to the drain of the auxiliary switching element 32 and a cathode at the other end of the coupling capacitor 54. A Zener diode 40 connected to the anode of the output diode 24 and having an anode connected to the anode of the output diode 24; a backflow prevention diode 56 having an anode connected to the cathode of the Zener diode 40; and a cathode of the backflow prevention diode 56 and the output diode 24. And a smoothing capacitor 38 connected to the anode. The DC bias circuit 52 is suitable particularly when the reverse voltage generated at both ends of the output diode 24 is very high. In the case of the DC bias circuits 34 and 48, a certain amount of loss occurs in the charging resistor 36. The DC bias circuit 52 has an advantage that loss can be reduced.

  As shown in FIG. 11A, the DC bias circuit 58 of the third modification is configured such that one end of the series circuit of the charging resistor 36 and the discharge blocking diode 50 of the DC bias circuit 48 is not the drain of the auxiliary switching element 32. The starting resistor 60 is provided between the drain of the auxiliary switching element 32 and the cathode of the Zener diode 40. The starting resistor 60 is a resistor for first turning on the auxiliary switching element 32 when the input power supply 18 is turned on, and has a role different from that of the charging resistor 36 of the DC bias circuit 48. Therefore, the starting resistor 60 has an advantage that the resistance value can be extremely increased, and loss generated in the starting resistor 60 can be reduced. After the auxiliary switching element 32 is first turned on, the smoothing capacitor 38 is charged through the charging resistor 36, and the necessary voltage V38 is ensured regardless of the starting resistor 60. Since the voltage across the charging resistor 36 generates only a low voltage below a certain level, the loss is very small.

  The DC bias circuit 102 of the fourth modification is obtained by changing a part of the configuration of the DC bias circuit 48 of the first modification, and as shown in FIG. 11A, the drain of the auxiliary switching element 32. And a Zener diode 106 having a cathode connected to the other end of the capacitor 104 and an anode connected to the source of the auxiliary switching element 32. The anode of the discharge blocking diode 50 is connected to the capacitor 104. Are connected to the connection point of the zener diode 106, the cathode of the discharge blocking diode 50 is connected to the cathode of the zener diode 40, and the charging resistor 36 is omitted. The capacity of the capacitor 104 is sufficiently smaller than that of the auxiliary capacitor 30 and the smoothing capacitor 38.

  The DC bias circuit 102 is particularly suitable when the reverse voltage generated across the output diode 24 is very high (for example, several hundred volts). In the case of the DC bias circuit 48 described above, a high voltage is generated at both ends of the charging resistor 36 and the reverse current blocking diode 50, so that there is a problem that a certain loss occurs in the charging resistor 36, and a small and high withstand voltage diode element is obtained. Problems such as difficult to do. On the other hand, in the case of the DC bias circuit 102, only a low voltage (a voltage close to the Zener voltage of the Zener diode 106) is generated at both ends of the discharge blocking diode 50. Since the charging resistor 36 is not required, there is an advantage that loss can be suppressed.

  Note that the DC bias circuit 52 shown in FIG. 10B and the DC bias circuit 102 shown in FIG. 11B suppress the peak value of the surge current because there is a possibility that the surge current repeatedly flows through each internal capacitor. Therefore, it is preferable to insert a resistance element having a small resistance value at an appropriate position.

  Next, another embodiment of the switching power supply device of the present invention will be described with reference to FIGS. Here, the same components as those in the above embodiment are denoted by the same reference numerals and description thereof is omitted. As shown in FIG. 12, the switching power supply device 62 of the second embodiment includes a step-down chopper type power conversion circuit 64, and the snubber circuit 12 is provided at both ends of the output diode 24. The point that the control circuit 16 controls the critical mode is the same. In the case of the step-up chopper type power conversion circuit 14 described above, during the period in which the main switching element 20 is on, the output inductor 22 is excited by the input power supply 18 without supplying power from the input power supply 18 to the output, and the main switching element 20 Is off, the excitation energy stored in the output inductor 22 is released to the output to supply power to the load 28. On the other hand, the step-down chopper type power conversion circuit 64 supplies power from the input power supply 18 to the load 28 while the main switching element 20 is on, and excites the output inductor 22 by the input power supply 18 to perform main switching. There is a difference in operation in which the excitation energy stored in the output inductor 22 is discharged to the output and power is supplied to the load 28 while the element 20 is off.

  However, the step-down chopper type switching power supply device 62 also has the same excellent effect as the switching power supply device 10 when the control circuit 16 controls the critical mode and the snubber circuit 12 operates.

  As shown in FIG. 13, the switching power supply device 66 of the third embodiment includes a buck-boost chopper type power conversion circuit 68, and the snubber circuit 12 is provided at both ends of the output diode 24. The point that the control circuit 16 controls the critical mode is the same.

  The step-up / step-down chopper type power conversion circuit 68 does not supply power from the input power source 18 to the output while the main switching element 20 is on, similarly to the step-up chopper type power conversion circuit 14 described above. Thus, the output inductor 22 is excited, and the excitation energy stored in the output inductor 22 is discharged to the output while the main switching element 20 is off to supply power to the load 28. The step-up / step-down chopper type switching power supply device 66 also has the same excellent effects as the switching power supply device 10 and the like when the control circuit 16 controls the critical mode and the snubber circuit 12 operates.

  As shown in FIG. 14, the switching power supply device 70 of the fourth embodiment includes a step-up / down chopper type power conversion circuit 72 called an H-bridge converter. The power conversion circuit 72 includes two main switching elements 20 (1) and 20 (2) that are turned on and off in the same phase, and two output diodes 24 (1) and 24 that are turned on and off in the same phase. (2), and the output inductor 22 is arranged in the center and connected in a bridge shape. Then, snubber circuits 12 (1) and 12 (2) similar to the above are provided at both ends of the output diodes 24 (1) and 24 (2). The point that the control circuit 16 controls the critical mode is the same.

  The step-up / step-down chopper type power conversion circuit 72 is similar to the step-up / step-down chopper type power conversion circuit 68 described above, and does not supply power from the input power source 18 to the output while the main switching element 20 is on. 18, the output inductor 22 is excited, and during the period in which the main switching element 20 is off, the excitation energy stored in the output inductor 22 is released to the output to supply power to the load 28. Unlike the power conversion circuit 68, the power conversion circuit 72 is characterized in that the ground of the input voltage Vi and the output voltage Vo can be set to the same potential.

  The step-up / step-down chopper type switching power supply 70 also has excellent effects similar to those of the switching power supply 10 and the like by the control circuit 16 controlling the critical mode and the snubber circuits 12 (1) and 12 (2) operating. Is obtained.

  As shown in FIG. 15, the switching power supply device 74 of the fifth embodiment includes an insulating power conversion circuit 76 called a flyback converter, and the snubber circuit 12 is provided at both ends of the output diode 24. . In the power conversion circuit 76, a transformer having two windings 22 (1) and 22 (2) magnetically coupled to each other serves as the output inductor 22. The point that the control circuit 16 controls the critical mode is the same.

  The insulated power conversion circuit 76 is output by the input power supply 18 without supplying power from the input power supply 18 to the output while the main switching element 20 is on, similarly to the step-up chopper type power conversion circuit 14 described above. The inductor 22 is excited, and during the period when the main switching element 20 is off, the excitation energy stored in the output inductor 22 is released to the output to supply power to the load 28. The power conversion circuit 76 is characterized in that an operation for exciting the output inductor 22 is performed through the winding 22 (1), and an operation for releasing the excitation energy is performed through the winding 22 (2).

  The switching power supply 74 also has the same excellent effects as the switching power supply 10 and the like when the control circuit 16 controls the critical mode and the snubber circuit 12 operates.

  As shown in FIG. 16A, the switching power supply device 78 of the sixth embodiment includes a step-up chopper type power conversion circuit 14, and a novel snubber circuit 80 is provided at both ends of the output diode 24. The point that the control circuit 16 controls the critical mode is the same.

  The snubber circuit 80 includes an auxiliary capacitor 30, an auxiliary switching element 82, and a DC bias circuit 84. The auxiliary capacitor 30 has one end connected to the cathode of the output diode 24. The auxiliary switching element 82 is a P-channel MOS FET, and has a source connected to the other end of the auxiliary capacitor 30 and a drain connected to the anode of the output diode 24. The DC bias circuit 84 is a circuit that biases the gate of the auxiliary switching element 82 and the cathode of the output diode 24 in the negative direction with a predetermined DC voltage.

  As shown in FIG. 16B, the internal configuration of the DC bias circuit 84 includes a charging resistor 36 having one end connected to the drain of the auxiliary switching element 82, the other end of the charging resistor 36, and the cathode of the output diode 24. A smoothing capacitor 38 connected between them and a Zener diode 40 (zener voltage Vz40) having an anode connected to the other end of the charging resistor 36 and a cathode connected to the cathode of the output diode 24 are provided. The DC bias circuit 84 performs an operation of substantially averaging the pulse voltage at both ends of the output diode 24 by the charging resistor 36 and the smoothing capacitor 38. At the both ends of the smoothing capacitor 38, a substantially DC voltage V38 defined by the Zener voltage Vz40 is obtained. (Negative voltage) is generated to bias between the gate of the auxiliary switching element 32 and the cathode of the output diode 24.

  The snubber circuit 80 is a complementary circuit of the snubber circuit 12 using an N-channel MOS FET, and the basic operation is the same. Therefore, the switching power supply device 78 also has the same excellent effects as the switching power supply device 10 and the like when the control circuit 16 controls the critical mode and the snubber circuit 80 operates.

  FIG. 17 shows a modification of the snubber circuit 80. The snubber circuit 86 of this modification is a parallel circuit of an extraction diode 44 and a gate resistor 46 whose anode is arranged on the DC bias circuit 84 side between the output of the DC bias circuit 84 and the gate of the auxiliary switching element 82. Has been inserted. The snubber circuit 86 is a complementary circuit of the snubber circuit 42 shown in FIG. 9, and the same operation and effect can be obtained.

  FIG. 18A shows a first modification of the DC bias circuit 84. In the DC bias circuit 88 of the first modification, in addition to the configuration of the DC bias circuit 84, a discharge blocking diode 50 for blocking the discharge current from the smoothing capacitor 38 is inserted at a position in series with the charging resistor 36. The DC bias circuit 88 is a complementary circuit of the DC bias circuit 48 shown in FIG. 10A, and the same operation and effect can be obtained.

  FIG. 18B shows a second modification of the DC bias circuit 84. The DC bias circuit 90 of the second modification has a coupling capacitor 54 having one end connected to the drain of the auxiliary switching element 82, an anode connected to the other end of the coupling capacitor 54, and a cathode connected to the cathode of the output diode 24. Is connected to the anode of the Zener diode 40, and the anode of the Zener diode 40 is connected to the cathode of the backflow preventing diode 56. And a capacitor 38. The DC bias circuit 90 is a complementary circuit of the DC bias circuit 52 shown in FIG. 10B, and can obtain the same operation and effect.

  Further, FIG. 19 shows a third modification of the DC bias circuit 84. A DC bias circuit 92 according to a third modification is configured such that one end of a series circuit of the charging resistor 36 and the discharge blocking diode 50 of the DC bias circuit 88 is connected to the source instead of the drain of the auxiliary switching element 82. The starting resistor 60 is provided between the drain of 82 and the anode of the Zener diode 40. The DC bias circuit 92 is a complementary circuit of the DC bias circuit 58 shown in FIG. 11, and can obtain the same effect.

  The switching power supply device of the present invention is not limited to the above embodiment. For example, the power conversion circuit may be a circuit that includes a predetermined main switching element, an output diode, and an output inductor, and that is configured so that the control circuit can perform critical mode control. A configuration other than a circuit may be used.

  The main switching element is preferably a MOS FET, but other transistor elements capable of conducting in both directions may be used. When an element that conducts in only one direction, such as a bipolar transistor, is used, it can be combined with a parallel diode for flowing current in the opposite direction to form one main switching element.

  The auxiliary switching element of the snubber circuit is preferably an N- or P-channel MOS type FET. However, if the conditions are met, other semiconductors such as a bipolar transistor, IGBT, and SCR can be used to achieve the same operation. it can. For example, as shown in FIG. 20, an operation similar to that of the snubber circuit 12 can be realized by a snubber circuit 100 in which an NPN bipolar transistor 94, a diode 96, a base resistor 98, an auxiliary capacitor 30, and a DC bias circuit 34 are combined. However, in the case of the snubber circuit 100, the number of parts is increased as compared with the snubber circuit 12, and a problem peculiar to the bipolar transistor 94 (for example, when the switching frequency is very high, the bipolar transistor 94 is turned off quickly at an appropriate timing. Therefore, care must be taken when setting the constant of each element. The same precautions are necessary when other semiconductors are used.

  The DC bias circuit provided in the snubber circuit may be a circuit that generates a predetermined DC voltage corresponding to the voltage V38 of the smoothing capacitor 38 described above, and can be changed to a configuration other than the configuration of the above-described embodiment and the modified example. it can. For example, when another winding is provided in the output inductor for some purpose, a DC voltage corresponding to the voltage V38 can be generated by rectifying and smoothing the voltage generated in the other winding. In addition, when the main switching element is provided on the low side and the auxiliary switching element is provided on the high side as in the boost chopper, a direct current voltage supplied to an IC or the like that drives the main switching element is used with a diode and a capacitor. Then, a DC voltage corresponding to the voltage V38 may be generated by bootstrapping.

10, 62, 66, 70, 74, 78 Switching power supply device 12, 12 (1), 12 (2), 42, 68, 72, 76, 80, 86 Snubber circuit 14, 64 Power conversion circuit 16 Control circuit 18 Input Power source 20, 20 (1), 20 (2) Main switching element 22 Output inductor 24, 24 (1), 24 (2) Output diode 30, 30 (1), 30 (2) Auxiliary capacitor 32, 32 (1) , 32 (2), 82 Auxiliary switching elements 34, 34 (1), 34 (2), 48, 52, 58, 84, 88, 90, 92, 102 DC bias circuit 36 Charging resistor 38 Smoothing capacitor 40 Zener diode 44 Extraction diode 46 Gate resistance 50 Discharge blocking diode 54 Coupling capacitor 56 Backflow prevention diode 60 Start resistance

Claims (14)

A main switching element connected in series to an input power supply to intermittently input voltage, and an excitation energy that is excited by the input power supply while the main switching element is on and is stored during the on period, and the main switching element is off An output inductor that discharges to the output, and an output diode that conducts when the main switching element is off and serves as a current path when the excitation energy is discharged to the output. A power conversion circuit for supplying power to the power supply,
In a switching power supply device comprising a control circuit for controlling the on-time and off-time of the main switching element,
The power conversion circuit is provided with a snubber circuit,
The snubber circuit includes an auxiliary capacitor having one end connected to the anode of the output diode, and an N-channel MOS FET having a source connected to the other end of the auxiliary capacitor and a drain connected to the cathode of the output diode. An auxiliary switching element, and a DC bias circuit for biasing in a positive direction with a predetermined DC voltage between the gate of the auxiliary switching element and the anode of the output diode,
The control circuit performs a critical mode control in which the main switch element is quickly reversed from off to on after the excitation energy of the output inductor is released through the output diode.
After the main switching element is turned off, the auxiliary switching element has its gate-source voltage increased due to a decrease in the voltage of the auxiliary capacitor, and the gate-source voltage exceeds the ON threshold. Inverted from off to on, and then, before the main switching element is turned on, the voltage of the auxiliary capacitor rises to reduce its own gate-source voltage, and the gate-source voltage reaches the on threshold. A switching power supply that reverses from on to off at a lower timing. Between the output of the DC bias circuit and the gate of the auxiliary switching element, a parallel circuit of an extraction diode and a gate resistor in which a cathode is arranged on the DC bias circuit side is inserted,
2. The switching power supply device according to claim 1, wherein the gate resistor delays a timing at which the auxiliary switching element is inverted from off to on by limiting a current flowing into a gate of the auxiliary switching element. The DC bias circuit includes:
A charging resistor having one end connected to the drain of the auxiliary switching element, a smoothing capacitor connected between the other end of the charging resistor and the anode of the output diode, and a cathode connected to the other end of the charging resistor. A Zener diode having an anode connected to the anode of the output diode,
The switching power supply device according to claim 1 or 2, wherein the predetermined DC voltage defined by a Zener voltage of the Zener diode is output from a connection point between the charging resistor and the smoothing capacitor.   The switching power supply device according to claim 3, wherein a discharge blocking diode for blocking a discharge current from the smoothing capacitor is inserted at a position in series with the charging resistor. The DC bias circuit includes:
A coupling capacitor having one end connected to the drain of the auxiliary switching element, a Zener diode having a cathode connected to the other end of the coupling capacitor, and an anode connected to the anode of the output diode, and the cathode of the Zener diode A backflow prevention diode having an anode connected thereto, and a smoothing capacitor connected between a cathode of the backflow prevention diode and an anode of the output diode,
The switching power supply according to claim 1 or 2, wherein the predetermined DC voltage defined by a Zener voltage of the Zener diode is output from a connection point between the backflow prevention diode and the smoothing capacitor. A main switching element connected in series to an input power supply to intermittently input voltage, and an excitation energy that is excited by the input power supply while the main switching element is on and is stored during the on period, and the main switching element is off An output inductor that discharges to the output, and an output diode that conducts when the main switching element is off and serves as a current path when the excitation energy is discharged to the output. A power conversion circuit for supplying power to the power supply,
In a switching power supply device comprising a control circuit for controlling the on-time and off-time of the main switching element,
The power conversion circuit is provided with a snubber circuit,
The snubber circuit includes an auxiliary capacitor having one end connected to the cathode of the output diode, and a P-channel MOS FET having a source connected to the other end of the auxiliary capacitor and a drain connected to the anode of the output diode. An auxiliary switching element, and a DC bias circuit for biasing in a negative direction with a predetermined DC voltage between the gate of the auxiliary switching element and the cathode of the output diode,
The control circuit performs a critical mode control in which the main switch element is quickly reversed from off to on after the excitation energy of the output inductor is released through the output diode.
After the main switching element is turned off, the auxiliary switching element has its gate-source voltage increased due to a decrease in the voltage of the auxiliary capacitor, and the gate-source voltage exceeds the ON threshold. Inverted from off to on, and then, before the main switching element is turned on, the voltage of the auxiliary capacitor rises to reduce its own gate-source voltage, and the gate-source voltage reaches the on threshold. A switching power supply that reverses from on to off at a lower timing. Between the output of the DC bias circuit and the gate of the auxiliary switching element, a parallel circuit of an extraction diode and a gate resistor in which an anode is disposed on the DC bias circuit side is inserted,
The switching power supply device according to claim 6, wherein the gate resistor delays a timing at which the auxiliary switching element is inverted from off to on by limiting a current flowing out from a gate of the auxiliary switching element. The DC bias circuit includes:
A charging resistor having one end connected to the drain of the auxiliary switching element, a smoothing capacitor connected between the other end of the charging resistor and the cathode of the output diode, and an anode connected to the other end of the charging resistor A Zener diode having a cathode connected to the cathode of the output diode,
The switching power supply according to claim 6 or 7, wherein the predetermined DC voltage defined by a Zener voltage of the Zener diode is output from a connection point between the charging resistor and the smoothing capacitor.   The switching power supply device according to claim 8, wherein a discharge blocking diode for blocking a discharge current from the smoothing capacitor is inserted at a position in series with the charging resistor. The DC bias circuit includes:
A coupling capacitor having one end connected to the drain of the auxiliary switching element, a Zener diode having an anode connected to the other end of the coupling capacitor, and a cathode connected to the cathode of the output diode, and an anode of the Zener diode A backflow prevention diode having a cathode connected thereto, and a smoothing capacitor connected between an anode of the backflow prevention diode and a cathode of the output diode,
The switching power supply according to claim 6 or 7, wherein the predetermined DC voltage defined by a Zener voltage of the Zener diode is output from a connection point between the backflow prevention diode and the smoothing capacitor.   The control circuit reverses the main switch element from off to on at a timing when the voltage across the main switching element drops to a predetermined voltage after the excitation energy of the output inductor is released through the output diode. Item 11. The switching power supply device according to any one of Items 1 to 10.   The switching power supply according to claim 1, wherein an additional capacitor is connected between a drain and a source of the auxiliary switching element. The power conversion circuit includes:
While the main switching element is on, power is supplied from the input power source to the load and the output inductor is excited by the input power source,
The switching power supply device according to any one of claims 1 to 12, wherein, during a period in which the main switching element is off, the excitation energy stored in the output inductor is discharged to an output to supply power to the load. The power conversion circuit includes:
While the main switching element is on, the output inductor is excited by the input power supply without supplying power from the input power supply to the output,
The switching power supply device according to any one of claims 1 to 12, wherein, during a period in which the main switching element is off, the excitation energy stored in the output inductor is discharged to an output to supply power to the load.

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