JP6851773B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6851773B2 JP6851773B2 JP2016212797A JP2016212797A JP6851773B2 JP 6851773 B2 JP6851773 B2 JP 6851773B2 JP 2016212797 A JP2016212797 A JP 2016212797A JP 2016212797 A JP2016212797 A JP 2016212797A JP 6851773 B2 JP6851773 B2 JP 6851773B2
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- H—ELECTRICITY
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- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
- H10F39/026—Wafer-level processing
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- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/804—Containers or encapsulations
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- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/805—Coatings
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- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/811—Interconnections
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- H10P74/27—Structural arrangements therefor
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- H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
- H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/652—Cross-sectional shapes
- H10W70/6528—Cross-sectional shapes of the portions that connect to chips, wafers or package parts
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- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
- H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
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- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
- H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
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- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01251—Changing the shapes of bumps
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- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
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- H—ELECTRICITY
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- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
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- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/331—Shapes of die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W99/00—Subject matter not provided for in other groups of this subclass
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- Solid State Image Pick-Up Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016212797A JP6851773B2 (ja) | 2016-10-31 | 2016-10-31 | 半導体装置 |
| US15/726,602 US10381399B2 (en) | 2016-10-31 | 2017-10-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016212797A JP6851773B2 (ja) | 2016-10-31 | 2016-10-31 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018074022A JP2018074022A (ja) | 2018-05-10 |
| JP2018074022A5 JP2018074022A5 (enExample) | 2019-12-12 |
| JP6851773B2 true JP6851773B2 (ja) | 2021-03-31 |
Family
ID=62064843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016212797A Active JP6851773B2 (ja) | 2016-10-31 | 2016-10-31 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US10381399B2 (enExample) |
| JP (1) | JP6851773B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017122449A1 (ja) * | 2016-01-15 | 2017-07-20 | ソニー株式会社 | 半導体装置および撮像装置 |
| US12376400B2 (en) * | 2018-05-28 | 2025-07-29 | Sony Semiconductor Solutions Corporation | Imaging device |
| TWI870807B (zh) * | 2023-03-23 | 2025-01-21 | 同欣電子工業股份有限公司 | 晶片封裝結構 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002198463A (ja) | 2000-12-26 | 2002-07-12 | Canon Inc | チップサイズパッケージおよびその製造方法 |
| JP4271909B2 (ja) | 2002-07-29 | 2009-06-03 | 富士フイルム株式会社 | 固体撮像装置およびその製造方法 |
| JP4241160B2 (ja) | 2002-04-22 | 2009-03-18 | 富士フイルム株式会社 | 固体撮像装置の製造方法 |
| US7074638B2 (en) | 2002-04-22 | 2006-07-11 | Fuji Photo Film Co., Ltd. | Solid-state imaging device and method of manufacturing said solid-state imaging device |
| JP2004063765A (ja) | 2002-07-29 | 2004-02-26 | Fuji Photo Film Co Ltd | 固体撮像装置およびその製造方法 |
| JP2004063786A (ja) | 2002-07-29 | 2004-02-26 | Fuji Photo Film Co Ltd | 固体撮像装置およびその製造方法 |
| JP4248928B2 (ja) | 2003-05-13 | 2009-04-02 | ローム株式会社 | 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置 |
| JP4551638B2 (ja) | 2003-08-01 | 2010-09-29 | 富士フイルム株式会社 | 固体撮像装置の製造方法 |
| JP2005056998A (ja) | 2003-08-01 | 2005-03-03 | Fuji Photo Film Co Ltd | 固体撮像装置およびその製造方法 |
| JP2006030159A (ja) | 2004-06-15 | 2006-02-02 | Canon Inc | ピエゾ抵抗型半導体装置及びその製造方法 |
| JP2008047723A (ja) * | 2006-08-17 | 2008-02-28 | Epson Toyocom Corp | 表面実装型電子デバイス、調整用プローブ装置、及び表面実装型電子デバイスの調整方法 |
| KR100769722B1 (ko) | 2006-10-10 | 2007-10-24 | 삼성전기주식회사 | 이미지센서의 웨이퍼 레벨 칩 스케일 패키지 및 그제조방법 |
| JP2008130738A (ja) | 2006-11-20 | 2008-06-05 | Fujifilm Corp | 固体撮像素子 |
| JP5344336B2 (ja) | 2008-02-27 | 2013-11-20 | 株式会社ザイキューブ | 半導体装置 |
| JP5175620B2 (ja) * | 2008-05-29 | 2013-04-03 | シャープ株式会社 | 電子素子ウェハモジュールおよびその製造方法、電子素子モジュール、電子情報機器 |
| JP2011146486A (ja) * | 2010-01-13 | 2011-07-28 | Panasonic Corp | 光学デバイスおよびその製造方法ならびに電子機器 |
| CN103077951B (zh) * | 2013-01-09 | 2016-03-30 | 苏州晶方半导体科技股份有限公司 | Bsi图像传感器的晶圆级封装方法 |
-
2016
- 2016-10-31 JP JP2016212797A patent/JP6851773B2/ja active Active
-
2017
- 2017-10-06 US US15/726,602 patent/US10381399B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2018074022A (ja) | 2018-05-10 |
| US10381399B2 (en) | 2019-08-13 |
| US20180130846A1 (en) | 2018-05-10 |
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