JP6830351B2 - 回路 - Google Patents
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- JP6830351B2 JP6830351B2 JP2016250634A JP2016250634A JP6830351B2 JP 6830351 B2 JP6830351 B2 JP 6830351B2 JP 2016250634 A JP2016250634 A JP 2016250634A JP 2016250634 A JP2016250634 A JP 2016250634A JP 6830351 B2 JP6830351 B2 JP 6830351B2
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- transistor
- insulator
- oxide
- circuit
- potential
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- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
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- MGWGWNFMUOTEHG-UHFFFAOYSA-N 4-(3,5-dimethylphenyl)-1,3-thiazol-2-amine Chemical compound CC1=CC(C)=CC(C=2N=C(N)SC=2)=C1 MGWGWNFMUOTEHG-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
- G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
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Description
本実施の形態では、階調電圧生成回路としての機能を有する半導体装置10の一例について説明する。
図1(A)は、増幅回路51の一例を示す。増幅回路51は、非反転入力端子として機能する端子INと、反転入力端子として機能する端子IN−と、出力端子として機能する端子OUTと、を有する。端子INには、電位VINが与えられる。端子OUTからは、電位VOUTが出力される。端子IN−には、端子OUTからの出力がフィードバックされる。
本発明の一態様の半導体装置10は、デジタルアナログ変換回路(以下、D/A変換回路)11、D/A変換回路31、D/A変換回路32、及び増幅回路51を有する。増幅回路51は、増幅回路52及び増幅回路53を有する。
図5には、図4と異なる半導体装置10の一例を示す。図5に示す半導体装置10では、増幅回路52として図1(B)に示す回路を用い、増幅回路53として、図3(B)に示す回路を用いる。
D/A変換回路11、D/A変換回路31及びD/A変換回路32は、デジタル信号に基づき、アナログ値を生成する回路である。例えば、D/A変換回路11、D/A変換回路31及びD/A変換回路32は、デジタル信号に基づき、階調電圧を生成することができる。
本実施の形態では、本発明の一態様の半導体装置の構造の一例を説明する。
本発明の一態様の半導体装置の断面構造の一例を図10に示す。本発明の一態様の半導体装置は例えば、後述する信号線駆動回路100、または信号線駆動回路100の一部、を有することが好ましい。
本実施の形態では、実施の形態1に示した半導体装置10を含む表示パネルについて説明を行う。
図12の回路ブロック図に示す表示パネルは、信号線駆動回路100、走査線駆動回路101、及び画素部102を有する。また、画素部102中にマトリクス状に配置された複数の画素103を示している。なお、画素部102を表示部と呼ぶ場合もある。
次に、図13を用いて信号線駆動回路100の詳細について説明を行う。図13に示す回路ブロック図は、Nビットの画像信号を処理することが可能な信号線駆動回路100の構成例を示している。
図14(A)は発光素子を有するパネルに用いることができる画素103の一例を示す。図14(B)は図14(A)に示す画素103の動作例を示すタイミングチャートである。
図16(A)に、液晶素子を有するパネルに用いることができる画素回路の一例を示す。図16(A)に示す画素103は、トランジスタ131と、容量素子133と、表示素子として機能できる液晶素子134とを有する。
本実施の形態では、上記実施の形態に示す表示パネルのより具体的な構成例について、図17乃至図21を用いて説明を行う。なお、本実施の形態では、表示パネルの一例として、液晶素子を用いた表示パネル及び発光素子を用いた表示パネルについて説明する。
図17(A)乃至(C)は、表示パネルの構成例を示す上面図である。
図19(A)及び図19(B)は、図17(B)中でN1−N2の鎖線で示した部位の断面構成を示す断面図である。
次いで上記実施の形態に示す表示パネルを用いた表示モジュールの応用例について、図24を用いて説明を行う。
本実施の形態では、上記実施の形態に示す表示パネルを適用した電子機器の例について、図26を用いて説明を行う。
本実施の形態では、本発明の一態様に適用可能なトランジスタの一例について述べる。
以下に説明するトランジスタ200は、前述のトランジスタ200a及びトランジスタ200bに適用することができるトランジスタである。
以下では、酸化物半導体の構造について説明する。
まずは、CAAC−OSについて説明する。
次に、nc−OSについて説明する。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。
次に、酸化物半導体のキャリア密度について、以下に説明を行う。
以下に、本発明に係る酸化物について説明する。
11 D/A変換回路
11a 電圧生成回路
11b PTL
11e トランジスタ
11f トランジスタ
31 D/A変換回路
32 D/A変換回路
40 端子
41 端子
42 端子
51 増幅回路
52 増幅回路
52a トランジスタ
52b トランジスタ
52c トランジスタ
52i トランジスタ
52j トランジスタ
52k トランジスタ
53 増幅回路
53a トランジスタ
53b トランジスタ
53c トランジスタ
53d トランジスタ
53e トランジスタ
53f トランジスタ
53g トランジスタ
53i トランジスタ
53j トランジスタ
53k トランジスタ
53L トランジスタ
53m トランジスタ
53n トランジスタ
53p トランジスタ
54 電流源
55 電流源
56a 回路
56b 回路
56c 回路
100 信号線駆動回路
100a 信号線駆動回路
100b 信号線駆動回路
101 走査線駆動回路
101a 走査線駆動回路
101b 走査線駆動回路
102 画素部
103 画素
104 導電体
106a 絶縁体
106b 絶縁体
108 酸化物半導体
108_1 層
108_2 層
108_3 層
108a 酸化物半導体
108b 酸化物半導体
108d ドレイン領域
108i チャネル領域
108s ソース領域
110 絶縁体
111 シフトレジスタ
112 ラッチ回路
112a 導電体
112b 導電体
113 レベルシフタ
114 D/A変換回路
115 増幅回路
116 絶縁体
118 LVDSレシーバ
119 ロジック回路
120 トランジスタ
120a 導電体
120b 導電体
121 トランジスタ
122 トランジスタ
123 容量素子
124 ノード
125 ノード
126 発光素子
131 トランジスタ
132 ノード
133 容量素子
134 液晶素子
141a 開口部
141b 開口部
142a 開口部
142b 開口部
142c 開口部
151a 領域
151b 領域
200 トランジスタ
200a トランジスタ
200b トランジスタ
201 駆動回路
202 検出回路
203 容量素子
204 容量
205 導電体
205a 導電体
205b 導電体
209 IC
210 絶縁体
212 絶縁体
214 絶縁体
216 絶縁体
218 導電体
220 絶縁体
222 絶縁体
224 絶縁体
230 酸化物半導体
230a 酸化物半導体
230b 酸化物半導体
230c 酸化物半導体
230d 酸化物半導体
240a 導電体
240b 導電体
241a 導電体
241b 導電体
244 導電体
245 導電体
250 絶縁体
260 導電体
260a 導電体
260b 導電体
260c 導電体
270 絶縁体
280 絶縁体
282 絶縁体
284 絶縁体
300 トランジスタ
300n トランジスタ
300p トランジスタ
301 基板
302 半導体領域
303 半導体領域
304 絶縁体
306 導電体
306n 導電体
306p 導電体
308a 低抵抗領域
308b 低抵抗領域
308c 低抵抗領域
308d 低抵抗領域
320 絶縁体
321 絶縁体
322 絶縁体
324 絶縁体
326 絶縁体
328 導電体
330 導電体
350 絶縁体
352 絶縁体
354 絶縁体
356 導電体
358 絶縁体
400 基板
407n チャネル形成領域
407p チャネル形成領域
455 導電体
455n 導電体
455p 導電体
460 素子分離領域
474n 領域
474p 領域
476a 低抵抗領域
476b 低抵抗領域
476c 低抵抗領域
476d 低抵抗領域
510 電極
511 電極
512 半導体層
516 電極
517 電極
602 基板
614 絶縁体
618 絶縁体
622 絶縁体
624 絶縁体
800 表示モジュール
801 上部カバー
802 下部カバー
803 FPC
804 タッチパネル
805 FPC
806 表示パネル
807 バックライトユニット
808 光源
809 フレーム
810 プリント基板
811 バッテリー
4001 基板
4001a 層
4005 シール材
4006 基板
4008 液晶層
4010 トランジスタ
4011 トランジスタ
4012 トランジスタ
4013 液晶素子
4014 配線
4015 電極
4018 FPC
4018b FPC
4019 異方性導電層
4020 容量素子
4021 電極
4030 電極層
4031 電極層
4032 絶縁層
4033 絶縁層
4035 スペーサ
4102 絶縁層
4103 絶縁層
4110 絶縁層
4111 絶縁層
4112 絶縁層
4510 隔壁
4511 発光層
4513 発光素子
4514 充填材
7000 表示装置
7001 筐体
7002 表示部
7003 支持台
7100 携帯情報端末
7101 筐体
7102 表示部
7103 バンド
7104 バックル
7105 操作ボタン
7106 入出力端子
7107 アイコン
7200 PC
7221 筐体
7222 表示部
7223 キーボード
7224 ポインティングデバイス
7400 携帯電話機
7401 筐体
7402 表示部
7403 操作ボタン
7404 外部接続ポート
7405 スピーカ
7406 マイクロフォン
7500 自動車
7551 車体
7552 車輪
7553 ダッシュボード
7554 ライト
7600 ビデオカメラ
7641 筐体
7642 筐体
7643 表示部
7644 操作キー
7645 レンズ
7646 接続部
Claims (4)
- Nビットの信号が入力される回路であり、
第1のデジタルアナログ変換回路と、第2のデジタルアナログ変換回路と、第3のデジタルアナログ変換回路と、増幅回路と、を有し、
前記増幅回路は、第1のトランジスタ、第2のトランジスタ、第3のトランジスタ及び第4のトランジスタを有し、
前記第1のトランジスタ及び前記第2のトランジスタは、nチャネル型トランジスタであり、
前記第3のトランジスタ及び前記第4のトランジスタは、pチャネル型トランジスタであり、
前記第1のデジタルアナログ変換回路の出力端子は、前記第1のトランジスタのゲートと、前記第3のトランジスタのゲートと、に電気的に接続され、
前記第2のデジタルアナログ変換回路の出力端子は、前記第2のトランジスタの基板電位に電気的に接続され、
前記第3のデジタルアナログ変換回路の出力端子は、前記第4のトランジスタの基板電位に電気的に接続され、
前記第1のトランジスタのソース及びドレインの一方は、前記第2のトランジスタのソース及びドレインの一方と電気的に接続され、
前記第3のトランジスタのソース及びドレインの一方は、前記第4のトランジスタのソース及びドレインの一方と電気的に接続され、
前記増幅回路の出力端子は、前記第2のトランジスタのゲートと、前記第4のトランジスタのゲートと、に電気的に接続され、
前記第1のデジタルアナログ変換回路には、前記Nビットの信号のうち、上位のMビットの信号が入力され、
前記第2のデジタルアナログ変換回路及び前記第3のデジタルアナログ変換回路には、前記Nビットの信号のうち、下位の(N−M)ビットの信号が入力される回路。 - Nビットの信号が入力される回路であり、
第1のデジタルアナログ変換回路と、第2のデジタルアナログ変換回路と、増幅回路と、を有し、
前記増幅回路は、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、第4のトランジスタと、を有し、
前記第1のトランジスタは、前記第2のトランジスタの差動対であり、
前記第3のトランジスタは、前記第4のトランジスタの差動対であり、
前記第1のデジタルアナログ変換回路の出力端子は、前記第1のトランジスタのゲートと、前記第3のトランジスタのゲートと、に電気的に接続され、
前記第2のデジタルアナログ変換回路の出力端子は、前記第2のトランジスタの基板電位に電気的に接続され、
前記第1のデジタルアナログ変換回路には、前記Nビットの信号のうち、上位のMビットの信号が入力され、
前記第2のデジタルアナログ変換回路には、前記Nビットの信号のうち、下位の(N−M)ビットの信号が入力される回路。 - Nビットの信号が入力される回路であり、
第1のデジタルアナログ変換回路と、第2のデジタルアナログ変換回路と、第1の増幅回路と、第2の増幅回路と、を有し、
前記第1の増幅回路は、入力端子と、第1の出力端子と、第2の出力端子と、を有し、
前記第1のデジタルアナログ変換回路の出力端子は、前記第1の増幅回路が有する前記入力端子に電気的に接続され、
前記第2の増幅回路は、第1のトランジスタと、第2のトランジスタと、を有し、
前記第1のトランジスタのゲートと前記第2のトランジスタのゲートは、電気的に接続され、
前記第2のデジタルアナログ変換回路の出力端子は、前記第1のトランジスタの基板電位に電気的に接続され、
前記第1のトランジスタのソース及びドレインの一方と、前記第2のトランジスタのソース及びドレインの一方と、には第1の電位が与えられ、
前記第1のトランジスタ及び前記第2のトランジスタがpチャネル型トランジスタの場合には、前記第1の電位は高電位信号であり、
前記第1のトランジスタ及び前記第2のトランジスタがnチャネル型トランジスタの場合には、前記第1の電位は低電位信号であり、
前記第1のトランジスタのソース及びドレインの他方は、前記第1の増幅回路が有する前記第1の出力端子に電気的に接続され、
前記第2のトランジスタのソース及びドレインの他方は、前記第1の増幅回路が有する前記第2の出力端子に電気的に接続され、
前記第1のデジタルアナログ変換回路には、前記Nビットの信号のうち、上位のMビットの信号が入力され、
前記第2のデジタルアナログ変換回路には、前記Nビットの信号のうち、下位の(N−M)ビットの信号が入力される回路。 - 請求項3において、
前記第1の増幅回路は、第3のトランジスタと、第4のトランジスタと、を有し、
前記第3のトランジスタは、前記第4のトランジスタの差動対であり、
前記第3のトランジスタのソース及びドレインの一方は、前記第1の増幅回路が有する前記第1の出力端子に電気的に接続され、
前記第4のトランジスタのソース及びドレインの一方は、前記第1の増幅回路が有する前記第2の出力端子に電気的に接続される回路。
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