JP6788607B2 - 階段型コンタクトソケット領域を形成する方法 - Google Patents

階段型コンタクトソケット領域を形成する方法 Download PDF

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JP6788607B2
JP6788607B2 JP2017552102A JP2017552102A JP6788607B2 JP 6788607 B2 JP6788607 B2 JP 6788607B2 JP 2017552102 A JP2017552102 A JP 2017552102A JP 2017552102 A JP2017552102 A JP 2017552102A JP 6788607 B2 JP6788607 B2 JP 6788607B2
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area
socket
electrode
memory
horizontal
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JP2018513559A (ja
JP2018513559A5 (enExample
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潤 角野
潤 角野
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
JP2017552102A 2015-04-24 2016-04-14 階段型コンタクトソケット領域を形成する方法 Expired - Fee Related JP6788607B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/695,835 2015-04-24
US14/695,835 US9515125B2 (en) 2015-04-24 2015-04-24 Socket structure for three-dimensional memory
PCT/JP2016/002025 WO2016170759A1 (en) 2015-04-24 2016-04-14 Socket structure for three-dimensional memory

Publications (3)

Publication Number Publication Date
JP2018513559A JP2018513559A (ja) 2018-05-24
JP2018513559A5 JP2018513559A5 (enExample) 2019-05-23
JP6788607B2 true JP6788607B2 (ja) 2020-11-25

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JP2017552102A Expired - Fee Related JP6788607B2 (ja) 2015-04-24 2016-04-14 階段型コンタクトソケット領域を形成する方法

Country Status (4)

Country Link
US (3) US9515125B2 (enExample)
JP (1) JP6788607B2 (enExample)
KR (1) KR20170141665A (enExample)
WO (1) WO2016170759A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9478556B2 (en) 2014-09-11 2016-10-25 Kabushiki Kaisha Toshiba Semiconductor memory device
KR102536261B1 (ko) 2015-12-18 2023-05-25 삼성전자주식회사 3차원 반도체 장치
US9767901B1 (en) * 2016-08-24 2017-09-19 Hewlett Packard Enterprise Development Lp Circuits having selector devices with different I-V responses
US10777566B2 (en) * 2017-11-10 2020-09-15 Macronix International Co., Ltd. 3D array arranged for memory and in-memory sum-of-products operations
CN111149206B (zh) * 2017-11-15 2023-08-18 桑迪士克科技有限责任公司 在平台区中具有加厚字线的三维存储器器件及其制造方法
US10461163B2 (en) 2017-11-15 2019-10-29 Sandisk Technologies Llc Three-dimensional memory device with thickened word lines in terrace region and method of making thereof
US10453854B2 (en) 2017-11-15 2019-10-22 Sandisk Technologies Llc Three-dimensional memory device with thickened word lines in terrace region
US11222695B2 (en) * 2019-11-15 2022-01-11 Micron Technology, Inc. Socket design for a memory device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITTO20021118A1 (it) * 2002-12-24 2004-06-25 St Microelectronics Srl Dispositivo mos e procedimento di fabbricazione di
JP5016832B2 (ja) * 2006-03-27 2012-09-05 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US7910973B2 (en) * 2008-03-17 2011-03-22 Kabushiki Kaisha Toshiba Semiconductor storage device
JP2010027870A (ja) * 2008-07-18 2010-02-04 Toshiba Corp 半導体記憶装置及びその製造方法
JP5380190B2 (ja) * 2009-07-21 2014-01-08 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
KR101559958B1 (ko) * 2009-12-18 2015-10-13 삼성전자주식회사 3차원 반도체 장치의 제조 방법 및 이에 따라 제조된 3차원 반도체 장치
JP2011211039A (ja) * 2010-03-30 2011-10-20 Toshiba Corp 記憶装置及びその製造方法
US8885382B2 (en) * 2012-06-29 2014-11-11 Intel Corporation Compact socket connection to cross-point array
JP2015056452A (ja) * 2013-09-10 2015-03-23 株式会社東芝 半導体記憶装置及びその製造方法

Also Published As

Publication number Publication date
US20170077399A1 (en) 2017-03-16
US9728722B2 (en) 2017-08-08
US20170288141A1 (en) 2017-10-05
US9935266B2 (en) 2018-04-03
US9515125B2 (en) 2016-12-06
JP2018513559A (ja) 2018-05-24
US20160315121A1 (en) 2016-10-27
WO2016170759A1 (en) 2016-10-27
KR20170141665A (ko) 2017-12-26

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