JP6732901B2 - 別個のワード線及び消去ゲートを有するフラッシュメモリを形成する方法 - Google Patents
別個のワード線及び消去ゲートを有するフラッシュメモリを形成する方法 Download PDFInfo
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- 229920005591 polysilicon Polymers 0.000 claims description 27
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- 230000001590 oxidative effect Effects 0.000 claims 7
- 239000012774 insulation material Substances 0.000 claims 4
- 239000010410 layer Substances 0.000 description 37
- 150000004767 nitrides Chemical class 0.000 description 22
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
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- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
本出願は、参照により本明細書に組み込まれる、2015年10月21日に出願された米国仮出願第62/244,688号の利益を主張するものである。
Claims (14)
- 不揮発性メモリセルを形成する方法であって、
第1の導電型の基板内に、第2の導電型の、離間した第1の領域及び第2の領域を形成することであって、それらの間にチャネル領域を画定する、ことと、
前記チャネル領域の第1の部分の上に配設されて、これから絶縁された浮遊ゲートを、前記第1の領域の部分の上に形成することであって、前記浮遊ゲートは、前記第1の領域の上に配設された鋭い縁を含む、ことと、
前記鋭い縁の周りにトンネル酸化物層を形成することと、
前記第1の領域の上に、これから絶縁された消去ゲートを形成することであって、前記消去ゲートは、前記鋭い縁に面するノッチを含み、前記ノッチは、前記トンネル酸化物層によって前記鋭い縁から絶縁されている、ことと、
前記第2の領域に隣接している前記チャネル領域の第2の部分の上に配設されて、これから絶縁されたワード線ゲートを形成することであって、前記ワード線ゲートの形成は、前記トンネル酸化物層の形成及び前記消去ゲートの形成の後に実行される、ことと、を含み、
前記浮遊ゲートを形成することは、
前記基板の上に、前記基板から絶縁された導電層を形成することと、
絶縁材のブロックを前記導電層上に形成することと、
前記導電層の平坦な上面を、前記導電層の上面が前記絶縁材のブロックに達する状態で前記導電層の上面を上方に傾斜させて、酸化させることと、を含む、方法。 - 前記基板の中に溝を形成することと、
前記溝を、前記溝から外に前記基板の表面の上に延在する第1の絶縁材によって充填することであって、前記溝の形成及び前記溝の充填は、前記導電層の形成の前に実行される、ことと、を更に含む、請求項1に記載の方法。 - 前記浮遊ゲートの形成が、
前記導電層及び前記第1の絶縁材の上面が平面であるように、前記酸化させることの前に、前記導電層の上面及び前記第1の絶縁材の上面に化学的機械的研磨を実行することと、
前記第1の絶縁材の上側部分を除去して第2の絶縁材で置換することと、を更に含む、請求項2に記載の方法。 - 前記酸化させることの後に、前記第2の絶縁材及び前記第1の絶縁材の上側部分をエッチング除去することを更に含む、請求項3に記載の方法。
- 前記浮遊ゲートの形成が、
前記酸化させることの前に、前記第1の絶縁材の上の前記導電層の部分を除去して第2の絶縁材で置換することを更に含む、請求項2に記載の方法。 - 前記酸化させることの後に、前記第2の絶縁材及び前記第1の絶縁材の上側部分をエッチング除去することを更に含む、請求項5に記載の方法。
- 前記浮遊ゲートの形成が、
前記酸化させることの前に、前記第1の絶縁材の上に配設された前記導電層の部分の上に絶縁材のブロックを形成することを更に含む、請求項2に記載の方法。 - 前記酸化させることの後に、前記絶縁材のブロックと、前記第1の絶縁材の上の前記導電層の部分と、前記第1の絶縁材の上側部分と、をエッチング除去することを更に含む、請求項7に記載の方法。
- 前記浮遊ゲートの形成が、
絶縁スペーサを前記消去ゲートの側壁に沿って、及び前記導電層の上に形成することと、
前記絶縁スペーサに隣接した前記導電層のエッチングを実行することと、を更に含む、請求項1に記載の方法。 - 前記ワード線ゲートの形成が、
前記チャネル領域の前記第2の部分の上に配設されて、これから絶縁された第1の部分、及び前記消去ゲートの上に配設されて、これから絶縁された第2の部分を有する第2の導電層を形成することと、
前記第2の導電層の前記第2の部分を除去することと、を含む、請求項1に記載の方法。 - 前記ワード線ゲートの形成が、
前記第2の導電層の前記第1の部分の上に絶縁スペーサを形成することと、
前記絶縁スペーサの下に配設されていない前記第2の導電層の前記第1の部分の部分を除去することと、を更に含む、請求項10に記載の方法。 - 前記第2の領域の形成が、前記ワード線ゲートの形成の後に実行される、請求項10に記載の方法。
- 前記ワード線ゲートの形成が、
前記基板の上にhigh−K絶縁層を形成することと、
前記high−K絶縁層の上に金属ブロックを形成することと、を含む、請求項1に記載の方法。 - 前記ワード線ゲートの形成が、
前記基板の上にhigh−K絶縁層を形成することと、
前記high−K絶縁層の上にポリシリコンブロックを形成することと、
前記ポリシリコンブロックを除去して金属ブロックで置換することと、を含む、請求項1に記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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US201562244688P | 2015-10-21 | 2015-10-21 | |
US62/244,688 | 2015-10-21 | ||
US15/290,960 | 2016-10-11 | ||
US15/290,960 US10141321B2 (en) | 2015-10-21 | 2016-10-11 | Method of forming flash memory with separate wordline and erase gates |
PCT/US2016/057101 WO2017070018A1 (en) | 2015-10-21 | 2016-10-14 | Method of forming flash memory with separate wordline and erase gates |
Publications (2)
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JP2018535547A JP2018535547A (ja) | 2018-11-29 |
JP6732901B2 true JP6732901B2 (ja) | 2020-07-29 |
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JP2018520125A Active JP6732901B2 (ja) | 2015-10-21 | 2016-10-14 | 別個のワード線及び消去ゲートを有するフラッシュメモリを形成する方法 |
Country Status (7)
Country | Link |
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US (1) | US10141321B2 (ja) |
EP (1) | EP3365894B1 (ja) |
JP (1) | JP6732901B2 (ja) |
KR (1) | KR102051766B1 (ja) |
CN (1) | CN108140414B (ja) |
TW (1) | TWI645544B (ja) |
WO (1) | WO2017070018A1 (ja) |
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CN108140414B (zh) | 2021-11-26 |
TWI645544B (zh) | 2018-12-21 |
KR20180074738A (ko) | 2018-07-03 |
EP3365894A4 (en) | 2019-09-18 |
TW201719821A (zh) | 2017-06-01 |
US20170117285A1 (en) | 2017-04-27 |
US10141321B2 (en) | 2018-11-27 |
WO2017070018A1 (en) | 2017-04-27 |
KR102051766B1 (ko) | 2019-12-03 |
EP3365894A1 (en) | 2018-08-29 |
JP2018535547A (ja) | 2018-11-29 |
EP3365894B1 (en) | 2022-05-18 |
CN108140414A (zh) | 2018-06-08 |
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