JP6669029B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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JP6669029B2
JP6669029B2 JP2016189179A JP2016189179A JP6669029B2 JP 6669029 B2 JP6669029 B2 JP 6669029B2 JP 2016189179 A JP2016189179 A JP 2016189179A JP 2016189179 A JP2016189179 A JP 2016189179A JP 6669029 B2 JP6669029 B2 JP 6669029B2
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semiconductor layer
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JP2018056257A (ja
JP2018056257A5 (https=
Inventor
隆弘 藤井
隆弘 藤井
正芳 小嵜
正芳 小嵜
隆樹 丹羽
隆樹 丹羽
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Toyoda Gosei Co Ltd
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    • H10D30/025Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
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    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
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    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/66Vertical DMOS [VDMOS] FETs
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    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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JP2016189179A 2016-09-28 2016-09-28 半導体装置の製造方法 Active JP6669029B2 (ja)

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JP2016189179A JP6669029B2 (ja) 2016-09-28 2016-09-28 半導体装置の製造方法
US15/697,261 US10083918B2 (en) 2016-09-28 2017-09-06 Manufacturing method of semiconductor device

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CN108962995A (zh) * 2018-07-17 2018-12-07 深圳大学 复合GaN基膜和MOSFET器件
CN112750890A (zh) * 2019-10-29 2021-05-04 季优科技(上海)有限公司 一种具有浮岛结构的沟槽型垂直氮化镓功率器件
JP7294098B2 (ja) * 2019-12-05 2023-06-20 豊田合成株式会社 p型III族窒化物半導体の製造方法
CN112186034A (zh) * 2020-10-22 2021-01-05 西安电子科技大学 一种带有斜场板结构的氮化镓肖特基二极管及其制作方法
JP7578525B2 (ja) * 2021-03-29 2024-11-06 株式会社デンソー 窒化物半導体装置の製造方法
JP7572309B2 (ja) * 2021-06-17 2024-10-23 株式会社デンソー 窒化物半導体装置の製造方法
JP7586776B2 (ja) * 2021-06-17 2024-11-19 株式会社デンソー 半導体装置とその製造方法

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JP3244980B2 (ja) 1995-01-06 2002-01-07 株式会社東芝 半導体素子の製造方法
US5656832A (en) 1994-03-09 1997-08-12 Kabushiki Kaisha Toshiba Semiconductor heterojunction device with ALN buffer layer of 3nm-10nm average film thickness
JP3948452B2 (ja) * 2003-11-04 2007-07-25 松下電器産業株式会社 荷重センサ及びその製造方法
JP2006032552A (ja) 2004-07-14 2006-02-02 Toshiba Corp 窒化物含有半導体装置
JP2007317794A (ja) * 2006-05-24 2007-12-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
US8823057B2 (en) * 2006-11-06 2014-09-02 Cree, Inc. Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
JP6260145B2 (ja) * 2013-08-27 2018-01-17 富士電機株式会社 半導体装置の製造方法
FR3026557B1 (fr) * 2014-09-26 2018-03-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de dopage d'un semi-conducteur a base de gan
FR3026558B1 (fr) * 2014-09-26 2018-03-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede d'activation de dopants dans une couche semi-conductrice a base de gan

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US20180090452A1 (en) 2018-03-29
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