JP6648743B2 - 炭化珪素半導体装置の製造方法 - Google Patents

炭化珪素半導体装置の製造方法 Download PDF

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JP6648743B2
JP6648743B2 JP2017179442A JP2017179442A JP6648743B2 JP 6648743 B2 JP6648743 B2 JP 6648743B2 JP 2017179442 A JP2017179442 A JP 2017179442A JP 2017179442 A JP2017179442 A JP 2017179442A JP 6648743 B2 JP6648743 B2 JP 6648743B2
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layer
silicon carbide
type
trench
forming
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JP2018061023A (ja
JP2018061023A5 (https=
Inventor
茂行 高木
茂行 高木
下村　正樹
正樹 下村
竹内　有一
有一 竹内
鈴木　克己
克己 鈴木
佐智子 青井
佐智子 青井
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Denso Corp
Toyota Motor Corp
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Denso Corp
Toyota Motor Corp
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Priority to PCT/JP2017/036349 priority Critical patent/WO2018066662A1/ja
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Publication of JP2018061023A5 publication Critical patent/JP2018061023A5/ja
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    • H—ELECTRICITY
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    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
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    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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    • H10D8/051—Manufacture or treatment of Schottky diodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H—ELECTRICITY
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    • H10P50/00—Etching of wafers, substrates or parts of devices
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    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
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    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment

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  • Recrystallisation Techniques (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
JP2017179442A 2016-10-05 2017-09-19 炭化珪素半導体装置の製造方法 Active JP6648743B2 (ja)

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Application Number Priority Date Filing Date Title
PCT/JP2017/036349 WO2018066662A1 (ja) 2016-10-05 2017-10-05 炭化珪素半導体装置の製造方法
US16/353,670 US10748780B2 (en) 2016-10-05 2019-03-14 Manufacturing method of silicon carbide semiconductor device

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JP2016197414 2016-10-05
JP2016197414 2016-10-05

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JP7140148B2 (ja) * 2019-02-27 2022-09-21 株式会社デンソー 炭化珪素半導体装置およびその製造方法

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JPH08167587A (ja) * 1994-12-12 1996-06-25 Yamaha Corp 半導体ウェハの平坦化法
JP3180895B2 (ja) * 1997-08-18 2001-06-25 富士電機株式会社 炭化けい素半導体装置の製造方法
JP3804375B2 (ja) 1999-12-09 2006-08-02 株式会社日立製作所 半導体装置とそれを用いたパワースイッチング駆動システム
JP4862254B2 (ja) * 2004-09-28 2012-01-25 日産自動車株式会社 半導体装置の製造方法
US7554137B2 (en) * 2005-10-25 2009-06-30 Infineon Technologies Austria Ag Power semiconductor component with charge compensation structure and method for the fabrication thereof
US7595241B2 (en) * 2006-08-23 2009-09-29 General Electric Company Method for fabricating silicon carbide vertical MOSFET devices
US20080292991A1 (en) * 2007-05-24 2008-11-27 Advanced Micro Devices, Inc. High fidelity multiple resist patterning
JP4732423B2 (ja) 2007-11-13 2011-07-27 株式会社デンソー 炭化珪素半導体装置の製造方法
JP4924440B2 (ja) * 2008-01-14 2012-04-25 株式会社デンソー 炭化珪素半導体装置の製造方法
JP2010135552A (ja) * 2008-12-04 2010-06-17 Mitsubishi Electric Corp 炭化珪素半導体装置の製造方法
JP5811977B2 (ja) * 2012-09-18 2015-11-11 株式会社デンソー 炭化珪素半導体装置
JP6126833B2 (ja) * 2012-12-18 2017-05-10 昭和電工株式会社 ＳｉＣ基板の製造方法
JP6048317B2 (ja) * 2013-06-05 2016-12-21 株式会社デンソー 炭化珪素半導体装置

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US20190214264A1 (en) 2019-07-11
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