JP6566430B2 - 基板処理方法 - Google Patents

基板処理方法 Download PDF

Info

Publication number
JP6566430B2
JP6566430B2 JP2017507853A JP2017507853A JP6566430B2 JP 6566430 B2 JP6566430 B2 JP 6566430B2 JP 2017507853 A JP2017507853 A JP 2017507853A JP 2017507853 A JP2017507853 A JP 2017507853A JP 6566430 B2 JP6566430 B2 JP 6566430B2
Authority
JP
Japan
Prior art keywords
substrate
fluorine
layer
based layer
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017507853A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017526181A (ja
JP2017526181A5 (enExample
Inventor
エヌ． タピリー，カンダバラ
エヌ． タピリー，カンダバラ
文貴 天野
文貴 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of JP2017526181A publication Critical patent/JP2017526181A/ja
Publication of JP2017526181A5 publication Critical patent/JP2017526181A5/ja
Application granted granted Critical
Publication of JP6566430B2 publication Critical patent/JP6566430B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H10P50/283—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D64/01352—
    • H10D64/01356—
    • H10P14/6319—
    • H10P14/6529—
    • H10P50/00—
    • H10P50/285—
    • H10P70/23—
    • H10P95/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Plasma & Fusion (AREA)
  • Analytical Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
JP2017507853A 2014-08-12 2015-08-11 基板処理方法 Active JP6566430B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201462036474P 2014-08-12 2014-08-12
US62/036,474 2014-08-12
PCT/US2015/044623 WO2016025462A1 (en) 2014-08-12 2015-08-11 Substrate processing method

Publications (3)

Publication Number Publication Date
JP2017526181A JP2017526181A (ja) 2017-09-07
JP2017526181A5 JP2017526181A5 (enExample) 2018-09-06
JP6566430B2 true JP6566430B2 (ja) 2019-08-28

Family

ID=55302680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017507853A Active JP6566430B2 (ja) 2014-08-12 2015-08-11 基板処理方法

Country Status (5)

Country Link
US (1) US9558962B2 (enExample)
JP (1) JP6566430B2 (enExample)
KR (1) KR102396247B1 (enExample)
TW (1) TWI587389B (enExample)
WO (1) WO2016025462A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101790206B1 (ko) 2010-10-05 2017-10-25 실코텍 코포레이션 내마모성 코팅, 물건 및 방법
US20150118416A1 (en) * 2013-10-31 2015-04-30 Semes Co., Ltd. Substrate treating apparatus and method
JP6426489B2 (ja) * 2015-02-03 2018-11-21 東京エレクトロン株式会社 エッチング方法
US10276469B2 (en) * 2015-04-17 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming semiconductor device structure
WO2017040623A1 (en) 2015-09-01 2017-03-09 Silcotek Corp. Thermal chemical vapor deposition coating
US20170283943A1 (en) 2016-03-29 2017-10-05 Silcotek Corp. Treated article, system having treated article, and process incorporating treated article
US10580658B2 (en) * 2016-04-13 2020-03-03 Tokyo Electron Limited Method for preferential oxidation of silicon in substrates containing silicon and germanium
JP6742165B2 (ja) * 2016-06-14 2020-08-19 東京エレクトロン株式会社 窒化珪素膜の処理方法および窒化珪素膜の形成方法
US10707152B2 (en) * 2017-01-16 2020-07-07 Innolux Corporation High-frequency device and manufacturing method thereof
US11161324B2 (en) 2017-09-13 2021-11-02 Silcotek Corp. Corrosion-resistant coated article and thermal chemical vapor deposition coating process
US11388809B2 (en) * 2019-03-25 2022-07-12 Recarbon, Inc. Systems for controlling plasma reactors
WO2020252306A1 (en) 2019-06-14 2020-12-17 Silcotek Corp. Nano-wire growth
US12473635B2 (en) 2020-06-03 2025-11-18 Silcotek Corp. Dielectric article
JP2022112654A (ja) * 2021-01-22 2022-08-03 東京エレクトロン株式会社 接合システムおよび接合方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313042B1 (en) * 1999-09-03 2001-11-06 Applied Materials, Inc. Cleaning contact with successive fluorine and hydrogen plasmas
US6579812B2 (en) 2001-05-22 2003-06-17 Macronix International Co Ltd. Method for removing residual polymer after the dry etching process and reducing oxide loss
US6872323B1 (en) * 2001-11-01 2005-03-29 Novellus Systems, Inc. In situ plasma process to remove fluorine residues from the interior surfaces of a CVD reactor
US6746970B2 (en) 2002-06-24 2004-06-08 Macronix International Co., Ltd. Method of forming a fluorocarbon polymer film on a substrate using a passivation layer
US20050045206A1 (en) * 2003-08-26 2005-03-03 Smith Patricia Beauregard Post-etch clean process for porous low dielectric constant materials
US7977244B2 (en) * 2006-12-18 2011-07-12 United Microelectronics Corp. Semiconductor manufacturing process
JP5084250B2 (ja) * 2006-12-26 2012-11-28 東京エレクトロン株式会社 ガス処理装置およびガス処理方法ならびに記憶媒体
JP5374039B2 (ja) 2007-12-27 2013-12-25 東京エレクトロン株式会社 基板処理方法、基板処理装置及び記憶媒体
US8133797B2 (en) * 2008-05-16 2012-03-13 Novellus Systems, Inc. Protective layer to enable damage free gap fill
JP5508701B2 (ja) * 2008-08-28 2014-06-04 岩谷産業株式会社 半導体処理装置及び処理方法
JP5492574B2 (ja) * 2010-01-08 2014-05-14 東京エレクトロン株式会社 基板のクリーニング方法及び基板のクリーニング装置
US20120273861A1 (en) 2011-04-29 2012-11-01 Shanghan Institute Of Microsystem And Imformation Technology,Chinese Academ Method of depositing gate dielectric, method of preparing mis capacitor, and mis capacitor
US20130012012A1 (en) 2011-07-10 2013-01-10 Chien-Liang Lin Semiconductor process
US8679982B2 (en) * 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8679983B2 (en) * 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen

Also Published As

Publication number Publication date
KR20170042315A (ko) 2017-04-18
WO2016025462A9 (en) 2016-04-07
WO2016025462A1 (en) 2016-02-18
JP2017526181A (ja) 2017-09-07
KR102396247B1 (ko) 2022-05-09
US20160049309A1 (en) 2016-02-18
US9558962B2 (en) 2017-01-31
TWI587389B (zh) 2017-06-11
TW201614728A (en) 2016-04-16

Similar Documents

Publication Publication Date Title
JP6566430B2 (ja) 基板処理方法
US8021987B2 (en) Method of modifying insulating film
KR101938441B1 (ko) 반도체 디바이스의 형성 방법
KR101163264B1 (ko) 플라즈마 프로세싱을 사용하여 하이-ｋ 층을 포함하는 게이트 유전체 스택을 변형하는 방법
KR102396835B1 (ko) 마이크로파 플라즈마에 의한 나노와이어의 모서리 라운딩 및 트리밍 방법
TWI618152B (zh) 基板上三維結構之層的含氨電漿氮化
JP5042038B2 (ja) 半導体装置を製造する方法
KR102083036B1 (ko) 수소 플라즈마를 사용하여 반도체 상에 계면층을 형성하는 방법
KR100966927B1 (ko) 절연막의 제조 방법 및 반도체 장치의 제조 방법
KR102003058B1 (ko) 피처리 기체의 처리 방법
TWI621218B (zh) 包含鍺之半導體元件及其形成方法
TWI903529B (zh) 在基板上製造記憶體單元裝置的方法
JP2016225356A (ja) 半導体素子の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180730

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180730

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190305

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190527

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190625

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20190723

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190723

R150 Certificate of patent or registration of utility model

Ref document number: 6566430

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250