JP6542263B2 - 低グリッチノイズのセグメント型dac用のハイブリッドr−2r構造 - Google Patents

低グリッチノイズのセグメント型dac用のハイブリッドr−2r構造 Download PDF

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JP6542263B2
JP6542263B2 JP2016569747A JP2016569747A JP6542263B2 JP 6542263 B2 JP6542263 B2 JP 6542263B2 JP 2016569747 A JP2016569747 A JP 2016569747A JP 2016569747 A JP2016569747 A JP 2016569747A JP 6542263 B2 JP6542263 B2 JP 6542263B2
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stages
dac
current
resistive
bit
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Japanese (ja)
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JP2017520172A5 (https=
JP2017520172A (ja
Inventor
リ、サン・ミン
セオ、ドンウォン
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Qualcomm Inc
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Qualcomm Inc
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0863Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0612Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic over the full range of the converter, e.g. for correcting differential non-linearity
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0863Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
    • H03M1/0881Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches by forcing a gradual change from one output level to the next, e.g. soft-start
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/68Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H03M1/687Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/78Simultaneous conversion using ladder network
    • H03M1/785Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Analogue/Digital Conversion (AREA)
JP2016569747A 2014-05-27 2015-05-06 低グリッチノイズのセグメント型dac用のハイブリッドr−2r構造 Expired - Fee Related JP6542263B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201462003497P 2014-05-27 2014-05-27
US62/003,497 2014-05-27
US14/493,254 2014-09-22
US14/493,254 US9178524B1 (en) 2014-05-27 2014-09-22 Hybrid R-2R structure for low glitch noise segmented DAC
PCT/US2015/029535 WO2015183496A1 (en) 2014-05-27 2015-05-06 Hybrid r-2r structure for low glitch noise segmented dac

Publications (3)

Publication Number Publication Date
JP2017520172A JP2017520172A (ja) 2017-07-20
JP2017520172A5 JP2017520172A5 (https=) 2018-05-31
JP6542263B2 true JP6542263B2 (ja) 2019-07-10

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JP2016569747A Expired - Fee Related JP6542263B2 (ja) 2014-05-27 2015-05-06 低グリッチノイズのセグメント型dac用のハイブリッドr−2r構造

Country Status (6)

Country Link
US (1) US9178524B1 (https=)
EP (1) EP3149858A1 (https=)
JP (1) JP6542263B2 (https=)
KR (1) KR20170009874A (https=)
CN (1) CN106688184A (https=)
WO (1) WO2015183496A1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170083222A (ko) * 2016-01-08 2017-07-18 삼성전자주식회사 헤드폰 드라이버 및 이를 포함하는 사운드 프로세서
US10200055B2 (en) * 2017-01-11 2019-02-05 Analog Devices Global Glitch characterization in digital-to-analog conversion
EP3616322B1 (en) * 2017-04-25 2026-03-18 Telefonaktiebolaget LM Ericsson (PUBL) Digital-to-analog conversion circuit
CN110663188B (zh) * 2017-06-21 2023-04-04 德州仪器公司 分段式数/模转换器
US10014877B1 (en) * 2017-09-01 2018-07-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Multi-segmented all logic DAC
CN111434041B (zh) 2017-12-21 2024-08-16 德州仪器公司 内插数/模转换器(dac)
CN110557123A (zh) 2018-06-04 2019-12-10 恩智浦美国有限公司 分段式电阻型数模转换器
US10447292B1 (en) 2018-08-27 2019-10-15 Qualcomm Incorporated Multiple-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuits
US10425095B1 (en) 2018-08-27 2019-09-24 Qualcomm Incorporated Multiple-bit parallel successive approximation (SA) flash analog-to-digital converter (ADC) circuits
US10454487B1 (en) 2018-08-30 2019-10-22 Qualcomm Incorporated Segmented resistor architecture for digital-to-analog converters
US10333544B1 (en) 2018-09-19 2019-06-25 Qualcomm Incorporated Digital-to-analog converter (DAC) circuits employing resistor rotator circuits configured to be included in analog-to-digital converter (ADC) circuits
CN110380692B (zh) * 2019-06-28 2020-11-24 上海类比半导体技术有限公司 一种差分放大器的修调电路
US10756744B1 (en) * 2019-07-18 2020-08-25 Apple Inc. Linearity improvement for segmented R-DACs
US11791832B2 (en) * 2022-01-18 2023-10-17 Nxp B.V. Timing calibration technique for radio frequency digital-to-analog converter

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245718A (ja) * 1985-04-24 1986-11-01 Iwatsu Electric Co Ltd デイジタル−アナログ変換器
JPS6294024A (ja) * 1985-10-21 1987-04-30 Toshiba Corp C−r型d/a変換器
JPH0377430A (ja) * 1989-08-19 1991-04-03 Fujitsu Ltd D/aコンバータ
JP3335820B2 (ja) * 1995-11-14 2002-10-21 川崎マイクロエレクトロニクス株式会社 Daコンバータ
JPH10112654A (ja) * 1996-10-07 1998-04-28 Toshiba Corp 電流セグメント方式ディジタル・アナログ変換器
JPH10135836A (ja) * 1996-10-29 1998-05-22 Sanyo Electric Co Ltd D/a変換器
US6633248B2 (en) 2001-05-29 2003-10-14 Intel Corporation Converting digital signals to analog signals
US6583744B2 (en) * 2001-06-22 2003-06-24 Texas Instruments Incorporated Correction circuit for beta mismatch between thermometer encoded and R-2R ladder segments of a current steering DAC
US6924761B2 (en) * 2003-06-19 2005-08-02 Intel Corporation Differential digital-to-analog converter
US7042381B1 (en) 2004-10-29 2006-05-09 Broadcom Corporation Delay equalized Z/2Z ladder for digital to analog conversion
US7679538B2 (en) * 2005-08-12 2010-03-16 Tsang Robin M Current-steering type digital-to-analog converter
US7283082B1 (en) 2006-06-16 2007-10-16 Texas Instruments Incorporated High-speed, high-resolution voltage output digital-to-analog converter and method
EP2019490B1 (en) 2007-07-27 2018-07-18 Socionext Inc. Segmented circuitry
JP2010004422A (ja) * 2008-06-23 2010-01-07 Sharp Corp D/a変換回路
US8984035B2 (en) 2009-01-28 2015-03-17 Ess Technology, Inc. Channel select filter apparatus and method
US7812665B2 (en) 2009-02-23 2010-10-12 Number 14 B.V. Amplifiers with input offset trim and methods
US8089380B2 (en) * 2009-08-17 2012-01-03 Analog Devices, Inc. Voltage mode DAC with calibration circuit using current mode DAC and ROM lookup
US8169353B2 (en) * 2009-09-30 2012-05-01 Qualcomm, Incorporated Wideband digital to analog converter with built-in load attenuator
JP2012050004A (ja) * 2010-08-30 2012-03-08 Renesas Electronics Corp Da変換器
US8330634B2 (en) * 2011-02-08 2012-12-11 Maxim Integrated Products, Inc. Precision sub-radix2 DAC with linearity calibration
US8941522B2 (en) 2012-05-04 2015-01-27 Analog Devices Technology Segmented digital-to-analog converter having weighted current sources
US8896472B2 (en) * 2013-03-08 2014-11-25 Qualcomm Incorporated Low glitch-noise DAC

Also Published As

Publication number Publication date
KR20170009874A (ko) 2017-01-25
WO2015183496A1 (en) 2015-12-03
EP3149858A1 (en) 2017-04-05
US9178524B1 (en) 2015-11-03
JP2017520172A (ja) 2017-07-20
CN106688184A (zh) 2017-05-17

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