JP2017520172A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2017520172A5 JP2017520172A5 JP2016569747A JP2016569747A JP2017520172A5 JP 2017520172 A5 JP2017520172 A5 JP 2017520172A5 JP 2016569747 A JP2016569747 A JP 2016569747A JP 2016569747 A JP2016569747 A JP 2016569747A JP 2017520172 A5 JP2017520172 A5 JP 2017520172A5
- Authority
- JP
- Japan
- Prior art keywords
- stages
- dac
- current
- stage
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201462003497P | 2014-05-27 | 2014-05-27 | |
| US62/003,497 | 2014-05-27 | ||
| US14/493,254 | 2014-09-22 | ||
| US14/493,254 US9178524B1 (en) | 2014-05-27 | 2014-09-22 | Hybrid R-2R structure for low glitch noise segmented DAC |
| PCT/US2015/029535 WO2015183496A1 (en) | 2014-05-27 | 2015-05-06 | Hybrid r-2r structure for low glitch noise segmented dac |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017520172A JP2017520172A (ja) | 2017-07-20 |
| JP2017520172A5 true JP2017520172A5 (https=) | 2018-05-31 |
| JP6542263B2 JP6542263B2 (ja) | 2019-07-10 |
Family
ID=54352833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016569747A Expired - Fee Related JP6542263B2 (ja) | 2014-05-27 | 2015-05-06 | 低グリッチノイズのセグメント型dac用のハイブリッドr−2r構造 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9178524B1 (https=) |
| EP (1) | EP3149858A1 (https=) |
| JP (1) | JP6542263B2 (https=) |
| KR (1) | KR20170009874A (https=) |
| CN (1) | CN106688184A (https=) |
| WO (1) | WO2015183496A1 (https=) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170083222A (ko) * | 2016-01-08 | 2017-07-18 | 삼성전자주식회사 | 헤드폰 드라이버 및 이를 포함하는 사운드 프로세서 |
| US10200055B2 (en) * | 2017-01-11 | 2019-02-05 | Analog Devices Global | Glitch characterization in digital-to-analog conversion |
| EP3616322B1 (en) * | 2017-04-25 | 2026-03-18 | Telefonaktiebolaget LM Ericsson (PUBL) | Digital-to-analog conversion circuit |
| CN110663188B (zh) * | 2017-06-21 | 2023-04-04 | 德州仪器公司 | 分段式数/模转换器 |
| US10014877B1 (en) * | 2017-09-01 | 2018-07-03 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Multi-segmented all logic DAC |
| CN111434041B (zh) | 2017-12-21 | 2024-08-16 | 德州仪器公司 | 内插数/模转换器(dac) |
| CN110557123A (zh) | 2018-06-04 | 2019-12-10 | 恩智浦美国有限公司 | 分段式电阻型数模转换器 |
| US10447292B1 (en) | 2018-08-27 | 2019-10-15 | Qualcomm Incorporated | Multiple-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuits |
| US10425095B1 (en) | 2018-08-27 | 2019-09-24 | Qualcomm Incorporated | Multiple-bit parallel successive approximation (SA) flash analog-to-digital converter (ADC) circuits |
| US10454487B1 (en) | 2018-08-30 | 2019-10-22 | Qualcomm Incorporated | Segmented resistor architecture for digital-to-analog converters |
| US10333544B1 (en) | 2018-09-19 | 2019-06-25 | Qualcomm Incorporated | Digital-to-analog converter (DAC) circuits employing resistor rotator circuits configured to be included in analog-to-digital converter (ADC) circuits |
| CN110380692B (zh) * | 2019-06-28 | 2020-11-24 | 上海类比半导体技术有限公司 | 一种差分放大器的修调电路 |
| US10756744B1 (en) * | 2019-07-18 | 2020-08-25 | Apple Inc. | Linearity improvement for segmented R-DACs |
| US11791832B2 (en) * | 2022-01-18 | 2023-10-17 | Nxp B.V. | Timing calibration technique for radio frequency digital-to-analog converter |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61245718A (ja) * | 1985-04-24 | 1986-11-01 | Iwatsu Electric Co Ltd | デイジタル−アナログ変換器 |
| JPS6294024A (ja) * | 1985-10-21 | 1987-04-30 | Toshiba Corp | C−r型d/a変換器 |
| JPH0377430A (ja) * | 1989-08-19 | 1991-04-03 | Fujitsu Ltd | D/aコンバータ |
| JP3335820B2 (ja) * | 1995-11-14 | 2002-10-21 | 川崎マイクロエレクトロニクス株式会社 | Daコンバータ |
| JPH10112654A (ja) * | 1996-10-07 | 1998-04-28 | Toshiba Corp | 電流セグメント方式ディジタル・アナログ変換器 |
| JPH10135836A (ja) * | 1996-10-29 | 1998-05-22 | Sanyo Electric Co Ltd | D/a変換器 |
| US6633248B2 (en) | 2001-05-29 | 2003-10-14 | Intel Corporation | Converting digital signals to analog signals |
| US6583744B2 (en) * | 2001-06-22 | 2003-06-24 | Texas Instruments Incorporated | Correction circuit for beta mismatch between thermometer encoded and R-2R ladder segments of a current steering DAC |
| US6924761B2 (en) * | 2003-06-19 | 2005-08-02 | Intel Corporation | Differential digital-to-analog converter |
| US7042381B1 (en) | 2004-10-29 | 2006-05-09 | Broadcom Corporation | Delay equalized Z/2Z ladder for digital to analog conversion |
| US7679538B2 (en) * | 2005-08-12 | 2010-03-16 | Tsang Robin M | Current-steering type digital-to-analog converter |
| US7283082B1 (en) | 2006-06-16 | 2007-10-16 | Texas Instruments Incorporated | High-speed, high-resolution voltage output digital-to-analog converter and method |
| EP2019490B1 (en) | 2007-07-27 | 2018-07-18 | Socionext Inc. | Segmented circuitry |
| JP2010004422A (ja) * | 2008-06-23 | 2010-01-07 | Sharp Corp | D/a変換回路 |
| US8984035B2 (en) | 2009-01-28 | 2015-03-17 | Ess Technology, Inc. | Channel select filter apparatus and method |
| US7812665B2 (en) | 2009-02-23 | 2010-10-12 | Number 14 B.V. | Amplifiers with input offset trim and methods |
| US8089380B2 (en) * | 2009-08-17 | 2012-01-03 | Analog Devices, Inc. | Voltage mode DAC with calibration circuit using current mode DAC and ROM lookup |
| US8169353B2 (en) * | 2009-09-30 | 2012-05-01 | Qualcomm, Incorporated | Wideband digital to analog converter with built-in load attenuator |
| JP2012050004A (ja) * | 2010-08-30 | 2012-03-08 | Renesas Electronics Corp | Da変換器 |
| US8330634B2 (en) * | 2011-02-08 | 2012-12-11 | Maxim Integrated Products, Inc. | Precision sub-radix2 DAC with linearity calibration |
| US8941522B2 (en) | 2012-05-04 | 2015-01-27 | Analog Devices Technology | Segmented digital-to-analog converter having weighted current sources |
| US8896472B2 (en) * | 2013-03-08 | 2014-11-25 | Qualcomm Incorporated | Low glitch-noise DAC |
-
2014
- 2014-09-22 US US14/493,254 patent/US9178524B1/en active Active
-
2015
- 2015-05-06 CN CN201580026954.2A patent/CN106688184A/zh active Pending
- 2015-05-06 WO PCT/US2015/029535 patent/WO2015183496A1/en not_active Ceased
- 2015-05-06 KR KR1020167032805A patent/KR20170009874A/ko not_active Withdrawn
- 2015-05-06 EP EP15722019.5A patent/EP3149858A1/en not_active Withdrawn
- 2015-05-06 JP JP2016569747A patent/JP6542263B2/ja not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2017520172A5 (https=) | ||
| JP2017103783A5 (https=) | ||
| CN108370484B (zh) | 用于超声装置的跨阻放大器以及相关装置和方法 | |
| EP3399650B1 (en) | Multiple string, multiple output digital to analog converter | |
| CN101207385B (zh) | 数模转换器及其数模转换方法 | |
| CN105009457B (zh) | 低毛刺噪声dac | |
| US9698813B2 (en) | Input buffer and analog-to-digital converter | |
| EP3335315A1 (en) | Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages | |
| US20160211858A1 (en) | Hybrid pipelined analog-to-digital converter | |
| JP2009194558A (ja) | カレントミラー回路及びデジタルアナログ変換回路 | |
| KR20140032001A (ko) | 가중된 저항 소자들을 갖는 디지털-아날로그 컨버터 회로부 | |
| JP2006314197A5 (https=) | ||
| TW516269B (en) | Ultra low voltage CMOS class AB power amplifier with parasitic capacitance internal compensation | |
| JP6749969B2 (ja) | 多重ストリングの多重出力デジタル−アナログ変換器 | |
| JP2024073532A (ja) | 増幅器フリッカノイズ及びオフセットを緩和するシステム及び方法 | |
| US10379693B2 (en) | Current output circuit | |
| JP2015523821A5 (https=) | ||
| WO2008029778A1 (fr) | Circuit de repliement et convertisseur analogique à numérique | |
| JP2009105578A (ja) | 直並列型アナログ/デジタル変換器及びアナログ/デジタル変換方法 | |
| US9705524B2 (en) | R2R digital-to-analog converter circuit | |
| JP2016072719A (ja) | 送信回路および半導体集積回路 | |
| JPWO2023119866A5 (https=) | ||
| JP2015517774A5 (https=) | ||
| Norden et al. | Age-related impairments in the dynamic regulation of active microglia by astrocytes | |
| Ghasemzadeh et al. | A new background continuous‐time offset cancelation and gain calibration strategy for open‐loop residue amplifiers in high‐speed and high‐resolution ADC's |