JP6530777B2 - 消去およびプログラム可能な不揮発性メモリ - Google Patents
消去およびプログラム可能な不揮発性メモリ Download PDFInfo
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- JP6530777B2 JP6530777B2 JP2017079027A JP2017079027A JP6530777B2 JP 6530777 B2 JP6530777 B2 JP 6530777B2 JP 2017079027 A JP2017079027 A JP 2017079027A JP 2017079027 A JP2017079027 A JP 2017079027A JP 6530777 B2 JP6530777 B2 JP 6530777B2
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- 239000002184 metal Substances 0.000 claims description 27
- 239000003990 capacitor Substances 0.000 claims description 16
- 239000000969 carrier Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 22
- 238000000034 method Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- G06F7/588—Random number generators, i.e. based on natural stochastic processes
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
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- G11C16/10—Programming or data input circuits
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Description
Claims (14)
- 消去およびプログラム可能な不揮発性メモリであって、
選択ゲートと、第1のドープ領域と、第2のドープ領域とを含み、前記選択ゲートがワード線に接続され、前記第1のドープ領域がソース線に接続される第1のトランジスタと、
第2のドープ領域と、第3のドープ領域と、フローティングゲートとを含み、前記第3のドープ領域がビット線に接続される第2のトランジスタと、
消去線に接続される消去ゲート領域であって、前記フローティングゲートが前記消去ゲート領域上に延在し、前記消去ゲート領域の近くに位置する消去ゲート領域と、
前記フローティングゲート上に配置される金属層であって、前記ビット線と前記フローティングゲートとの間に形成され、ビアを介して前記ビット線に接続される金属層とを備える、消去およびプログラム可能な不揮発性メモリ。 - 前記第1のトランジスタおよび前記第2のトランジスタはn型トランジスタであり、前記第1のドープ領域、前記第2のドープ領域および前記第3ドープ領域はn型ドープ領域である、請求項1に記載の消去およびプログラム可能な不揮発性メモリ。
- 前記第1のトランジスタおよび前記第2のトランジスタはpウェル領域内に構成され、前記pウェルはp型基板内に形成される、請求項2に記載の消去およびプログラム可能な不揮発性メモリ。
- 前記第1のトランジスタおよび前記第2のトランジスタがpウェル領域内に構成され、さらに前記pウェルおよびp型基板の間に深いnウェル領域を含む、請求項2に記載の消去およびプログラム可能な不揮発性メモリ。
- 前記第1のトランジスタおよび前記第2のトランジスタはpウェル領域内に構成され、プログラムサイクル中に、第1の電圧が前記pウェル領域および前記ソース線に供給され、プログラム電圧が前記ビット線および前記消去線に供給され、オン電圧がワード線に供給されることで、複数の電子が前記フローティングゲートに注入される、請求項2に記載の消去およびプログラム可能な不揮発性メモリ。
- 前記第1のトランジスタおよび前記第2のトランジスタはpウェル領域内に構成され、消去サイクル中に、第1の電圧が前記pウェル領域、前記ソース線および前記ビット線に供給され、消去電圧が前記消去線に供給され、オフ電圧が前記ワード線に供給されることで、複数の電子が前記フローティングゲートから放出される、請求項2に記載の消去およびプログラム可能な不揮発性メモリ。
- 前記第1のトランジスタおよび前記第2のトランジスタはpウェル領域内に構成され、読み出しサイクル中に、第1の電圧が前記pウェル領域、前記ソース線および前記消去線に供給され、読み出し電圧が前記ビット線に供給され、オン電圧が前記ワード線に供給されることで、読み出し電流が前記ソース線に流れる、請求項2に記載の消去およびプログラム可能な不揮発性メモリ。
- 前記フローティングゲートの第1の部分が、前記消去ゲート領域の上に重なって配置され、前記フローティングゲートの第2の部分が、前記第2のトランジスタのチャネル領域の上に重なって配置され、前記第2の部分の面積に対する前記第1の部分の面積の比が、1/4〜2/3の範囲にある、請求項1に記載の消去およびプログラム可能な不揮発性メモリ。
- 前記金属層の面積が、前記フローティングゲートの面積よりも大きい、請求項1に記載の消去およびプログラム可能な不揮発性メモリ。
- 選択トランジスタと、フローティングゲートトランジスタと、第1のキャパシタと、第2のキャパシタと、金属層とを備える、消去およびプログラム可能な不揮発性メモリであって、
前記選択トランジスタのゲート端子がワード線に接続され、前記選択トランジスタの第1のドレイン/ソース端子がソース線に接続され、
前記フローティングゲートトランジスタの第1のドレイン/ソース端子が前記選択トランジスタの第2のドレイン/ソース端子に接続され、前記フローティングゲートトランジスタの第2のドレイン/ソース端子がビット線に接続され、前記フローティングゲートトランジスタはフローティングゲートを含み、
前記第1のキャパシタが前記フローティングゲートと消去線との間に接続され、
前記金属層と前記フローティングゲートとは協同して前記第2のキャパシタとして形成され、前記ビット線は、ビアを介して前記金属層と接続される、
消去およびプログラム可能な不揮発性メモリ。 - 前記選択トランジスタおよび前記フローティングゲートトランジスタがn型トランジスタであり、前記選択トランジスタおよび前記フローティングゲートトランジスタがpウェル領域内に構成される、請求項10に記載の消去およびプログラム可能な不揮発性メモリ。
- プログラムサイクル中に、第1の電圧が前記pウェル領域および前記ソース線に供給され、プログラム電圧が前記ビット線および前記消去線に供給され、オン電圧が前記ワード線に供給されることで、複数のホットキャリアが前記フローティングゲートに注入される、請求項11に記載の消去およびプログラム可能な不揮発性メモリ。
- 消去サイクル中に、第1の電圧が前記pウェル領域、前記ソース線および前記ビット線に供給され、消去電圧が前記消去線に供給され、オフ電圧が前記ワード線に供給されることで、複数の電子が前記フローティングゲートから放出される、請求項11に記載の消去およびプログラム可能な不揮発性メモリ。
- 読み出しサイクル中に、第1の電圧が前記pウェル領域、前記ソース線および前記消去線に供給され、読み出し電圧が前記ビット線に供給され、オン電圧がワード線に供給されることで、読み出し電流が前記ソース線に流れる、請求項11に記載の消去およびプログラム可能な不揮発性メモリ。
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