JP6505540B2 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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Publication number
JP6505540B2
JP6505540B2 JP2015147882A JP2015147882A JP6505540B2 JP 6505540 B2 JP6505540 B2 JP 6505540B2 JP 2015147882 A JP2015147882 A JP 2015147882A JP 2015147882 A JP2015147882 A JP 2015147882A JP 6505540 B2 JP6505540 B2 JP 6505540B2
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Japan
Prior art keywords
lead frame
resin layer
lead
semiconductor device
opening
Prior art date
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JP2015147882A
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English (en)
Japanese (ja)
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JP2017028200A5 (enExample
JP2017028200A (ja
Inventor
真太郎 林
真太郎 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to JP2015147882A priority Critical patent/JP6505540B2/ja
Publication of JP2017028200A publication Critical patent/JP2017028200A/ja
Publication of JP2017028200A5 publication Critical patent/JP2017028200A5/ja
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2015147882A 2015-07-27 2015-07-27 半導体装置及び半導体装置の製造方法 Active JP6505540B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015147882A JP6505540B2 (ja) 2015-07-27 2015-07-27 半導体装置及び半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015147882A JP6505540B2 (ja) 2015-07-27 2015-07-27 半導体装置及び半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2017028200A JP2017028200A (ja) 2017-02-02
JP2017028200A5 JP2017028200A5 (enExample) 2018-04-26
JP6505540B2 true JP6505540B2 (ja) 2019-04-24

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JP2015147882A Active JP6505540B2 (ja) 2015-07-27 2015-07-27 半導体装置及び半導体装置の製造方法

Country Status (1)

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JP (1) JP6505540B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6909629B2 (ja) * 2017-05-10 2021-07-28 ローム株式会社 半導体装置
JP7022541B2 (ja) * 2017-09-11 2022-02-18 ローム株式会社 半導体装置
JP2019110278A (ja) * 2017-12-20 2019-07-04 株式会社デンソー 半導体装置
TWI737505B (zh) * 2020-09-29 2021-08-21 力成科技股份有限公司 封裝結構
JP7450575B2 (ja) * 2021-03-18 2024-03-15 株式会社東芝 半導体装置及びその製造方法
WO2024203110A1 (ja) * 2023-03-24 2024-10-03 ローム株式会社 半導体装置、および半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3436159B2 (ja) * 1998-11-11 2003-08-11 松下電器産業株式会社 樹脂封止型半導体装置の製造方法
JP3046024B1 (ja) * 1999-04-23 2000-05-29 松下電子工業株式会社 リ―ドフレ―ムおよびそれを用いた樹脂封止型半導体装置の製造方法
JP5122835B2 (ja) * 2007-02-27 2013-01-16 ローム株式会社 半導体装置、リードフレームおよび半導体装置の製造方法
JP5126687B2 (ja) * 2009-02-16 2013-01-23 大日本印刷株式会社 樹脂封止型半導体装置、リードフレーム、リードフレームの製造方法、および樹脂封止型半導体装置の製造方法
JP5319571B2 (ja) * 2010-02-12 2013-10-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8389330B2 (en) * 2010-06-24 2013-03-05 Stats Chippac Ltd. Integrated circuit package system with package stand-off and method of manufacture thereof

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JP2017028200A (ja) 2017-02-02

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