JP6469554B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6469554B2 JP6469554B2 JP2015179683A JP2015179683A JP6469554B2 JP 6469554 B2 JP6469554 B2 JP 6469554B2 JP 2015179683 A JP2015179683 A JP 2015179683A JP 2015179683 A JP2015179683 A JP 2015179683A JP 6469554 B2 JP6469554 B2 JP 6469554B2
- Authority
- JP
- Japan
- Prior art keywords
- word line
- voltage
- semiconductor device
- pmos transistor
- driver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/18—Peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Multimedia (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015179683A JP6469554B2 (ja) | 2015-09-11 | 2015-09-11 | 半導体装置 |
| US15/212,162 US9721647B2 (en) | 2015-09-11 | 2016-07-15 | Semiconductor device |
| CN201610704791.5A CN106531206B (zh) | 2015-09-11 | 2016-08-22 | 半导体器件 |
| US15/627,535 US10255970B2 (en) | 2015-09-11 | 2017-06-20 | Semiconductor device |
| US16/145,342 US10354722B2 (en) | 2015-09-11 | 2018-09-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015179683A JP6469554B2 (ja) | 2015-09-11 | 2015-09-11 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017054570A JP2017054570A (ja) | 2017-03-16 |
| JP2017054570A5 JP2017054570A5 (enExample) | 2018-06-28 |
| JP6469554B2 true JP6469554B2 (ja) | 2019-02-13 |
Family
ID=58238935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015179683A Active JP6469554B2 (ja) | 2015-09-11 | 2015-09-11 | 半導体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (3) | US9721647B2 (enExample) |
| JP (1) | JP6469554B2 (enExample) |
| CN (1) | CN106531206B (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6469554B2 (ja) * | 2015-09-11 | 2019-02-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US9786363B1 (en) * | 2016-11-01 | 2017-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Word-line enable pulse generator, SRAM and method for adjusting word-line enable time of SRAM |
| US10943645B2 (en) * | 2018-07-31 | 2021-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd | Memory device with a booster word line |
| JP7270451B2 (ja) * | 2019-04-26 | 2023-05-10 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の駆動方法 |
| US11189336B2 (en) * | 2019-10-30 | 2021-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Word line driving device for minimizing RC delay |
| JP2021108307A (ja) | 2019-12-27 | 2021-07-29 | キオクシア株式会社 | 半導体記憶装置 |
| US11170830B2 (en) * | 2020-02-11 | 2021-11-09 | Taiwan Semiconductor Manufacturing Company Limited | Word line driver for low voltage operation |
| US11211113B1 (en) * | 2020-08-18 | 2021-12-28 | Micron Technology, Inc. | Integrated assemblies comprising wordlines having ends selectively shunted to low voltage for speed transitioning |
| KR20220058284A (ko) | 2020-10-30 | 2022-05-09 | 삼성전자주식회사 | 워드 라인 보조 셀을 갖는 셀 어레이를 포함하는 집적 회로 |
| US11521670B2 (en) * | 2020-11-12 | 2022-12-06 | Micron Technology, Inc. | Word lines coupled to pull-down transistors, and related devices, systems, and methods |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55150189A (en) * | 1979-05-10 | 1980-11-21 | Nec Corp | Memory circuit |
| JPS60226095A (ja) * | 1984-04-25 | 1985-11-11 | Hitachi Micro Comput Eng Ltd | 半導体記憶装置 |
| JPS63276793A (ja) * | 1987-05-07 | 1988-11-15 | Nec Ic Microcomput Syst Ltd | ワ−ド線駆動回路 |
| JPH06203579A (ja) * | 1993-01-08 | 1994-07-22 | Fujitsu Ltd | 出力回路及び記憶装置 |
| JP3908493B2 (ja) * | 2001-08-30 | 2007-04-25 | 株式会社東芝 | 電子回路及び半導体記憶装置 |
| JP4439167B2 (ja) * | 2002-08-30 | 2010-03-24 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US7064981B2 (en) * | 2004-08-04 | 2006-06-20 | Micron Technology, Inc. | NAND string wordline delay reduction |
| JP4912016B2 (ja) * | 2005-05-23 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| JP4631743B2 (ja) * | 2006-02-27 | 2011-02-16 | ソニー株式会社 | 半導体装置 |
| US7379354B2 (en) * | 2006-05-16 | 2008-05-27 | Texas Instruments Incorporated | Methods and apparatus to provide voltage control for SRAM write assist circuits |
| US7733686B2 (en) * | 2006-12-30 | 2010-06-08 | Texas Instruments Incorporated | Pulse width control for read and write assist for SRAM circuits |
| US8014226B2 (en) * | 2009-12-22 | 2011-09-06 | Arm Limited | Integrated circuit memory with word line driving helper circuits |
| JP2014067942A (ja) * | 2012-09-27 | 2014-04-17 | Toshiba Corp | 不揮発性半導体記憶装置 |
| JP2014099225A (ja) | 2012-11-14 | 2014-05-29 | Renesas Electronics Corp | 半導体装置 |
| JP6469554B2 (ja) * | 2015-09-11 | 2019-02-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2015
- 2015-09-11 JP JP2015179683A patent/JP6469554B2/ja active Active
-
2016
- 2016-07-15 US US15/212,162 patent/US9721647B2/en active Active
- 2016-08-22 CN CN201610704791.5A patent/CN106531206B/zh active Active
-
2017
- 2017-06-20 US US15/627,535 patent/US10255970B2/en active Active
-
2018
- 2018-09-28 US US16/145,342 patent/US10354722B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20170287553A1 (en) | 2017-10-05 |
| CN106531206A (zh) | 2017-03-22 |
| US20190035456A1 (en) | 2019-01-31 |
| CN106531206B (zh) | 2022-05-27 |
| US10354722B2 (en) | 2019-07-16 |
| US10255970B2 (en) | 2019-04-09 |
| US9721647B2 (en) | 2017-08-01 |
| JP2017054570A (ja) | 2017-03-16 |
| US20170076785A1 (en) | 2017-03-16 |
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